Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Ingenic JZ4740 "glue layer"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2013, Apelete Seketeli <apelete@seketeli.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/usb/role.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/usb/usb_phy_generic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include "musb_core.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) struct jz4740_glue {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 	struct platform_device	*pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 	struct musb		*musb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 	struct clk		*clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 	struct usb_role_switch	*role_sw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) static irqreturn_t jz4740_musb_interrupt(int irq, void *__hci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	unsigned long	flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	irqreturn_t	retval = IRQ_NONE, retval_dma = IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	struct musb	*musb = __hci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	if (IS_ENABLED(CONFIG_USB_INVENTRA_DMA) && musb->dma_controller)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 		retval_dma = dma_controller_irq(irq, musb->dma_controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	spin_lock_irqsave(&musb->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	 * The controller is gadget only, the state of the host mode IRQ bits is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	 * undefined. Mask them to make sure that the musb driver core will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	 * never see them set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	musb->int_usb &= MUSB_INTR_SUSPEND | MUSB_INTR_RESUME |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 			 MUSB_INTR_RESET | MUSB_INTR_SOF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	if (musb->int_usb || musb->int_tx || musb->int_rx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 		retval = musb_interrupt(musb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	spin_unlock_irqrestore(&musb->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	if (retval == IRQ_HANDLED || retval_dma == IRQ_HANDLED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 		return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) static struct musb_fifo_cfg jz4740_musb_fifo_cfg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 64, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) static const struct musb_hdrc_config jz4740_musb_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	/* Silicon does not implement USB OTG. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	.multipoint	= 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	/* Max EPs scanned, driver will decide which EP can be used. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	.num_eps	= 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	/* RAMbits needed to configure EPs from table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	.ram_bits	= 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	.fifo_cfg	= jz4740_musb_fifo_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	.fifo_cfg_size	= ARRAY_SIZE(jz4740_musb_fifo_cfg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) static int jz4740_musb_role_switch_set(struct usb_role_switch *sw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 				       enum usb_role role)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	struct jz4740_glue *glue = usb_role_switch_get_drvdata(sw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	struct usb_phy *phy = glue->musb->xceiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	switch (role) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	case USB_ROLE_NONE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 		atomic_notifier_call_chain(&phy->notifier, USB_EVENT_NONE, phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	case USB_ROLE_DEVICE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 		atomic_notifier_call_chain(&phy->notifier, USB_EVENT_VBUS, phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	case USB_ROLE_HOST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 		atomic_notifier_call_chain(&phy->notifier, USB_EVENT_ID, phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) static int jz4740_musb_init(struct musb *musb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	struct device *dev = musb->controller->parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	struct jz4740_glue *glue = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	struct usb_role_switch_desc role_sw_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 		.set = jz4740_musb_role_switch_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 		.driver_data = glue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 		.fwnode = dev_fwnode(dev),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	glue->musb = musb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	if (dev->of_node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 		musb->xceiv = devm_usb_get_phy_by_phandle(dev, "phys", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 		musb->xceiv = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	if (IS_ERR(musb->xceiv)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 		err = PTR_ERR(musb->xceiv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 		if (err != -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 			dev_err(dev, "No transceiver configured: %d", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	glue->role_sw = usb_role_switch_register(dev, &role_sw_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	if (IS_ERR(glue->role_sw)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 		dev_err(dev, "Failed to register USB role switch");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 		return PTR_ERR(glue->role_sw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	 * Silicon does not implement ConfigData register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	 * Set dyn_fifo to avoid reading EP config from hardware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	musb->dyn_fifo = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	musb->isr = jz4740_musb_interrupt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static int jz4740_musb_exit(struct musb *musb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	struct jz4740_glue *glue = dev_get_drvdata(musb->controller->parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	usb_role_switch_unregister(glue->role_sw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static const struct musb_platform_ops jz4740_musb_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	.quirks		= MUSB_DMA_INVENTRA | MUSB_INDEXED_EP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	.fifo_mode	= 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	.init		= jz4740_musb_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	.exit		= jz4740_musb_exit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #ifdef CONFIG_USB_INVENTRA_DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	.dma_init	= musbhs_dma_controller_create_noirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	.dma_exit	= musbhs_dma_controller_destroy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static const struct musb_hdrc_platform_data jz4740_musb_pdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	.mode		= MUSB_PERIPHERAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	.config		= &jz4740_musb_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	.platform_ops	= &jz4740_musb_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static struct musb_fifo_cfg jz4770_musb_fifo_cfg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	{ .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	{ .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	{ .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	{ .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	{ .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	{ .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static struct musb_hdrc_config jz4770_musb_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	.multipoint	= 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	.num_eps	= 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	.ram_bits	= 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	.fifo_cfg	= jz4770_musb_fifo_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	.fifo_cfg_size	= ARRAY_SIZE(jz4770_musb_fifo_cfg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) static const struct musb_hdrc_platform_data jz4770_musb_pdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	.mode		= MUSB_PERIPHERAL, /* TODO: support OTG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	.config		= &jz4770_musb_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	.platform_ops	= &jz4740_musb_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) static int jz4740_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	struct device			*dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	const struct musb_hdrc_platform_data *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	struct platform_device		*musb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	struct jz4740_glue		*glue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	struct clk			*clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	int				ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	glue = devm_kzalloc(dev, sizeof(*glue), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	if (!glue)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	pdata = of_device_get_match_data(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	if (!pdata) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 		dev_err(dev, "missing platform data");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	musb = platform_device_alloc("musb-hdrc", PLATFORM_DEVID_AUTO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	if (!musb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 		dev_err(dev, "failed to allocate musb device");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	clk = devm_clk_get(dev, "udc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 		dev_err(dev, "failed to get clock");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 		ret = PTR_ERR(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 		goto err_platform_device_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	ret = clk_prepare_enable(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 		dev_err(dev, "failed to enable clock");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 		goto err_platform_device_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	musb->dev.parent		= dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	musb->dev.dma_mask		= &musb->dev.coherent_dma_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	musb->dev.coherent_dma_mask	= DMA_BIT_MASK(32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	glue->pdev			= musb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	glue->clk			= clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	platform_set_drvdata(pdev, glue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	ret = platform_device_add_resources(musb, pdev->resource,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 					    pdev->num_resources);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 		dev_err(dev, "failed to add resources");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 		goto err_clk_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	ret = platform_device_add_data(musb, pdata, sizeof(*pdata));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 		dev_err(dev, "failed to add platform_data");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 		goto err_clk_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	ret = platform_device_add(musb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 		dev_err(dev, "failed to register musb device");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 		goto err_clk_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) err_clk_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	clk_disable_unprepare(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) err_platform_device_put:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	platform_device_put(musb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) static int jz4740_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	struct jz4740_glue *glue = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	platform_device_unregister(glue->pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	clk_disable_unprepare(glue->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) static const struct of_device_id jz4740_musb_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	{ .compatible = "ingenic,jz4740-musb", .data = &jz4740_musb_pdata },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	{ .compatible = "ingenic,jz4770-musb", .data = &jz4770_musb_pdata },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	{ /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) MODULE_DEVICE_TABLE(of, jz4740_musb_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) static struct platform_driver jz4740_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	.probe		= jz4740_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	.remove		= jz4740_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	.driver		= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 		.name	= "musb-jz4740",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 		.of_match_table = jz4740_musb_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) MODULE_DESCRIPTION("JZ4740 MUSB Glue Layer");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) MODULE_AUTHOR("Apelete Seketeli <apelete@seketeli.net>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) module_platform_driver(jz4740_driver);