^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2005-2006 by Texas Instruments
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #ifndef __MUSB_HDRDF_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define __MUSB_HDRDF_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * DaVinci-specific definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) /* Integrated highspeed/otg PHY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define USBPHY_CTL_PADDR 0x01c40034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define USBPHY_DATAPOL BIT(11) /* (dm355) switch D+/D- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define USBPHY_PHYCLKGD BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define USBPHY_SESNDEN BIT(7) /* v(sess_end) comparator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define USBPHY_VBDTCTEN BIT(6) /* v(bus) comparator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define USBPHY_VBUSSENS BIT(5) /* (dm355,ro) is vbus > 0.5V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define USBPHY_PHYPLLON BIT(4) /* override pll suspend */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define USBPHY_CLKO1SEL BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define USBPHY_OSCPDWN BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define USBPHY_OTGPDWN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define USBPHY_PHYPDWN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define DM355_DEEPSLEEP_PADDR 0x01c40048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define DRVVBUS_FORCE BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define DRVVBUS_OVERRIDE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* For now include usb OTG module registers here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define DAVINCI_USB_VERSION_REG 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define DAVINCI_USB_CTRL_REG 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define DAVINCI_USB_STAT_REG 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define DAVINCI_RNDIS_REG 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define DAVINCI_AUTOREQ_REG 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define DAVINCI_USB_INT_SOURCE_REG 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define DAVINCI_USB_INT_SET_REG 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define DAVINCI_USB_INT_SRC_CLR_REG 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define DAVINCI_USB_INT_MASK_REG 0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define DAVINCI_USB_INT_MASK_SET_REG 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define DAVINCI_USB_INT_MASK_CLR_REG 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define DAVINCI_USB_INT_SRC_MASKED_REG 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define DAVINCI_USB_EOI_REG 0x3c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define DAVINCI_USB_EOI_INTVEC 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* BEGIN CPPI-generic (?) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /* CPPI related registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define DAVINCI_TXCPPI_CTRL_REG 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define DAVINCI_TXCPPI_TEAR_REG 0x84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define DAVINCI_CPPI_EOI_REG 0x88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define DAVINCI_CPPI_INTVEC_REG 0x8c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define DAVINCI_TXCPPI_MASKED_REG 0x90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define DAVINCI_TXCPPI_RAW_REG 0x94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define DAVINCI_TXCPPI_INTENAB_REG 0x98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define DAVINCI_TXCPPI_INTCLR_REG 0x9c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define DAVINCI_RXCPPI_CTRL_REG 0xC0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define DAVINCI_RXCPPI_MASKED_REG 0xD0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define DAVINCI_RXCPPI_RAW_REG 0xD4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define DAVINCI_RXCPPI_INTENAB_REG 0xD8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define DAVINCI_RXCPPI_INTCLR_REG 0xDC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define DAVINCI_RXCPPI_BUFCNT0_REG 0xE0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define DAVINCI_RXCPPI_BUFCNT1_REG 0xE4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define DAVINCI_RXCPPI_BUFCNT2_REG 0xE8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define DAVINCI_RXCPPI_BUFCNT3_REG 0xEC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /* CPPI state RAM entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define DAVINCI_CPPI_STATERAM_BASE_OFFSET 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define DAVINCI_TXCPPI_STATERAM_OFFSET(chnum) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) (DAVINCI_CPPI_STATERAM_BASE_OFFSET + ((chnum) * 0x40))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define DAVINCI_RXCPPI_STATERAM_OFFSET(chnum) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) (DAVINCI_CPPI_STATERAM_BASE_OFFSET + 0x20 + ((chnum) * 0x40))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* CPPI masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define DAVINCI_DMA_CTRL_ENABLE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define DAVINCI_DMA_CTRL_DISABLE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define DAVINCI_DMA_ALL_CHANNELS_ENABLE 0xF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define DAVINCI_DMA_ALL_CHANNELS_DISABLE 0xF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /* END CPPI-generic (?) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define DAVINCI_USB_TX_ENDPTS_MASK 0x1f /* ep0 + 4 tx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define DAVINCI_USB_RX_ENDPTS_MASK 0x1e /* 4 rx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define DAVINCI_USB_USBINT_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define DAVINCI_USB_TXINT_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define DAVINCI_USB_RXINT_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define DAVINCI_INTR_DRVVBUS 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define DAVINCI_USB_USBINT_MASK 0x01ff0000 /* 8 Mentor, DRVVBUS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define DAVINCI_USB_TXINT_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) (DAVINCI_USB_TX_ENDPTS_MASK << DAVINCI_USB_TXINT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define DAVINCI_USB_RXINT_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) (DAVINCI_USB_RX_ENDPTS_MASK << DAVINCI_USB_RXINT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define DAVINCI_BASE_OFFSET 0x400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #endif /* __MUSB_HDRDF_H__ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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