^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2005-2006 by Texas Instruments
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * This file is part of the Inventra Controller Driver for Linux.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/list.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/usb/usb_phy_generic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <mach/cputype.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <mach/hardware.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <asm/mach-types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include "musb_core.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include "davinci.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include "cppi_dma.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define USB_PHY_CTRL IO_ADDRESS(USBPHY_CTL_PADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define DM355_DEEPSLEEP IO_ADDRESS(DM355_DEEPSLEEP_PADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) struct davinci_glue {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) struct platform_device *musb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) bool vbus_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) struct gpio_desc *vbus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) struct work_struct vbus_work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* REVISIT (PM) we should be able to keep the PHY in low power mode most
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * of the time (24 MHZ oscillator and PLL off, etc) by setting POWER.D0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * and, when in host mode, autosuspending idle root ports... PHYPLLON
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * (overriding SUSPENDM?) then likely needs to stay off.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) static inline void phy_on(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) u32 phy_ctrl = __raw_readl(USB_PHY_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* power everything up; start the on-chip PHY and its PLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) phy_ctrl &= ~(USBPHY_OSCPDWN | USBPHY_OTGPDWN | USBPHY_PHYPDWN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) phy_ctrl |= USBPHY_SESNDEN | USBPHY_VBDTCTEN | USBPHY_PHYPLLON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) __raw_writel(phy_ctrl, USB_PHY_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /* wait for PLL to lock before proceeding */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) while ((__raw_readl(USB_PHY_CTRL) & USBPHY_PHYCLKGD) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) static inline void phy_off(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) u32 phy_ctrl = __raw_readl(USB_PHY_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /* powerdown the on-chip PHY, its PLL, and the OTG block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) phy_ctrl &= ~(USBPHY_SESNDEN | USBPHY_VBDTCTEN | USBPHY_PHYPLLON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) phy_ctrl |= USBPHY_OSCPDWN | USBPHY_OTGPDWN | USBPHY_PHYPDWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) __raw_writel(phy_ctrl, USB_PHY_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) static int dma_off = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) static void davinci_musb_enable(struct musb *musb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) u32 tmp, old, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /* workaround: setup irqs through both register sets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) tmp = (musb->epmask & DAVINCI_USB_TX_ENDPTS_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) << DAVINCI_USB_TXINT_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) musb_writel(musb->ctrl_base, DAVINCI_USB_INT_MASK_SET_REG, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) old = tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) tmp = (musb->epmask & (0xfffe & DAVINCI_USB_RX_ENDPTS_MASK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) << DAVINCI_USB_RXINT_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) musb_writel(musb->ctrl_base, DAVINCI_USB_INT_MASK_SET_REG, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) tmp |= old;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) val = ~MUSB_INTR_SOF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) tmp |= ((val & 0x01ff) << DAVINCI_USB_USBINT_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) musb_writel(musb->ctrl_base, DAVINCI_USB_INT_MASK_SET_REG, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) if (is_dma_capable() && !dma_off)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) printk(KERN_WARNING "%s %s: dma not reactivated\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) __FILE__, __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) dma_off = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* force a DRVVBUS irq so we can start polling for ID change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) musb_writel(musb->ctrl_base, DAVINCI_USB_INT_SET_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) DAVINCI_INTR_DRVVBUS << DAVINCI_USB_USBINT_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * Disable the HDRC and flush interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static void davinci_musb_disable(struct musb *musb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /* because we don't set CTRLR.UINT, "important" to:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * - not read/write INTRUSB/INTRUSBE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * - (except during initial setup, as workaround)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * - use INTSETR/INTCLRR instead
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) musb_writel(musb->ctrl_base, DAVINCI_USB_INT_MASK_CLR_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) DAVINCI_USB_USBINT_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) | DAVINCI_USB_TXINT_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) | DAVINCI_USB_RXINT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) musb_writel(musb->ctrl_base, DAVINCI_USB_EOI_REG, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) if (is_dma_capable() && !dma_off)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) WARNING("dma still active\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define portstate(stmt) stmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * VBUS SWITCHING IS BOARD-SPECIFIC ... at least for the DM6446 EVM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * which doesn't wire DRVVBUS to the FET that switches it. Unclear
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * if that's a problem with the DM6446 chip or just with that board.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * In either case, the DM355 EVM automates DRVVBUS the normal way,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * when J10 is out, and TI documents it as handling OTG.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /* I2C operations are always synchronous, and require a task context.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) * With unloaded systems, using the shared workqueue seems to suffice
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) * to satisfy the 100msec A_WAIT_VRISE timeout...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static void evm_deferred_drvvbus(struct work_struct *work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) struct davinci_glue *glue = container_of(work, struct davinci_glue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) vbus_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) gpiod_set_value_cansleep(glue->vbus, glue->vbus_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) glue->vbus_state = !glue->vbus_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static void davinci_musb_source_power(struct musb *musb, int is_on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) int immediate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) struct davinci_glue *glue = dev_get_drvdata(musb->controller->parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /* This GPIO handling is entirely optional */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) if (!glue->vbus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) if (is_on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) is_on = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) if (glue->vbus_state == is_on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) /* 0/1 vs "-1 == unknown/init" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) glue->vbus_state = !is_on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) if (machine_is_davinci_evm()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) if (immediate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) gpiod_set_value_cansleep(glue->vbus, glue->vbus_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) schedule_work(&glue->vbus_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) if (immediate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) glue->vbus_state = is_on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) static void davinci_musb_set_vbus(struct musb *musb, int is_on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) WARN_ON(is_on && is_peripheral_active(musb));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) davinci_musb_source_power(musb, is_on, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define POLL_SECONDS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static void otg_timer(struct timer_list *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) struct musb *musb = from_timer(musb, t, dev_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) void __iomem *mregs = musb->mregs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) u8 devctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) /* We poll because DaVinci's won't expose several OTG-critical
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) * status change events (from the transceiver) otherwise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) devctl = musb_readb(mregs, MUSB_DEVCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) dev_dbg(musb->controller, "poll devctl %02x (%s)\n", devctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) usb_otg_state_string(musb->xceiv->otg->state));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) spin_lock_irqsave(&musb->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) switch (musb->xceiv->otg->state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) case OTG_STATE_A_WAIT_VFALL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) /* Wait till VBUS falls below SessionEnd (~0.2V); the 1.3 RTL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) * seems to mis-handle session "start" otherwise (or in our
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) * case "recover"), in routine "VBUS was valid by the time
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) * VBUSERR got reported during enumeration" cases.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) if (devctl & MUSB_DEVCTL_VBUS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) mod_timer(&musb->dev_timer, jiffies + POLL_SECONDS * HZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) musb->xceiv->otg->state = OTG_STATE_A_WAIT_VRISE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) musb_writel(musb->ctrl_base, DAVINCI_USB_INT_SET_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) MUSB_INTR_VBUSERROR << DAVINCI_USB_USBINT_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) case OTG_STATE_B_IDLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) * There's no ID-changed IRQ, so we have no good way to tell
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) * when to switch to the A-Default state machine (by setting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) * the DEVCTL.SESSION flag).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) * Workaround: whenever we're in B_IDLE, try setting the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) * session flag every few seconds. If it works, ID was
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) * grounded and we're now in the A-Default state machine.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) * NOTE setting the session flag is _supposed_ to trigger
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) * SRP, but clearly it doesn't.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) musb_writeb(mregs, MUSB_DEVCTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) devctl | MUSB_DEVCTL_SESSION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) devctl = musb_readb(mregs, MUSB_DEVCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) if (devctl & MUSB_DEVCTL_BDEVICE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) mod_timer(&musb->dev_timer, jiffies + POLL_SECONDS * HZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) musb->xceiv->otg->state = OTG_STATE_A_IDLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) spin_unlock_irqrestore(&musb->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) static irqreturn_t davinci_musb_interrupt(int irq, void *__hci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) irqreturn_t retval = IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) struct musb *musb = __hci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) struct usb_otg *otg = musb->xceiv->otg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) void __iomem *tibase = musb->ctrl_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) struct cppi *cppi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) spin_lock_irqsave(&musb->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) /* NOTE: DaVinci shadows the Mentor IRQs. Don't manage them through
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) * the Mentor registers (except for setup), use the TI ones and EOI.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) * Docs describe irq "vector" registers associated with the CPPI and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) * USB EOI registers. These hold a bitmask corresponding to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) * current IRQ, not an irq handler address. Would using those bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) * resolve some of the races observed in this dispatch code??
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) /* CPPI interrupts share the same IRQ line, but have their own
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) * mask, state, "vector", and EOI registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) cppi = container_of(musb->dma_controller, struct cppi, controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) if (is_cppi_enabled(musb) && musb->dma_controller && !cppi->irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) retval = cppi_interrupt(irq, __hci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) /* ack and handle non-CPPI interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) tmp = musb_readl(tibase, DAVINCI_USB_INT_SRC_MASKED_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) musb_writel(tibase, DAVINCI_USB_INT_SRC_CLR_REG, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) dev_dbg(musb->controller, "IRQ %08x\n", tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) musb->int_rx = (tmp & DAVINCI_USB_RXINT_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) >> DAVINCI_USB_RXINT_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) musb->int_tx = (tmp & DAVINCI_USB_TXINT_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) >> DAVINCI_USB_TXINT_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) musb->int_usb = (tmp & DAVINCI_USB_USBINT_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) >> DAVINCI_USB_USBINT_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) /* DRVVBUS irqs are the only proxy we have (a very poor one!) for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) * DaVinci's missing ID change IRQ. We need an ID change IRQ to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) * switch appropriately between halves of the OTG state machine.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) * Managing DEVCTL.SESSION per Mentor docs requires we know its
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) * value, but DEVCTL.BDEVICE is invalid without DEVCTL.SESSION set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) * Also, DRVVBUS pulses for SRP (but not at 5V) ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) if (tmp & (DAVINCI_INTR_DRVVBUS << DAVINCI_USB_USBINT_SHIFT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) int drvvbus = musb_readl(tibase, DAVINCI_USB_STAT_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) void __iomem *mregs = musb->mregs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) u8 devctl = musb_readb(mregs, MUSB_DEVCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) int err = musb->int_usb & MUSB_INTR_VBUSERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) err = musb->int_usb & MUSB_INTR_VBUSERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) /* The Mentor core doesn't debounce VBUS as needed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) * to cope with device connect current spikes. This
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) * means it's not uncommon for bus-powered devices
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) * to get VBUS errors during enumeration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) * This is a workaround, but newer RTL from Mentor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) * seems to allow a better one: "re"starting sessions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) * without waiting (on EVM, a **long** time) for VBUS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) * to stop registering in devctl.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) musb->int_usb &= ~MUSB_INTR_VBUSERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) musb->xceiv->otg->state = OTG_STATE_A_WAIT_VFALL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) mod_timer(&musb->dev_timer, jiffies + POLL_SECONDS * HZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) WARNING("VBUS error workaround (delay coming)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) } else if (drvvbus) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) MUSB_HST_MODE(musb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) musb->xceiv->otg->state = OTG_STATE_A_WAIT_VRISE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) portstate(musb->port1_status |= USB_PORT_STAT_POWER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) del_timer(&musb->dev_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) musb->is_active = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) MUSB_DEV_MODE(musb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) musb->xceiv->otg->state = OTG_STATE_B_IDLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) portstate(musb->port1_status &= ~USB_PORT_STAT_POWER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) /* NOTE: this must complete poweron within 100 msec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) * (OTG_TIME_A_WAIT_VRISE) but we don't check for that.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) davinci_musb_source_power(musb, drvvbus, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) dev_dbg(musb->controller, "VBUS %s (%s)%s, devctl %02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) drvvbus ? "on" : "off",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) usb_otg_state_string(musb->xceiv->otg->state),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) err ? " ERROR" : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) devctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) retval = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) if (musb->int_tx || musb->int_rx || musb->int_usb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) retval |= musb_interrupt(musb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) /* irq stays asserted until EOI is written */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) musb_writel(tibase, DAVINCI_USB_EOI_REG, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) /* poll for ID change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) if (musb->xceiv->otg->state == OTG_STATE_B_IDLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) mod_timer(&musb->dev_timer, jiffies + POLL_SECONDS * HZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) spin_unlock_irqrestore(&musb->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) static int davinci_musb_set_mode(struct musb *musb, u8 mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) /* EVM can't do this (right?) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) static int davinci_musb_init(struct musb *musb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) void __iomem *tibase = musb->ctrl_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) u32 revision;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) int ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) musb->xceiv = usb_get_phy(USB_PHY_TYPE_USB2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) if (IS_ERR_OR_NULL(musb->xceiv)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) ret = -EPROBE_DEFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) goto unregister;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) musb->mregs += DAVINCI_BASE_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) /* returns zero if e.g. not clocked */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) revision = musb_readl(tibase, DAVINCI_USB_VERSION_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) if (revision == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) timer_setup(&musb->dev_timer, otg_timer, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) davinci_musb_source_power(musb, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) /* dm355 EVM swaps D+/D- for signal integrity, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) * is clocked from the main 24 MHz crystal.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) if (machine_is_davinci_dm355_evm()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) u32 phy_ctrl = __raw_readl(USB_PHY_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) phy_ctrl &= ~(3 << 9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) phy_ctrl |= USBPHY_DATAPOL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) __raw_writel(phy_ctrl, USB_PHY_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) /* On dm355, the default-A state machine needs DRVVBUS control.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) * If we won't be a host, there's no need to turn it on.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) if (cpu_is_davinci_dm355()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) u32 deepsleep = __raw_readl(DM355_DEEPSLEEP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) deepsleep &= ~DRVVBUS_FORCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) __raw_writel(deepsleep, DM355_DEEPSLEEP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) /* reset the controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) musb_writel(tibase, DAVINCI_USB_CTRL_REG, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) /* start the on-chip PHY and its PLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) phy_on();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) msleep(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) /* NOTE: irqs are in mixed mode, not bypass to pure-musb */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) pr_debug("DaVinci OTG revision %08x phy %03x control %02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) revision, __raw_readl(USB_PHY_CTRL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) musb_readb(tibase, DAVINCI_USB_CTRL_REG));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) musb->isr = davinci_musb_interrupt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) usb_put_phy(musb->xceiv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) unregister:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) usb_phy_generic_unregister();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) static int davinci_musb_exit(struct musb *musb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) int maxdelay = 30;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) u8 devctl, warn = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) del_timer_sync(&musb->dev_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) /* force VBUS off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) if (cpu_is_davinci_dm355()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) u32 deepsleep = __raw_readl(DM355_DEEPSLEEP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) deepsleep &= ~DRVVBUS_FORCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) deepsleep |= DRVVBUS_OVERRIDE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) __raw_writel(deepsleep, DM355_DEEPSLEEP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) davinci_musb_source_power(musb, 0 /*off*/, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) * delay, to avoid problems with module reload.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) * if there's no peripheral connected, this can take a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) * long time to fall, especially on EVM with huge C133.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) if (!(devctl & MUSB_DEVCTL_VBUS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) if ((devctl & MUSB_DEVCTL_VBUS) != warn) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) warn = devctl & MUSB_DEVCTL_VBUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) dev_dbg(musb->controller, "VBUS %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) warn >> MUSB_DEVCTL_VBUS_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) msleep(1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) maxdelay--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) } while (maxdelay > 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) /* in OTG mode, another host might be connected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) if (devctl & MUSB_DEVCTL_VBUS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) dev_dbg(musb->controller, "VBUS off timeout (devctl %02x)\n", devctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) phy_off();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) usb_put_phy(musb->xceiv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) static const struct musb_platform_ops davinci_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) .quirks = MUSB_DMA_CPPI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) .init = davinci_musb_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) .exit = davinci_musb_exit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) #ifdef CONFIG_USB_TI_CPPI_DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) .dma_init = cppi_dma_controller_create,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) .dma_exit = cppi_dma_controller_destroy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) .enable = davinci_musb_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) .disable = davinci_musb_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) .set_mode = davinci_musb_set_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) .set_vbus = davinci_musb_set_vbus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) static const struct platform_device_info davinci_dev_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) .name = "musb-hdrc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) .id = PLATFORM_DEVID_AUTO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) .dma_mask = DMA_BIT_MASK(32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) static int davinci_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) struct resource musb_resources[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) struct musb_hdrc_platform_data *pdata = dev_get_platdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) struct platform_device *musb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) struct davinci_glue *glue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) struct platform_device_info pinfo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) int ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) glue = devm_kzalloc(&pdev->dev, sizeof(*glue), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) if (!glue)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) goto err0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) clk = devm_clk_get(&pdev->dev, "usb");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) dev_err(&pdev->dev, "failed to get clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) ret = PTR_ERR(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) goto err0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) ret = clk_enable(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) dev_err(&pdev->dev, "failed to enable clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) goto err0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) glue->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) glue->clk = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) pdata->platform_ops = &davinci_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) glue->vbus = devm_gpiod_get_optional(&pdev->dev, NULL, GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) if (IS_ERR(glue->vbus)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) ret = PTR_ERR(glue->vbus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) goto err0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) glue->vbus_state = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) INIT_WORK(&glue->vbus_work, evm_deferred_drvvbus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) usb_phy_generic_register();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) platform_set_drvdata(pdev, glue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) memset(musb_resources, 0x00, sizeof(*musb_resources) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) ARRAY_SIZE(musb_resources));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) musb_resources[0].name = pdev->resource[0].name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) musb_resources[0].start = pdev->resource[0].start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) musb_resources[0].end = pdev->resource[0].end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) musb_resources[0].flags = pdev->resource[0].flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) musb_resources[1].name = pdev->resource[1].name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) musb_resources[1].start = pdev->resource[1].start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) musb_resources[1].end = pdev->resource[1].end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) musb_resources[1].flags = pdev->resource[1].flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) * For DM6467 3 resources are passed. A placeholder for the 3rd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) * resource is always there, so it's safe to always copy it...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) musb_resources[2].name = pdev->resource[2].name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) musb_resources[2].start = pdev->resource[2].start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) musb_resources[2].end = pdev->resource[2].end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) musb_resources[2].flags = pdev->resource[2].flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) pinfo = davinci_dev_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) pinfo.parent = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) pinfo.res = musb_resources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) pinfo.num_res = ARRAY_SIZE(musb_resources);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) pinfo.data = pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) pinfo.size_data = sizeof(*pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) glue->musb = musb = platform_device_register_full(&pinfo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) if (IS_ERR(musb)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) ret = PTR_ERR(musb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) dev_err(&pdev->dev, "failed to register musb device: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) goto err1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) err1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) clk_disable(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) err0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) static int davinci_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) struct davinci_glue *glue = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) platform_device_unregister(glue->musb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) usb_phy_generic_unregister();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) clk_disable(glue->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) static struct platform_driver davinci_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) .probe = davinci_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) .remove = davinci_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) .name = "musb-davinci",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) MODULE_DESCRIPTION("DaVinci MUSB Glue Layer");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) module_platform_driver(davinci_driver);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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