^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /* Copyright (C) 2005-2006 by Texas Instruments */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) #ifndef _CPPI_DMA_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #define _CPPI_DMA_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/list.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/dmapool.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/dmaengine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include "musb_core.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include "musb_dma.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) /* CPPI RX/TX state RAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) struct cppi_tx_stateram {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) u32 tx_head; /* "DMA packet" head descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) u32 tx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) u32 tx_current; /* current descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) u32 tx_buf_current;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) u32 tx_info; /* flags, remaining buflen */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) u32 tx_rem_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) u32 tx_dummy; /* unused */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) u32 tx_complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) struct cppi_rx_stateram {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) u32 rx_skipbytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) u32 rx_head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) u32 rx_sop; /* "DMA packet" head descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) u32 rx_current; /* current descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) u32 rx_buf_current;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) u32 rx_len_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) u32 rx_cnt_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) u32 rx_complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /* hw_options bits in CPPI buffer descriptors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define CPPI_SOP_SET ((u32)(1 << 31))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define CPPI_EOP_SET ((u32)(1 << 30))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define CPPI_OWN_SET ((u32)(1 << 29)) /* owned by cppi */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define CPPI_EOQ_MASK ((u32)(1 << 28))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define CPPI_ZERO_SET ((u32)(1 << 23)) /* rx saw zlp; tx issues one */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define CPPI_RXABT_MASK ((u32)(1 << 19)) /* need more rx buffers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define CPPI_RECV_PKTLEN_MASK 0xFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define CPPI_BUFFER_LEN_MASK 0xFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define CPPI_TEAR_READY ((u32)(1 << 31))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /* CPPI data structure definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define CPPI_DESCRIPTOR_ALIGN 16 /* bytes; 5-dec docs say 4-byte align */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) struct cppi_descriptor {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /* hardware overlay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) u32 hw_next; /* next buffer descriptor Pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) u32 hw_bufp; /* i/o buffer pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) u32 hw_off_len; /* buffer_offset16, buffer_length16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) u32 hw_options; /* flags: SOP, EOP etc*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) struct cppi_descriptor *next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) dma_addr_t dma; /* address of this descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) u32 buflen; /* for RX: original buffer length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) } __attribute__ ((aligned(CPPI_DESCRIPTOR_ALIGN)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) struct cppi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* CPPI Channel Control structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct cppi_channel {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct dma_channel channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /* back pointer to the DMA controller structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct cppi *controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /* which direction of which endpoint? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) struct musb_hw_ep *hw_ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) bool transmit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) u8 index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /* DMA modes: RNDIS or "transparent" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) u8 is_rndis;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* book keeping for current transfer request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) dma_addr_t buf_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) u32 buf_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) u32 maxpacket;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) u32 offset; /* dma requested */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) void __iomem *state_ram; /* CPPI state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct cppi_descriptor *freelist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /* BD management fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) struct cppi_descriptor *head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) struct cppi_descriptor *tail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) struct cppi_descriptor *last_processed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /* use tx_complete in host role to track endpoints waiting for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * FIFONOTEMPTY to clear.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) struct list_head tx_complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* CPPI DMA controller object */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) struct cppi {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) struct dma_controller controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) void __iomem *mregs; /* Mentor regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) void __iomem *tibase; /* TI/CPPI regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) struct cppi_channel tx[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) struct cppi_channel rx[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) struct dma_pool *pool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) struct list_head tx_complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /* CPPI IRQ handler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) extern irqreturn_t cppi_interrupt(int, void *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) struct cppi41_dma_channel {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) struct dma_channel channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) struct cppi41_dma_controller *controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) struct musb_hw_ep *hw_ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) struct dma_chan *dc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) dma_cookie_t cookie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) u8 port_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) u8 is_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) u8 is_allocated;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) u8 usb_toggle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) dma_addr_t buf_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) u32 total_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) u32 prog_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) u32 transferred;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) u32 packet_sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) struct list_head tx_check;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) int tx_zlp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #endif /* end of ifndef _CPPI_DMA_H_ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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