Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Texas Instruments AM35x "glue layer"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Copyright (c) 2010, by Texas Instruments
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * Based on the DA8xx "glue layer" code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * Copyright (c) 2008-2009, MontaVista Software, Inc. <source@mvista.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  * This file is part of the Inventra Controller Driver for Linux.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/usb/usb_phy_generic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/platform_data/usb-omap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include "musb_core.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26)  * AM35x specific definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) /* USB 2.0 OTG module registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define USB_REVISION_REG	0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define USB_CTRL_REG		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define USB_STAT_REG		0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define USB_EMULATION_REG	0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) /* 0x10 Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define USB_AUTOREQ_REG		0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define USB_SRP_FIX_TIME_REG	0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define USB_TEARDOWN_REG	0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define EP_INTR_SRC_REG		0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define EP_INTR_SRC_SET_REG	0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define EP_INTR_SRC_CLEAR_REG	0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define EP_INTR_MASK_REG	0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define EP_INTR_MASK_SET_REG	0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define EP_INTR_MASK_CLEAR_REG	0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define EP_INTR_SRC_MASKED_REG	0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define CORE_INTR_SRC_REG	0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define CORE_INTR_SRC_SET_REG	0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define CORE_INTR_SRC_CLEAR_REG	0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define CORE_INTR_MASK_REG	0x4c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define CORE_INTR_MASK_SET_REG	0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define CORE_INTR_MASK_CLEAR_REG 0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define CORE_INTR_SRC_MASKED_REG 0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) /* 0x5c Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define USB_END_OF_INTR_REG	0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) /* Control register bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define AM35X_SOFT_RESET_MASK	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) /* USB interrupt register bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define AM35X_INTR_USB_SHIFT	16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define AM35X_INTR_USB_MASK	(0x1ff << AM35X_INTR_USB_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define AM35X_INTR_DRVVBUS	0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define AM35X_INTR_RX_SHIFT	16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define AM35X_INTR_TX_SHIFT	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define AM35X_TX_EP_MASK	0xffff		/* EP0 + 15 Tx EPs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define AM35X_RX_EP_MASK	0xfffe		/* 15 Rx EPs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define AM35X_TX_INTR_MASK	(AM35X_TX_EP_MASK << AM35X_INTR_TX_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define AM35X_RX_INTR_MASK	(AM35X_RX_EP_MASK << AM35X_INTR_RX_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define USB_MENTOR_CORE_OFFSET	0x400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) struct am35x_glue {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	struct device		*dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	struct platform_device	*musb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	struct platform_device	*phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	struct clk		*phy_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	struct clk		*clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79)  * am35x_musb_enable - enable interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) static void am35x_musb_enable(struct musb *musb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	void __iomem *reg_base = musb->ctrl_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	u32 epmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	/* Workaround: setup IRQs through both register sets. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	epmask = ((musb->epmask & AM35X_TX_EP_MASK) << AM35X_INTR_TX_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	       ((musb->epmask & AM35X_RX_EP_MASK) << AM35X_INTR_RX_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	musb_writel(reg_base, EP_INTR_MASK_SET_REG, epmask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	musb_writel(reg_base, CORE_INTR_MASK_SET_REG, AM35X_INTR_USB_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	/* Force the DRVVBUS IRQ so we can start polling for ID change. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	musb_writel(reg_base, CORE_INTR_SRC_SET_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 			AM35X_INTR_DRVVBUS << AM35X_INTR_USB_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99)  * am35x_musb_disable - disable HDRC and flush interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static void am35x_musb_disable(struct musb *musb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	void __iomem *reg_base = musb->ctrl_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	musb_writel(reg_base, CORE_INTR_MASK_CLEAR_REG, AM35X_INTR_USB_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	musb_writel(reg_base, EP_INTR_MASK_CLEAR_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 			 AM35X_TX_INTR_MASK | AM35X_RX_INTR_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	musb_writel(reg_base, USB_END_OF_INTR_REG, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define portstate(stmt)		stmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static void am35x_musb_set_vbus(struct musb *musb, int is_on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	WARN_ON(is_on && is_peripheral_active(musb));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define	POLL_SECONDS	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static void otg_timer(struct timer_list *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	struct musb		*musb = from_timer(musb, t, dev_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	void __iomem		*mregs = musb->mregs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	u8			devctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	unsigned long		flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	 * We poll because AM35x's won't expose several OTG-critical
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	 * status change events (from the transceiver) otherwise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	devctl = musb_readb(mregs, MUSB_DEVCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	dev_dbg(musb->controller, "Poll devctl %02x (%s)\n", devctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 		usb_otg_state_string(musb->xceiv->otg->state));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	spin_lock_irqsave(&musb->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	switch (musb->xceiv->otg->state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	case OTG_STATE_A_WAIT_BCON:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 		devctl &= ~MUSB_DEVCTL_SESSION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 		devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 		if (devctl & MUSB_DEVCTL_BDEVICE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 			musb->xceiv->otg->state = OTG_STATE_B_IDLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 			MUSB_DEV_MODE(musb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 		} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 			musb->xceiv->otg->state = OTG_STATE_A_IDLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 			MUSB_HST_MODE(musb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	case OTG_STATE_A_WAIT_VFALL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 		musb->xceiv->otg->state = OTG_STATE_A_WAIT_VRISE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 		musb_writel(musb->ctrl_base, CORE_INTR_SRC_SET_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 			    MUSB_INTR_VBUSERROR << AM35X_INTR_USB_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	case OTG_STATE_B_IDLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		devctl = musb_readb(mregs, MUSB_DEVCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 		if (devctl & MUSB_DEVCTL_BDEVICE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 			mod_timer(&musb->dev_timer, jiffies + POLL_SECONDS * HZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 			musb->xceiv->otg->state = OTG_STATE_A_IDLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	spin_unlock_irqrestore(&musb->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static void am35x_musb_try_idle(struct musb *musb, unsigned long timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	static unsigned long last_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	if (timeout == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 		timeout = jiffies + msecs_to_jiffies(3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	/* Never idle if active, or when VBUS timeout is not set as host */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	if (musb->is_active || (musb->a_wait_bcon == 0 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 				musb->xceiv->otg->state == OTG_STATE_A_WAIT_BCON)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 		dev_dbg(musb->controller, "%s active, deleting timer\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 			usb_otg_state_string(musb->xceiv->otg->state));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		del_timer(&musb->dev_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 		last_timer = jiffies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	if (time_after(last_timer, timeout) && timer_pending(&musb->dev_timer)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		dev_dbg(musb->controller, "Longer idle timer already pending, ignoring...\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	last_timer = timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	dev_dbg(musb->controller, "%s inactive, starting idle timer for %u ms\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 		usb_otg_state_string(musb->xceiv->otg->state),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 		jiffies_to_msecs(timeout - jiffies));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	mod_timer(&musb->dev_timer, timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static irqreturn_t am35x_musb_interrupt(int irq, void *hci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	struct musb  *musb = hci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	void __iomem *reg_base = musb->ctrl_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	struct device *dev = musb->controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	struct musb_hdrc_platform_data *plat = dev_get_platdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	struct omap_musb_board_data *data = plat->board_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	irqreturn_t ret = IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	u32 epintr, usbintr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	spin_lock_irqsave(&musb->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	/* Get endpoint interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	epintr = musb_readl(reg_base, EP_INTR_SRC_MASKED_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	if (epintr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 		musb_writel(reg_base, EP_INTR_SRC_CLEAR_REG, epintr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 		musb->int_rx =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 			(epintr & AM35X_RX_INTR_MASK) >> AM35X_INTR_RX_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 		musb->int_tx =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 			(epintr & AM35X_TX_INTR_MASK) >> AM35X_INTR_TX_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	/* Get usb core interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	usbintr = musb_readl(reg_base, CORE_INTR_SRC_MASKED_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	if (!usbintr && !epintr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 		goto eoi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	if (usbintr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 		musb_writel(reg_base, CORE_INTR_SRC_CLEAR_REG, usbintr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 		musb->int_usb =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 			(usbintr & AM35X_INTR_USB_MASK) >> AM35X_INTR_USB_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	 * DRVVBUS IRQs are the only proxy we have (a very poor one!) for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	 * AM35x's missing ID change IRQ.  We need an ID change IRQ to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	 * switch appropriately between halves of the OTG state machine.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	 * Managing DEVCTL.SESSION per Mentor docs requires that we know its
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	 * value but DEVCTL.BDEVICE is invalid without DEVCTL.SESSION set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	 * Also, DRVVBUS pulses for SRP (but not at 5V) ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	if (usbintr & (AM35X_INTR_DRVVBUS << AM35X_INTR_USB_SHIFT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 		int drvvbus = musb_readl(reg_base, USB_STAT_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 		void __iomem *mregs = musb->mregs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 		u8 devctl = musb_readb(mregs, MUSB_DEVCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 		int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 		err = musb->int_usb & MUSB_INTR_VBUSERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 		if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 			/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 			 * The Mentor core doesn't debounce VBUS as needed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 			 * to cope with device connect current spikes. This
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 			 * means it's not uncommon for bus-powered devices
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 			 * to get VBUS errors during enumeration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 			 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 			 * This is a workaround, but newer RTL from Mentor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 			 * seems to allow a better one: "re"-starting sessions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 			 * without waiting for VBUS to stop registering in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 			 * devctl.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 			 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 			musb->int_usb &= ~MUSB_INTR_VBUSERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 			musb->xceiv->otg->state = OTG_STATE_A_WAIT_VFALL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 			mod_timer(&musb->dev_timer, jiffies + POLL_SECONDS * HZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 			WARNING("VBUS error workaround (delay coming)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 		} else if (drvvbus) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 			MUSB_HST_MODE(musb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 			musb->xceiv->otg->state = OTG_STATE_A_WAIT_VRISE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 			portstate(musb->port1_status |= USB_PORT_STAT_POWER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 			del_timer(&musb->dev_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 		} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 			musb->is_active = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 			MUSB_DEV_MODE(musb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 			musb->xceiv->otg->state = OTG_STATE_B_IDLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 			portstate(musb->port1_status &= ~USB_PORT_STAT_POWER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 		/* NOTE: this must complete power-on within 100 ms. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 		dev_dbg(musb->controller, "VBUS %s (%s)%s, devctl %02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 				drvvbus ? "on" : "off",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 				usb_otg_state_string(musb->xceiv->otg->state),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 				err ? " ERROR" : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 				devctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 		ret = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	/* Drop spurious RX and TX if device is disconnected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	if (musb->int_usb & MUSB_INTR_DISCONNECT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 		musb->int_tx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 		musb->int_rx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	if (musb->int_tx || musb->int_rx || musb->int_usb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 		ret |= musb_interrupt(musb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) eoi:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	/* EOI needs to be written for the IRQ to be re-asserted. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	if (ret == IRQ_HANDLED || epintr || usbintr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 		/* clear level interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 		if (data->clear_irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 			data->clear_irq();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 		/* write EOI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 		musb_writel(reg_base, USB_END_OF_INTR_REG, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	/* Poll for ID change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	if (musb->xceiv->otg->state == OTG_STATE_B_IDLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 		mod_timer(&musb->dev_timer, jiffies + POLL_SECONDS * HZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	spin_unlock_irqrestore(&musb->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) static int am35x_musb_set_mode(struct musb *musb, u8 musb_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	struct device *dev = musb->controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	struct musb_hdrc_platform_data *plat = dev_get_platdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	struct omap_musb_board_data *data = plat->board_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	int     retval = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	if (data->set_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 		data->set_mode(musb_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 		retval = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) static int am35x_musb_init(struct musb *musb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	struct device *dev = musb->controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	struct musb_hdrc_platform_data *plat = dev_get_platdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	struct omap_musb_board_data *data = plat->board_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	void __iomem *reg_base = musb->ctrl_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	u32 rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	musb->mregs += USB_MENTOR_CORE_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	/* Returns zero if e.g. not clocked */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	rev = musb_readl(reg_base, USB_REVISION_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	if (!rev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	musb->xceiv = usb_get_phy(USB_PHY_TYPE_USB2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	if (IS_ERR_OR_NULL(musb->xceiv))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 		return -EPROBE_DEFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	timer_setup(&musb->dev_timer, otg_timer, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	/* Reset the musb */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	if (data->reset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 		data->reset();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	/* Reset the controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	musb_writel(reg_base, USB_CTRL_REG, AM35X_SOFT_RESET_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	/* Start the on-chip PHY and its PLL. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	if (data->set_phy_power)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 		data->set_phy_power(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	msleep(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	musb->isr = am35x_musb_interrupt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 	/* clear level interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	if (data->clear_irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 		data->clear_irq();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) static int am35x_musb_exit(struct musb *musb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	struct device *dev = musb->controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 	struct musb_hdrc_platform_data *plat = dev_get_platdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	struct omap_musb_board_data *data = plat->board_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 	del_timer_sync(&musb->dev_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	/* Shutdown the on-chip PHY and its PLL. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	if (data->set_phy_power)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 		data->set_phy_power(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 	usb_put_phy(musb->xceiv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) /* AM35x supports only 32bit read operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) static void am35x_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 	void __iomem *fifo = hw_ep->fifo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 	u32		val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 	int		i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 	/* Read for 32bit-aligned destination address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 	if (likely((0x03 & (unsigned long) dst) == 0) && len >= 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 		readsl(fifo, dst, len >> 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 		dst += len & ~0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 		len &= 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 	 * Now read the remaining 1 to 3 byte or complete length if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 	 * unaligned address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 	if (len > 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 		for (i = 0; i < (len >> 2); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 			*(u32 *) dst = musb_readl(fifo, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 			dst += 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 		len &= 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 	if (len > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 		val = musb_readl(fifo, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 		memcpy(dst, &val, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) static const struct musb_platform_ops am35x_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 	.quirks		= MUSB_DMA_INVENTRA | MUSB_INDEXED_EP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 	.init		= am35x_musb_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 	.exit		= am35x_musb_exit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 	.read_fifo	= am35x_read_fifo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) #ifdef CONFIG_USB_INVENTRA_DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 	.dma_init	= musbhs_dma_controller_create,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 	.dma_exit	= musbhs_dma_controller_destroy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 	.enable		= am35x_musb_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 	.disable	= am35x_musb_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 	.set_mode	= am35x_musb_set_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 	.try_idle	= am35x_musb_try_idle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 	.set_vbus	= am35x_musb_set_vbus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) static const struct platform_device_info am35x_dev_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 	.name		= "musb-hdrc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 	.id		= PLATFORM_DEVID_AUTO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 	.dma_mask	= DMA_BIT_MASK(32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) static int am35x_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 	struct musb_hdrc_platform_data	*pdata = dev_get_platdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 	struct platform_device		*musb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 	struct am35x_glue		*glue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 	struct platform_device_info	pinfo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 	struct clk			*phy_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 	struct clk			*clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 	int				ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 	glue = kzalloc(sizeof(*glue), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 	if (!glue)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 		goto err0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 	phy_clk = clk_get(&pdev->dev, "fck");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 	if (IS_ERR(phy_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) 		dev_err(&pdev->dev, "failed to get PHY clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 		ret = PTR_ERR(phy_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 		goto err3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) 	clk = clk_get(&pdev->dev, "ick");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) 	if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) 		dev_err(&pdev->dev, "failed to get clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) 		ret = PTR_ERR(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) 		goto err4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) 	ret = clk_enable(phy_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) 		dev_err(&pdev->dev, "failed to enable PHY clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) 		goto err5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) 	ret = clk_enable(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) 		dev_err(&pdev->dev, "failed to enable clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) 		goto err6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) 	glue->dev			= &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) 	glue->phy_clk			= phy_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) 	glue->clk			= clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) 	pdata->platform_ops		= &am35x_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) 	glue->phy = usb_phy_generic_register();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) 	if (IS_ERR(glue->phy)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) 		ret = PTR_ERR(glue->phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) 		goto err7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) 	platform_set_drvdata(pdev, glue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) 	pinfo = am35x_dev_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) 	pinfo.parent = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) 	pinfo.res = pdev->resource;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) 	pinfo.num_res = pdev->num_resources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) 	pinfo.data = pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) 	pinfo.size_data = sizeof(*pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) 	glue->musb = musb = platform_device_register_full(&pinfo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) 	if (IS_ERR(musb)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) 		ret = PTR_ERR(musb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) 		dev_err(&pdev->dev, "failed to register musb device: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) 		goto err8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) err8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) 	usb_phy_generic_unregister(glue->phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) err7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) 	clk_disable(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) err6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) 	clk_disable(phy_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) err5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) 	clk_put(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) err4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) 	clk_put(phy_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) err3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) 	kfree(glue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) err0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) static int am35x_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) 	struct am35x_glue	*glue = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) 	platform_device_unregister(glue->musb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) 	usb_phy_generic_unregister(glue->phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) 	clk_disable(glue->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) 	clk_disable(glue->phy_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) 	clk_put(glue->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) 	clk_put(glue->phy_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) 	kfree(glue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) static int am35x_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) 	struct am35x_glue	*glue = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) 	struct musb_hdrc_platform_data *plat = dev_get_platdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) 	struct omap_musb_board_data *data = plat->board_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) 	/* Shutdown the on-chip PHY and its PLL. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) 	if (data->set_phy_power)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) 		data->set_phy_power(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) 	clk_disable(glue->phy_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) 	clk_disable(glue->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) static int am35x_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) 	struct am35x_glue	*glue = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) 	struct musb_hdrc_platform_data *plat = dev_get_platdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) 	struct omap_musb_board_data *data = plat->board_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) 	int			ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) 	/* Start the on-chip PHY and its PLL. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) 	if (data->set_phy_power)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) 		data->set_phy_power(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) 	ret = clk_enable(glue->phy_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) 		dev_err(dev, "failed to enable PHY clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) 	ret = clk_enable(glue->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) 		dev_err(dev, "failed to enable clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) static SIMPLE_DEV_PM_OPS(am35x_pm_ops, am35x_suspend, am35x_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) static struct platform_driver am35x_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) 	.probe		= am35x_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) 	.remove		= am35x_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) 	.driver		= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) 		.name	= "musb-am35x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) 		.pm	= &am35x_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) MODULE_DESCRIPTION("AM35x MUSB Glue Layer");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) MODULE_AUTHOR("Ajay Kumar Gupta <ajay.gupta@ti.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) module_platform_driver(am35x_driver);