Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (C) 2016 MediaTek Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Author: Chunfeng Yun <chunfeng.yun@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/iopoll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include "mtu3.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include "mtu3_dr.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include "mtu3_debug.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) /* u2-port0 should be powered on and enabled; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) int ssusb_check_clocks(struct ssusb_mtk *ssusb, u32 ex_clks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 	void __iomem *ibase = ssusb->ippc_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 	u32 value, check_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	check_val = ex_clks | SSUSB_SYS125_RST_B_STS | SSUSB_SYSPLL_STABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 			SSUSB_REF_RST_B_STS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	ret = readl_poll_timeout(ibase + U3D_SSUSB_IP_PW_STS1, value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 			(check_val == (value & check_val)), 100, 20000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 		dev_err(ssusb->dev, "clks of sts1 are not stable!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	ret = readl_poll_timeout(ibase + U3D_SSUSB_IP_PW_STS2, value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 			(value & SSUSB_U2_MAC_SYS_RST_B_STS), 100, 10000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 		dev_err(ssusb->dev, "mac2 clock is not stable\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) static int ssusb_phy_init(struct ssusb_mtk *ssusb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	for (i = 0; i < ssusb->num_phys; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 		ret = phy_init(ssusb->phys[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 			goto exit_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) exit_phy:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	for (; i > 0; i--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 		phy_exit(ssusb->phys[i - 1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) static int ssusb_phy_exit(struct ssusb_mtk *ssusb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	for (i = 0; i < ssusb->num_phys; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 		phy_exit(ssusb->phys[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) static int ssusb_phy_power_on(struct ssusb_mtk *ssusb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	for (i = 0; i < ssusb->num_phys; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 		ret = phy_power_on(ssusb->phys[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 			goto power_off_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) power_off_phy:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	for (; i > 0; i--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 		phy_power_off(ssusb->phys[i - 1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) static void ssusb_phy_power_off(struct ssusb_mtk *ssusb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	for (i = 0; i < ssusb->num_phys; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 		phy_power_off(ssusb->phys[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static int ssusb_clks_enable(struct ssusb_mtk *ssusb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	ret = clk_prepare_enable(ssusb->sys_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 		dev_err(ssusb->dev, "failed to enable sys_clk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 		goto sys_clk_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	ret = clk_prepare_enable(ssusb->ref_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 		dev_err(ssusb->dev, "failed to enable ref_clk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 		goto ref_clk_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	ret = clk_prepare_enable(ssusb->mcu_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 		dev_err(ssusb->dev, "failed to enable mcu_clk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 		goto mcu_clk_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	ret = clk_prepare_enable(ssusb->dma_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 		dev_err(ssusb->dev, "failed to enable dma_clk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 		goto dma_clk_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) dma_clk_err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	clk_disable_unprepare(ssusb->mcu_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) mcu_clk_err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	clk_disable_unprepare(ssusb->ref_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) ref_clk_err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	clk_disable_unprepare(ssusb->sys_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) sys_clk_err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static void ssusb_clks_disable(struct ssusb_mtk *ssusb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	clk_disable_unprepare(ssusb->dma_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	clk_disable_unprepare(ssusb->mcu_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	clk_disable_unprepare(ssusb->ref_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	clk_disable_unprepare(ssusb->sys_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static int ssusb_rscs_init(struct ssusb_mtk *ssusb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	ret = regulator_enable(ssusb->vusb33);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 		dev_err(ssusb->dev, "failed to enable vusb33\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		goto vusb33_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	ret = ssusb_clks_enable(ssusb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 		goto clks_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	ret = ssusb_phy_init(ssusb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 		dev_err(ssusb->dev, "failed to init phy\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 		goto phy_init_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	ret = ssusb_phy_power_on(ssusb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 		dev_err(ssusb->dev, "failed to power on phy\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		goto phy_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) phy_err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	ssusb_phy_exit(ssusb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) phy_init_err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	ssusb_clks_disable(ssusb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) clks_err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	regulator_disable(ssusb->vusb33);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) vusb33_err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) static void ssusb_rscs_exit(struct ssusb_mtk *ssusb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	ssusb_clks_disable(ssusb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	regulator_disable(ssusb->vusb33);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	ssusb_phy_power_off(ssusb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	ssusb_phy_exit(ssusb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) static void ssusb_ip_sw_reset(struct ssusb_mtk *ssusb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	/* reset whole ip (xhci & u3d) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	mtu3_setbits(ssusb->ippc_base, U3D_SSUSB_IP_PW_CTRL0, SSUSB_IP_SW_RST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	mtu3_clrbits(ssusb->ippc_base, U3D_SSUSB_IP_PW_CTRL0, SSUSB_IP_SW_RST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	 * device ip may be powered on in firmware/BROM stage before entering
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	 * kernel stage;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	 * power down device ip, otherwise ip-sleep will fail when working as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	 * host only mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	mtu3_setbits(ssusb->ippc_base, U3D_SSUSB_IP_PW_CTRL2, SSUSB_IP_DEV_PDN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) static int get_ssusb_rscs(struct platform_device *pdev, struct ssusb_mtk *ssusb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	struct device_node *node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	struct otg_switch_mtk *otg_sx = &ssusb->otg_switch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	ssusb->vusb33 = devm_regulator_get(dev, "vusb33");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	if (IS_ERR(ssusb->vusb33)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 		dev_err(dev, "failed to get vusb33\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 		return PTR_ERR(ssusb->vusb33);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	ssusb->sys_clk = devm_clk_get(dev, "sys_ck");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	if (IS_ERR(ssusb->sys_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 		dev_err(dev, "failed to get sys clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 		return PTR_ERR(ssusb->sys_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	ssusb->ref_clk = devm_clk_get_optional(dev, "ref_ck");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	if (IS_ERR(ssusb->ref_clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 		return PTR_ERR(ssusb->ref_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	ssusb->mcu_clk = devm_clk_get_optional(dev, "mcu_ck");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	if (IS_ERR(ssusb->mcu_clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 		return PTR_ERR(ssusb->mcu_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	ssusb->dma_clk = devm_clk_get_optional(dev, "dma_ck");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	if (IS_ERR(ssusb->dma_clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 		return PTR_ERR(ssusb->dma_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	ssusb->num_phys = of_count_phandle_with_args(node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 			"phys", "#phy-cells");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	if (ssusb->num_phys > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 		ssusb->phys = devm_kcalloc(dev, ssusb->num_phys,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 					sizeof(*ssusb->phys), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 		if (!ssusb->phys)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 			return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 		ssusb->num_phys = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	for (i = 0; i < ssusb->num_phys; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 		ssusb->phys[i] = devm_of_phy_get_by_index(dev, node, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 		if (IS_ERR(ssusb->phys[i])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 			dev_err(dev, "failed to get phy-%d\n", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 			return PTR_ERR(ssusb->phys[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	ssusb->ippc_base = devm_platform_ioremap_resource_byname(pdev, "ippc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	if (IS_ERR(ssusb->ippc_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 		return PTR_ERR(ssusb->ippc_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	ssusb->dr_mode = usb_get_dr_mode(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	if (ssusb->dr_mode == USB_DR_MODE_UNKNOWN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 		ssusb->dr_mode = USB_DR_MODE_OTG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	if (ssusb->dr_mode == USB_DR_MODE_PERIPHERAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 		goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	/* if host role is supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	ret = ssusb_wakeup_of_property_parse(ssusb, node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 		dev_err(dev, "failed to parse uwk property\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	/* optional property, ignore the error if it does not exist */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	of_property_read_u32(node, "mediatek,u3p-dis-msk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 			     &ssusb->u3p_dis_msk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	otg_sx->vbus = devm_regulator_get(dev, "vbus");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	if (IS_ERR(otg_sx->vbus)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 		dev_err(dev, "failed to get vbus\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 		return PTR_ERR(otg_sx->vbus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	if (ssusb->dr_mode == USB_DR_MODE_HOST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 		goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	/* if dual-role mode is supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	otg_sx->is_u3_drd = of_property_read_bool(node, "mediatek,usb3-drd");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	otg_sx->manual_drd_enabled =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 		of_property_read_bool(node, "enable-manual-drd");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	otg_sx->role_sw_used = of_property_read_bool(node, "usb-role-switch");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	if (!otg_sx->role_sw_used && of_property_read_bool(node, "extcon")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 		otg_sx->edev = extcon_get_edev_by_phandle(ssusb->dev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 		if (IS_ERR(otg_sx->edev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 			dev_err(ssusb->dev, "couldn't get extcon device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 			return PTR_ERR(otg_sx->edev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	dev_info(dev, "dr_mode: %d, is_u3_dr: %d, u3p_dis_msk: %x, drd: %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 		ssusb->dr_mode, otg_sx->is_u3_drd, ssusb->u3p_dis_msk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 		otg_sx->manual_drd_enabled ? "manual" : "auto");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) static int mtu3_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	struct device_node *node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	struct ssusb_mtk *ssusb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	int ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	/* all elements are set to ZERO as default value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	ssusb = devm_kzalloc(dev, sizeof(*ssusb), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	if (!ssusb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 		dev_err(dev, "No suitable DMA config available\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 		return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	platform_set_drvdata(pdev, ssusb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	ssusb->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	ret = get_ssusb_rscs(pdev, ssusb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	ssusb_debugfs_create_root(ssusb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	/* enable power domain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	pm_runtime_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	pm_runtime_get_sync(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	device_enable_async_suspend(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	ret = ssusb_rscs_init(ssusb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 		goto comm_init_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	ssusb_ip_sw_reset(ssusb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	if (IS_ENABLED(CONFIG_USB_MTU3_HOST))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 		ssusb->dr_mode = USB_DR_MODE_HOST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	else if (IS_ENABLED(CONFIG_USB_MTU3_GADGET))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 		ssusb->dr_mode = USB_DR_MODE_PERIPHERAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	/* default as host */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	ssusb->is_host = !(ssusb->dr_mode == USB_DR_MODE_PERIPHERAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 	switch (ssusb->dr_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	case USB_DR_MODE_PERIPHERAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 		ret = ssusb_gadget_init(ssusb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 		if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 			dev_err(dev, "failed to initialize gadget\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 			goto comm_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	case USB_DR_MODE_HOST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 		ret = ssusb_host_init(ssusb, node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 		if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 			dev_err(dev, "failed to initialize host\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 			goto comm_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	case USB_DR_MODE_OTG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 		ret = ssusb_gadget_init(ssusb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 		if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 			dev_err(dev, "failed to initialize gadget\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 			goto comm_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 		ret = ssusb_host_init(ssusb, node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 		if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 			dev_err(dev, "failed to initialize host\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 			goto gadget_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 		ret = ssusb_otg_switch_init(ssusb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 		if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 			dev_err(dev, "failed to initialize switch\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 			goto host_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 		dev_err(dev, "unsupported mode: %d\n", ssusb->dr_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 		ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 		goto comm_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) host_exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 	ssusb_host_exit(ssusb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) gadget_exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 	ssusb_gadget_exit(ssusb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) comm_exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 	ssusb_rscs_exit(ssusb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) comm_init_err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 	pm_runtime_put_sync(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 	pm_runtime_disable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 	ssusb_debugfs_remove_root(ssusb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) static int mtu3_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 	struct ssusb_mtk *ssusb = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 	switch (ssusb->dr_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 	case USB_DR_MODE_PERIPHERAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 		ssusb_gadget_exit(ssusb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 	case USB_DR_MODE_HOST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 		ssusb_host_exit(ssusb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 	case USB_DR_MODE_OTG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 		ssusb_otg_switch_exit(ssusb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 		ssusb_gadget_exit(ssusb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 		ssusb_host_exit(ssusb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 	ssusb_rscs_exit(ssusb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 	pm_runtime_put_sync(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 	pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 	ssusb_debugfs_remove_root(ssusb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)  * when support dual-role mode, we reject suspend when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)  * it works as device mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) static int __maybe_unused mtu3_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 	struct ssusb_mtk *ssusb = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 	dev_dbg(dev, "%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 	/* REVISIT: disconnect it for only device mode? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 	if (!ssusb->is_host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 	ssusb_host_disable(ssusb, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) 	ssusb_phy_power_off(ssusb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 	ssusb_clks_disable(ssusb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) 	ssusb_wakeup_set(ssusb, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) static int __maybe_unused mtu3_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) 	struct ssusb_mtk *ssusb = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) 	dev_dbg(dev, "%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) 	if (!ssusb->is_host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) 	ssusb_wakeup_set(ssusb, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) 	ret = ssusb_clks_enable(ssusb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) 		goto clks_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) 	ret = ssusb_phy_power_on(ssusb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) 		goto phy_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) 	ssusb_host_enable(ssusb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) phy_err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) 	ssusb_clks_disable(ssusb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) clks_err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) static const struct dev_pm_ops mtu3_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) 	SET_SYSTEM_SLEEP_PM_OPS(mtu3_suspend, mtu3_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) #define DEV_PM_OPS (IS_ENABLED(CONFIG_PM) ? &mtu3_pm_ops : NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) #ifdef CONFIG_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) static const struct of_device_id mtu3_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) 	{.compatible = "mediatek,mt8173-mtu3",},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) 	{.compatible = "mediatek,mtu3",},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) 	{},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) MODULE_DEVICE_TABLE(of, mtu3_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) static struct platform_driver mtu3_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) 	.probe = mtu3_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) 	.remove = mtu3_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) 		.name = MTU3_DRIVER_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) 		.pm = DEV_PM_OPS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) 		.of_match_table = of_match_ptr(mtu3_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) module_platform_driver(mtu3_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) MODULE_AUTHOR("Chunfeng Yun <chunfeng.yun@mediatek.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) MODULE_DESCRIPTION("MediaTek USB3 DRD Controller Driver");