^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * mtu3_dr.c - dual role switch and host glue layer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2016 MediaTek Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author: Chunfeng Yun <chunfeng.yun@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/iopoll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "mtu3.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "mtu3_dr.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /* mt8173 etc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define PERI_WK_CTRL1 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define WC1_IS_C(x) (((x) & 0xf) << 26) /* cycle debounce */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define WC1_IS_EN BIT(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define WC1_IS_P BIT(6) /* polarity for ip sleep */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /* mt2712 etc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define PERI_SSUSB_SPM_CTRL 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define SSC_IP_SLEEP_EN BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define SSC_SPM_INT_EN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) enum ssusb_uwk_vers {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) SSUSB_UWK_V1 = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) SSUSB_UWK_V2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * ip-sleep wakeup mode:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * all clocks can be turn off, but power domain should be kept on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) static void ssusb_wakeup_ip_sleep_set(struct ssusb_mtk *ssusb, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) u32 reg, msk, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) switch (ssusb->uwk_vers) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) case SSUSB_UWK_V1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) reg = ssusb->uwk_reg_base + PERI_WK_CTRL1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) msk = WC1_IS_EN | WC1_IS_C(0xf) | WC1_IS_P;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) val = enable ? (WC1_IS_EN | WC1_IS_C(0x8)) : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) case SSUSB_UWK_V2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) reg = ssusb->uwk_reg_base + PERI_SSUSB_SPM_CTRL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) msk = SSC_IP_SLEEP_EN | SSC_SPM_INT_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) val = enable ? msk : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) regmap_update_bits(ssusb->uwk, reg, msk, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) int ssusb_wakeup_of_property_parse(struct ssusb_mtk *ssusb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) struct device_node *dn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) struct of_phandle_args args;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /* wakeup function is optional */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) ssusb->uwk_en = of_property_read_bool(dn, "wakeup-source");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) if (!ssusb->uwk_en)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) ret = of_parse_phandle_with_fixed_args(dn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) "mediatek,syscon-wakeup", 2, 0, &args);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) ssusb->uwk_reg_base = args.args[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) ssusb->uwk_vers = args.args[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) ssusb->uwk = syscon_node_to_regmap(args.np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) of_node_put(args.np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) dev_info(ssusb->dev, "uwk - reg:0x%x, version:%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) ssusb->uwk_reg_base, ssusb->uwk_vers);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) return PTR_ERR_OR_ZERO(ssusb->uwk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) void ssusb_wakeup_set(struct ssusb_mtk *ssusb, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) if (ssusb->uwk_en)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) ssusb_wakeup_ip_sleep_set(ssusb, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) static void host_ports_num_get(struct ssusb_mtk *ssusb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) u32 xhci_cap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) xhci_cap = mtu3_readl(ssusb->ippc_base, U3D_SSUSB_IP_XHCI_CAP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) ssusb->u2_ports = SSUSB_IP_XHCI_U2_PORT_NUM(xhci_cap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) ssusb->u3_ports = SSUSB_IP_XHCI_U3_PORT_NUM(xhci_cap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) dev_dbg(ssusb->dev, "host - u2_ports:%d, u3_ports:%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) ssusb->u2_ports, ssusb->u3_ports);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /* only configure ports will be used later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) int ssusb_host_enable(struct ssusb_mtk *ssusb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) void __iomem *ibase = ssusb->ippc_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) int num_u3p = ssusb->u3_ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) int num_u2p = ssusb->u2_ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) int u3_ports_disabed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) u32 check_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /* power on host ip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) mtu3_clrbits(ibase, U3D_SSUSB_IP_PW_CTRL1, SSUSB_IP_HOST_PDN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /* power on and enable u3 ports except skipped ones */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) u3_ports_disabed = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) for (i = 0; i < num_u3p; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) if ((0x1 << i) & ssusb->u3p_dis_msk) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) u3_ports_disabed++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) value = mtu3_readl(ibase, SSUSB_U3_CTRL(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) value &= ~(SSUSB_U3_PORT_PDN | SSUSB_U3_PORT_DIS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) value |= SSUSB_U3_PORT_HOST_SEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) mtu3_writel(ibase, SSUSB_U3_CTRL(i), value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /* power on and enable all u2 ports */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) for (i = 0; i < num_u2p; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) value = mtu3_readl(ibase, SSUSB_U2_CTRL(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) value &= ~(SSUSB_U2_PORT_PDN | SSUSB_U2_PORT_DIS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) value |= SSUSB_U2_PORT_HOST_SEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) mtu3_writel(ibase, SSUSB_U2_CTRL(i), value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) check_clk = SSUSB_XHCI_RST_B_STS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) if (num_u3p > u3_ports_disabed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) check_clk = SSUSB_U3_MAC_RST_B_STS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) return ssusb_check_clocks(ssusb, check_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) int ssusb_host_disable(struct ssusb_mtk *ssusb, bool suspend)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) void __iomem *ibase = ssusb->ippc_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) int num_u3p = ssusb->u3_ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) int num_u2p = ssusb->u2_ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /* power down and disable u3 ports except skipped ones */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) for (i = 0; i < num_u3p; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) if ((0x1 << i) & ssusb->u3p_dis_msk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) value = mtu3_readl(ibase, SSUSB_U3_CTRL(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) value |= SSUSB_U3_PORT_PDN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) value |= suspend ? 0 : SSUSB_U3_PORT_DIS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) mtu3_writel(ibase, SSUSB_U3_CTRL(i), value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /* power down and disable all u2 ports */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) for (i = 0; i < num_u2p; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) value = mtu3_readl(ibase, SSUSB_U2_CTRL(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) value |= SSUSB_U2_PORT_PDN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) value |= suspend ? 0 : SSUSB_U2_PORT_DIS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) mtu3_writel(ibase, SSUSB_U2_CTRL(i), value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /* power down host ip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) mtu3_setbits(ibase, U3D_SSUSB_IP_PW_CTRL1, SSUSB_IP_HOST_PDN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) if (!suspend)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /* wait for host ip to sleep */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) ret = readl_poll_timeout(ibase + U3D_SSUSB_IP_PW_STS1, value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) (value & SSUSB_IP_SLEEP_STS), 100, 100000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) dev_err(ssusb->dev, "ip sleep failed!!!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static void ssusb_host_setup(struct ssusb_mtk *ssusb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) struct otg_switch_mtk *otg_sx = &ssusb->otg_switch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) host_ports_num_get(ssusb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) * power on host and power on/enable all ports
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) * if support OTG, gadget driver will switch port0 to device mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) ssusb_host_enable(ssusb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) if (otg_sx->manual_drd_enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) ssusb_set_force_mode(ssusb, MTU3_DR_FORCE_HOST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /* if port0 supports dual-role, works as host mode by default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) ssusb_set_vbus(&ssusb->otg_switch, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) static void ssusb_host_cleanup(struct ssusb_mtk *ssusb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) if (ssusb->is_host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) ssusb_set_vbus(&ssusb->otg_switch, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) ssusb_host_disable(ssusb, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) * If host supports multiple ports, the VBUSes(5V) of ports except port0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) * which supports OTG are better to be enabled by default in DTS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) * Because the host driver will keep link with devices attached when system
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) * enters suspend mode, so no need to control VBUSes after initialization.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) int ssusb_host_init(struct ssusb_mtk *ssusb, struct device_node *parent_dn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) struct device *parent_dev = ssusb->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) ssusb_host_setup(ssusb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) ret = of_platform_populate(parent_dn, NULL, NULL, parent_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) dev_dbg(parent_dev, "failed to create child devices at %pOF\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) parent_dn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) dev_info(parent_dev, "xHCI platform device register success...\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) void ssusb_host_exit(struct ssusb_mtk *ssusb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) of_platform_depopulate(ssusb->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) ssusb_host_cleanup(ssusb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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