Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * mtu3_dr.c - dual role switch and host glue layer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2016 MediaTek Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Author: Chunfeng Yun <chunfeng.yun@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/usb/role.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include "mtu3.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include "mtu3_dr.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include "mtu3_debug.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define USB2_PORT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define USB3_PORT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) enum mtu3_vbus_id_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 	MTU3_ID_FLOAT = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 	MTU3_ID_GROUND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 	MTU3_VBUS_OFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 	MTU3_VBUS_VALID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) static char *mailbox_state_string(enum mtu3_vbus_id_state state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	switch (state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	case MTU3_ID_FLOAT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 		return "ID_FLOAT";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	case MTU3_ID_GROUND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 		return "ID_GROUND";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	case MTU3_VBUS_OFF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 		return "VBUS_OFF";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	case MTU3_VBUS_VALID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 		return "VBUS_VALID";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 		return "UNKNOWN";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) static void toggle_opstate(struct ssusb_mtk *ssusb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	if (!ssusb->otg_switch.is_u3_drd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 		mtu3_setbits(ssusb->mac_base, U3D_DEVICE_CONTROL, DC_SESSION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 		mtu3_setbits(ssusb->mac_base, U3D_POWER_MANAGEMENT, SOFT_CONN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) /* only port0 supports dual-role mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) static int ssusb_port0_switch(struct ssusb_mtk *ssusb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	int version, bool tohost)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	void __iomem *ibase = ssusb->ippc_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	dev_dbg(ssusb->dev, "%s (switch u%d port0 to %s)\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 		version, tohost ? "host" : "device");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	if (version == USB2_PORT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 		/* 1. power off and disable u2 port0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 		value = mtu3_readl(ibase, SSUSB_U2_CTRL(0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 		value |= SSUSB_U2_PORT_PDN | SSUSB_U2_PORT_DIS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 		mtu3_writel(ibase, SSUSB_U2_CTRL(0), value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 		/* 2. power on, enable u2 port0 and select its mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 		value = mtu3_readl(ibase, SSUSB_U2_CTRL(0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 		value &= ~(SSUSB_U2_PORT_PDN | SSUSB_U2_PORT_DIS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 		value = tohost ? (value | SSUSB_U2_PORT_HOST_SEL) :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 			(value & (~SSUSB_U2_PORT_HOST_SEL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 		mtu3_writel(ibase, SSUSB_U2_CTRL(0), value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 		/* 1. power off and disable u3 port0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 		value = mtu3_readl(ibase, SSUSB_U3_CTRL(0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 		value |= SSUSB_U3_PORT_PDN | SSUSB_U3_PORT_DIS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 		mtu3_writel(ibase, SSUSB_U3_CTRL(0), value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 		/* 2. power on, enable u3 port0 and select its mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 		value = mtu3_readl(ibase, SSUSB_U3_CTRL(0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 		value &= ~(SSUSB_U3_PORT_PDN | SSUSB_U3_PORT_DIS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 		value = tohost ? (value | SSUSB_U3_PORT_HOST_SEL) :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 			(value & (~SSUSB_U3_PORT_HOST_SEL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 		mtu3_writel(ibase, SSUSB_U3_CTRL(0), value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) static void switch_port_to_host(struct ssusb_mtk *ssusb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	u32 check_clk = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	dev_dbg(ssusb->dev, "%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	ssusb_port0_switch(ssusb, USB2_PORT, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	if (ssusb->otg_switch.is_u3_drd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 		ssusb_port0_switch(ssusb, USB3_PORT, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 		check_clk = SSUSB_U3_MAC_RST_B_STS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	ssusb_check_clocks(ssusb, check_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	/* after all clocks are stable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	toggle_opstate(ssusb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static void switch_port_to_device(struct ssusb_mtk *ssusb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	u32 check_clk = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	dev_dbg(ssusb->dev, "%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	ssusb_port0_switch(ssusb, USB2_PORT, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	if (ssusb->otg_switch.is_u3_drd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 		ssusb_port0_switch(ssusb, USB3_PORT, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 		check_clk = SSUSB_U3_MAC_RST_B_STS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	ssusb_check_clocks(ssusb, check_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) int ssusb_set_vbus(struct otg_switch_mtk *otg_sx, int is_on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	struct ssusb_mtk *ssusb =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 		container_of(otg_sx, struct ssusb_mtk, otg_switch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	struct regulator *vbus = otg_sx->vbus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	/* vbus is optional */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	if (!vbus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	dev_dbg(ssusb->dev, "%s: turn %s\n", __func__, is_on ? "on" : "off");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	if (is_on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 		ret = regulator_enable(vbus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 			dev_err(ssusb->dev, "vbus regulator enable failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 		regulator_disable(vbus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)  * switch to host: -> MTU3_VBUS_OFF --> MTU3_ID_GROUND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)  * switch to device: -> MTU3_ID_FLOAT --> MTU3_VBUS_VALID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static void ssusb_set_mailbox(struct otg_switch_mtk *otg_sx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	enum mtu3_vbus_id_state status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	struct ssusb_mtk *ssusb =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 		container_of(otg_sx, struct ssusb_mtk, otg_switch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	struct mtu3 *mtu = ssusb->u3d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	dev_dbg(ssusb->dev, "mailbox %s\n", mailbox_state_string(status));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	mtu3_dbg_trace(ssusb->dev, "mailbox %s", mailbox_state_string(status));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	switch (status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	case MTU3_ID_GROUND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 		switch_port_to_host(ssusb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 		ssusb_set_vbus(otg_sx, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 		ssusb->is_host = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	case MTU3_ID_FLOAT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 		ssusb->is_host = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 		ssusb_set_vbus(otg_sx, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 		switch_port_to_device(ssusb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	case MTU3_VBUS_OFF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 		mtu3_stop(mtu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 		pm_relax(ssusb->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	case MTU3_VBUS_VALID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		/* avoid suspend when works as device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 		pm_stay_awake(ssusb->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		mtu3_start(mtu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 		dev_err(ssusb->dev, "invalid state\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static void ssusb_id_work(struct work_struct *work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	struct otg_switch_mtk *otg_sx =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 		container_of(work, struct otg_switch_mtk, id_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	if (otg_sx->id_event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 		ssusb_set_mailbox(otg_sx, MTU3_ID_GROUND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 		ssusb_set_mailbox(otg_sx, MTU3_ID_FLOAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static void ssusb_vbus_work(struct work_struct *work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	struct otg_switch_mtk *otg_sx =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 		container_of(work, struct otg_switch_mtk, vbus_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	if (otg_sx->vbus_event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 		ssusb_set_mailbox(otg_sx, MTU3_VBUS_VALID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 		ssusb_set_mailbox(otg_sx, MTU3_VBUS_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)  * @ssusb_id_notifier is called in atomic context, but @ssusb_set_mailbox
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)  * may sleep, so use work queue here
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) static int ssusb_id_notifier(struct notifier_block *nb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	unsigned long event, void *ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	struct otg_switch_mtk *otg_sx =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 		container_of(nb, struct otg_switch_mtk, id_nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	otg_sx->id_event = event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	schedule_work(&otg_sx->id_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	return NOTIFY_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) static int ssusb_vbus_notifier(struct notifier_block *nb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	unsigned long event, void *ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	struct otg_switch_mtk *otg_sx =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 		container_of(nb, struct otg_switch_mtk, vbus_nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	otg_sx->vbus_event = event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	schedule_work(&otg_sx->vbus_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	return NOTIFY_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static int ssusb_extcon_register(struct otg_switch_mtk *otg_sx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	struct ssusb_mtk *ssusb =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 		container_of(otg_sx, struct ssusb_mtk, otg_switch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	struct extcon_dev *edev = otg_sx->edev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	/* extcon is optional */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	if (!edev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	otg_sx->vbus_nb.notifier_call = ssusb_vbus_notifier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	ret = devm_extcon_register_notifier(ssusb->dev, edev, EXTCON_USB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 					&otg_sx->vbus_nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 		dev_err(ssusb->dev, "failed to register notifier for USB\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	otg_sx->id_nb.notifier_call = ssusb_id_notifier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	ret = devm_extcon_register_notifier(ssusb->dev, edev, EXTCON_USB_HOST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 					&otg_sx->id_nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 		dev_err(ssusb->dev, "failed to register notifier for USB-HOST\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	dev_dbg(ssusb->dev, "EXTCON_USB: %d, EXTCON_USB_HOST: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 		extcon_get_state(edev, EXTCON_USB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 		extcon_get_state(edev, EXTCON_USB_HOST));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	/* default as host, switch to device mode if needed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	if (extcon_get_state(edev, EXTCON_USB_HOST) == false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 		ssusb_set_mailbox(otg_sx, MTU3_ID_FLOAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	if (extcon_get_state(edev, EXTCON_USB) == true)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 		ssusb_set_mailbox(otg_sx, MTU3_VBUS_VALID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)  * We provide an interface via debugfs to switch between host and device modes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)  * depending on user input.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)  * This is useful in special cases, such as uses TYPE-A receptacle but also
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)  * wants to support dual-role mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) void ssusb_mode_switch(struct ssusb_mtk *ssusb, int to_host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	struct otg_switch_mtk *otg_sx = &ssusb->otg_switch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	if (to_host) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 		ssusb_set_force_mode(ssusb, MTU3_DR_FORCE_HOST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 		ssusb_set_mailbox(otg_sx, MTU3_VBUS_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 		ssusb_set_mailbox(otg_sx, MTU3_ID_GROUND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 		ssusb_set_force_mode(ssusb, MTU3_DR_FORCE_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 		ssusb_set_mailbox(otg_sx, MTU3_ID_FLOAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 		ssusb_set_mailbox(otg_sx, MTU3_VBUS_VALID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) void ssusb_set_force_mode(struct ssusb_mtk *ssusb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 			  enum mtu3_dr_force_mode mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	value = mtu3_readl(ssusb->ippc_base, SSUSB_U2_CTRL(0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	switch (mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	case MTU3_DR_FORCE_DEVICE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 		value |= SSUSB_U2_PORT_FORCE_IDDIG | SSUSB_U2_PORT_RG_IDDIG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	case MTU3_DR_FORCE_HOST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 		value |= SSUSB_U2_PORT_FORCE_IDDIG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 		value &= ~SSUSB_U2_PORT_RG_IDDIG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	case MTU3_DR_FORCE_NONE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 		value &= ~(SSUSB_U2_PORT_FORCE_IDDIG | SSUSB_U2_PORT_RG_IDDIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	mtu3_writel(ssusb->ippc_base, SSUSB_U2_CTRL(0), value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) static int ssusb_role_sw_set(struct usb_role_switch *sw, enum usb_role role)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	struct ssusb_mtk *ssusb = usb_role_switch_get_drvdata(sw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	bool to_host = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	if (role == USB_ROLE_HOST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 		to_host = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	if (to_host ^ ssusb->is_host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 		ssusb_mode_switch(ssusb, to_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) static enum usb_role ssusb_role_sw_get(struct usb_role_switch *sw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	struct ssusb_mtk *ssusb = usb_role_switch_get_drvdata(sw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	enum usb_role role;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	role = ssusb->is_host ? USB_ROLE_HOST : USB_ROLE_DEVICE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	return role;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) static int ssusb_role_sw_register(struct otg_switch_mtk *otg_sx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	struct usb_role_switch_desc role_sx_desc = { 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	struct ssusb_mtk *ssusb =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 		container_of(otg_sx, struct ssusb_mtk, otg_switch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	if (!otg_sx->role_sw_used)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	role_sx_desc.set = ssusb_role_sw_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	role_sx_desc.get = ssusb_role_sw_get;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	role_sx_desc.fwnode = dev_fwnode(ssusb->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 	role_sx_desc.driver_data = ssusb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	otg_sx->role_sw = usb_role_switch_register(ssusb->dev, &role_sx_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	return PTR_ERR_OR_ZERO(otg_sx->role_sw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) int ssusb_otg_switch_init(struct ssusb_mtk *ssusb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 	struct otg_switch_mtk *otg_sx = &ssusb->otg_switch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 	INIT_WORK(&otg_sx->id_work, ssusb_id_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	INIT_WORK(&otg_sx->vbus_work, ssusb_vbus_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	if (otg_sx->manual_drd_enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 		ssusb_dr_debugfs_init(ssusb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	else if (otg_sx->role_sw_used)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 		ret = ssusb_role_sw_register(otg_sx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 		ret = ssusb_extcon_register(otg_sx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) void ssusb_otg_switch_exit(struct ssusb_mtk *ssusb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 	struct otg_switch_mtk *otg_sx = &ssusb->otg_switch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 	cancel_work_sync(&otg_sx->id_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 	cancel_work_sync(&otg_sx->vbus_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 	usb_role_switch_unregister(otg_sx->role_sw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) }