^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * mtu3.h - MediaTek USB3 DRD header
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2016 MediaTek Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author: Chunfeng Yun <chunfeng.yun@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #ifndef __MTU3_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define __MTU3_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/dmapool.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/extcon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/list.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/phy/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/usb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/usb/ch9.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/usb/gadget.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/usb/otg.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) struct mtu3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) struct mtu3_ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) struct mtu3_request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include "mtu3_hw_regs.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include "mtu3_qmu.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define MU3D_EP_TXCR0(epnum) (U3D_TX1CSR0 + (((epnum) - 1) * 0x10))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define MU3D_EP_TXCR1(epnum) (U3D_TX1CSR1 + (((epnum) - 1) * 0x10))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define MU3D_EP_TXCR2(epnum) (U3D_TX1CSR2 + (((epnum) - 1) * 0x10))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define MU3D_EP_RXCR0(epnum) (U3D_RX1CSR0 + (((epnum) - 1) * 0x10))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define MU3D_EP_RXCR1(epnum) (U3D_RX1CSR1 + (((epnum) - 1) * 0x10))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define MU3D_EP_RXCR2(epnum) (U3D_RX1CSR2 + (((epnum) - 1) * 0x10))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define USB_QMU_TQHIAR(epnum) (U3D_TXQHIAR1 + (((epnum) - 1) * 0x4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define USB_QMU_RQHIAR(epnum) (U3D_RXQHIAR1 + (((epnum) - 1) * 0x4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define USB_QMU_RQCSR(epnum) (U3D_RXQCSR1 + (((epnum) - 1) * 0x10))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define USB_QMU_RQSAR(epnum) (U3D_RXQSAR1 + (((epnum) - 1) * 0x10))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define USB_QMU_RQCPR(epnum) (U3D_RXQCPR1 + (((epnum) - 1) * 0x10))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define USB_QMU_TQCSR(epnum) (U3D_TXQCSR1 + (((epnum) - 1) * 0x10))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define USB_QMU_TQSAR(epnum) (U3D_TXQSAR1 + (((epnum) - 1) * 0x10))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define USB_QMU_TQCPR(epnum) (U3D_TXQCPR1 + (((epnum) - 1) * 0x10))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SSUSB_U3_CTRL(p) (U3D_SSUSB_U3_CTRL_0P + ((p) * 0x08))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SSUSB_U2_CTRL(p) (U3D_SSUSB_U2_CTRL_0P + ((p) * 0x08))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define MTU3_DRIVER_NAME "mtu3"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define DMA_ADDR_INVALID (~(dma_addr_t)0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define MTU3_EP_ENABLED BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define MTU3_EP_STALL BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define MTU3_EP_WEDGE BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define MTU3_EP_BUSY BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define MTU3_U3_IP_SLOT_DEFAULT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define MTU3_U2_IP_SLOT_DEFAULT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * IP TRUNK version
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * from 0x1003 version, USB3 Gen2 is supported, two changes affect driver:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * 1. MAXPKT and MULTI bits layout of TXCSR1 and RXCSR1 are adjusted,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * but not backward compatible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * 2. QMU extend buffer length supported
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define MTU3_TRUNK_VERS_1003 0x1003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * Normally the device works on HS or SS, to simplify fifo management,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * devide fifo into some 512B parts, use bitmap to manage it; And
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * 128 bits size of bitmap is large enough, that means it can manage
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * up to 64KB fifo size.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * NOTE: MTU3_EP_FIFO_UNIT should be power of two
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define MTU3_EP_FIFO_UNIT (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define MTU3_FIFO_BIT_SIZE 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define MTU3_U2_IP_EP0_FIFO_SIZE 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * Maximum size of ep0 response buffer for ch9 requests,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * the SET_SEL request uses 6 so far, and GET_STATUS is 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define EP0_RESPONSE_BUF 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /* device operated link and speed got from DEVICE_CONF register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) enum mtu3_speed {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) MTU3_SPEED_INACTIVE = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) MTU3_SPEED_FULL = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) MTU3_SPEED_HIGH = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) MTU3_SPEED_SUPER = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) MTU3_SPEED_SUPER_PLUS = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * @MU3D_EP0_STATE_SETUP: waits for SETUP or received a SETUP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * without data stage.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * @MU3D_EP0_STATE_TX: IN data stage
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * @MU3D_EP0_STATE_RX: OUT data stage
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * @MU3D_EP0_STATE_TX_END: the last IN data is transferred, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * waits for its completion interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * @MU3D_EP0_STATE_STALL: ep0 is in stall status, will be auto-cleared
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * after receives a SETUP.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) enum mtu3_g_ep0_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) MU3D_EP0_STATE_SETUP = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) MU3D_EP0_STATE_TX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) MU3D_EP0_STATE_RX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) MU3D_EP0_STATE_TX_END,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) MU3D_EP0_STATE_STALL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) * MTU3_DR_FORCE_NONE: automatically switch host and periperal mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * by IDPIN signal.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) * MTU3_DR_FORCE_HOST: force to enter host mode and override OTG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) * IDPIN signal.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) * MTU3_DR_FORCE_DEVICE: force to enter peripheral mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) enum mtu3_dr_force_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) MTU3_DR_FORCE_NONE = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) MTU3_DR_FORCE_HOST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) MTU3_DR_FORCE_DEVICE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * @base: the base address of fifo
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * @limit: the bitmap size in bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * @bitmap: fifo bitmap in unit of @MTU3_EP_FIFO_UNIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) struct mtu3_fifo_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) u32 base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) u32 limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) DECLARE_BITMAP(bitmap, MTU3_FIFO_BIT_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) * General Purpose Descriptor (GPD):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) * The format of TX GPD is a little different from RX one.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) * And the size of GPD is 16 bytes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) * @dw0_info:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) * bit0: Hardware Own (HWO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) * bit1: Buffer Descriptor Present (BDP), always 0, BD is not supported
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) * bit2: Bypass (BPS), 1: HW skips this GPD if HWO = 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) * bit6: [EL] Zero Length Packet (ZLP), moved from @dw3_info[29]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) * bit7: Interrupt On Completion (IOC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) * bit[31:16]: ([EL] bit[31:12]) allow data buffer length (RX ONLY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) * the buffer length of the data to receive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) * bit[23:16]: ([EL] bit[31:24]) extension address (TX ONLY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) * lower 4 bits are extension bits of @buffer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) * upper 4 bits are extension bits of @next_gpd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) * @next_gpd: Physical address of the next GPD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) * @buffer: Physical address of the data buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) * @dw3_info:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) * bit[15:0]: ([EL] bit[19:0]) data buffer length,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) * (TX): the buffer length of the data to transmit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * (RX): The total length of data received
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) * bit[23:16]: ([EL] bit[31:24]) extension address (RX ONLY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) * lower 4 bits are extension bits of @buffer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * upper 4 bits are extension bits of @next_gpd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) * bit29: ([EL] abandoned) Zero Length Packet (ZLP) (TX ONLY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) struct qmu_gpd {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) __le32 dw0_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) __le32 next_gpd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) __le32 buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) __le32 dw3_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) * dma: physical base address of GPD segment
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) * start: virtual base address of GPD segment
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) * end: the last GPD element
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) * enqueue: the first empty GPD to use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) * dequeue: the first completed GPD serviced by ISR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) * NOTE: the size of GPD ring should be >= 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) struct mtu3_gpd_ring {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) dma_addr_t dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) struct qmu_gpd *start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) struct qmu_gpd *end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) struct qmu_gpd *enqueue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) struct qmu_gpd *dequeue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) * @vbus: vbus 5V used by host mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) * @edev: external connector used to detect vbus and iddig changes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) * @vbus_nb: notifier for vbus detection
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) * @vbus_work : work of vbus detection notifier, used to avoid sleep in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) * notifier callback which is atomic context
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) * @vbus_event : event of vbus detecion notifier
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) * @id_nb : notifier for iddig(idpin) detection
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) * @id_work : work of iddig detection notifier
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) * @id_event : event of iddig detecion notifier
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) * @role_sw : use USB Role Switch to support dual-role switch, can't use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) * extcon at the same time, and extcon is deprecated.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) * @role_sw_used : true when the USB Role Switch is used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) * @is_u3_drd: whether port0 supports usb3.0 dual-role device or not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) * @manual_drd_enabled: it's true when supports dual-role device by debugfs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) * to switch host/device modes depending on user input.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) struct otg_switch_mtk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) struct regulator *vbus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) struct extcon_dev *edev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) struct notifier_block vbus_nb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) struct work_struct vbus_work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) unsigned long vbus_event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) struct notifier_block id_nb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) struct work_struct id_work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) unsigned long id_event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) struct usb_role_switch *role_sw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) bool role_sw_used;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) bool is_u3_drd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) bool manual_drd_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) * @mac_base: register base address of device MAC, exclude xHCI's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) * @ippc_base: register base address of IP Power and Clock interface (IPPC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) * @vusb33: usb3.3V shared by device/host IP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) * @sys_clk: system clock of mtu3, shared by device/host IP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) * @ref_clk: reference clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) * @mcu_clk: mcu_bus_ck clock for AHB bus etc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) * @dma_clk: dma_bus_ck clock for AXI bus etc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) * @dr_mode: works in which mode:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) * host only, device only or dual-role mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) * @u2_ports: number of usb2.0 host ports
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) * @u3_ports: number of usb3.0 host ports
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) * @u3p_dis_msk: mask of disabling usb3 ports, for example, bit0==1 to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) * disable u3port0, bit1==1 to disable u3port1,... etc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) * @dbgfs_root: only used when supports manual dual-role switch via debugfs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) * @uwk_en: it's true when supports remote wakeup in host mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) * @uwk: syscon including usb wakeup glue layer between SSUSB IP and SPM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) * @uwk_reg_base: the base address of the wakeup glue layer in @uwk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) * @uwk_vers: the version of the wakeup glue layer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) struct ssusb_mtk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) struct mtu3 *u3d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) void __iomem *mac_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) void __iomem *ippc_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) struct phy **phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) int num_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) /* common power & clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) struct regulator *vusb33;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) struct clk *sys_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) struct clk *ref_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) struct clk *mcu_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) struct clk *dma_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) /* otg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) struct otg_switch_mtk otg_switch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) enum usb_dr_mode dr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) bool is_host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) int u2_ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) int u3_ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) int u3p_dis_msk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) struct dentry *dbgfs_root;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) /* usb wakeup for host mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) bool uwk_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) struct regmap *uwk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) u32 uwk_reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) u32 uwk_vers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) * @fifo_size: it is (@slot + 1) * @fifo_seg_size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) * @fifo_seg_size: it is roundup_pow_of_two(@maxp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) struct mtu3_ep {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) struct usb_ep ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) char name[12];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) struct mtu3 *mtu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) u8 epnum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) u8 type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) u8 is_in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) u16 maxp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) int slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) u32 fifo_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) u32 fifo_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) u32 fifo_seg_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) struct mtu3_fifo_info *fifo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) struct list_head req_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) struct mtu3_gpd_ring gpd_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) const struct usb_ss_ep_comp_descriptor *comp_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) const struct usb_endpoint_descriptor *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) int flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) struct mtu3_request {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) struct usb_request request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) struct list_head list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) struct mtu3_ep *mep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) struct mtu3 *mtu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) struct qmu_gpd *gpd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) int epnum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) static inline struct ssusb_mtk *dev_to_ssusb(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) return dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) * struct mtu3 - device driver instance data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) * @slot: MTU3_U2_IP_SLOT_DEFAULT for U2 IP only,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) * MTU3_U3_IP_SLOT_DEFAULT for U3 IP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) * @may_wakeup: means device's remote wakeup is enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) * @is_self_powered: is reported in device status and the config descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) * @delayed_status: true when function drivers ask for delayed status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) * @gen2cp: compatible with USB3 Gen2 IP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) * @ep0_req: dummy request used while handling standard USB requests
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) * for GET_STATUS and SET_SEL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) * @setup_buf: ep0 response buffer for GET_STATUS and SET_SEL requests
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) struct mtu3 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) struct ssusb_mtk *ssusb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) void __iomem *mac_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) void __iomem *ippc_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) struct mtu3_fifo_info tx_fifo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) struct mtu3_fifo_info rx_fifo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) struct mtu3_ep *ep_array;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) struct mtu3_ep *in_eps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) struct mtu3_ep *out_eps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) struct mtu3_ep *ep0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) int num_eps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) int slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) int active_ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) struct dma_pool *qmu_gpd_pool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) enum mtu3_g_ep0_state ep0_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) struct usb_gadget g; /* the gadget */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) struct usb_gadget_driver *gadget_driver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) struct mtu3_request ep0_req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) u8 setup_buf[EP0_RESPONSE_BUF];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) enum usb_device_speed max_speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) enum usb_device_speed speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) unsigned is_active:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) unsigned may_wakeup:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) unsigned is_self_powered:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) unsigned test_mode:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) unsigned softconnect:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) unsigned u1_enable:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) unsigned u2_enable:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) unsigned is_u3_ip:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) unsigned delayed_status:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) unsigned gen2cp:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) u8 address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) u8 test_mode_nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) u32 hw_version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) static inline struct mtu3 *gadget_to_mtu3(struct usb_gadget *g)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) return container_of(g, struct mtu3, g);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) static inline struct mtu3_request *to_mtu3_request(struct usb_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) return req ? container_of(req, struct mtu3_request, request) : NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) static inline struct mtu3_ep *to_mtu3_ep(struct usb_ep *ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) return ep ? container_of(ep, struct mtu3_ep, ep) : NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) static inline struct mtu3_request *next_request(struct mtu3_ep *mep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) return list_first_entry_or_null(&mep->req_list, struct mtu3_request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) static inline void mtu3_writel(void __iomem *base, u32 offset, u32 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) writel(data, base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) static inline u32 mtu3_readl(void __iomem *base, u32 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) return readl(base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) static inline void mtu3_setbits(void __iomem *base, u32 offset, u32 bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) void __iomem *addr = base + offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) u32 tmp = readl(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) writel((tmp | (bits)), addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) static inline void mtu3_clrbits(void __iomem *base, u32 offset, u32 bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) void __iomem *addr = base + offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) u32 tmp = readl(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) writel((tmp & ~(bits)), addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) int ssusb_check_clocks(struct ssusb_mtk *ssusb, u32 ex_clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) struct usb_request *mtu3_alloc_request(struct usb_ep *ep, gfp_t gfp_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) void mtu3_free_request(struct usb_ep *ep, struct usb_request *req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) void mtu3_req_complete(struct mtu3_ep *mep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) struct usb_request *req, int status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) int mtu3_config_ep(struct mtu3 *mtu, struct mtu3_ep *mep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) int interval, int burst, int mult);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) void mtu3_deconfig_ep(struct mtu3 *mtu, struct mtu3_ep *mep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) void mtu3_ep_stall_set(struct mtu3_ep *mep, bool set);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) void mtu3_ep0_setup(struct mtu3 *mtu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) void mtu3_start(struct mtu3 *mtu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) void mtu3_stop(struct mtu3 *mtu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) void mtu3_dev_on_off(struct mtu3 *mtu, int is_on);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) void mtu3_set_speed(struct mtu3 *mtu, enum usb_device_speed speed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) int mtu3_gadget_setup(struct mtu3 *mtu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) void mtu3_gadget_cleanup(struct mtu3 *mtu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) void mtu3_gadget_reset(struct mtu3 *mtu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) void mtu3_gadget_suspend(struct mtu3 *mtu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) void mtu3_gadget_resume(struct mtu3 *mtu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) void mtu3_gadget_disconnect(struct mtu3 *mtu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) irqreturn_t mtu3_ep0_isr(struct mtu3 *mtu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) extern const struct usb_ep_ops mtu3_ep0_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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