^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Driver for the NXP ISP1761 device controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2014 Ideas on Board Oy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Contacts:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Laurent Pinchart <laurent.pinchart@ideasonboard.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/list.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/timer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/usb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "isp1760-core.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "isp1760-regs.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "isp1760-udc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define ISP1760_VBUS_POLL_INTERVAL msecs_to_jiffies(500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) struct isp1760_request {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) struct usb_request req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) struct list_head queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) struct isp1760_ep *ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) unsigned int packet_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) static inline struct isp1760_udc *gadget_to_udc(struct usb_gadget *gadget)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) return container_of(gadget, struct isp1760_udc, gadget);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) static inline struct isp1760_ep *ep_to_udc_ep(struct usb_ep *ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) return container_of(ep, struct isp1760_ep, ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) static inline struct isp1760_request *req_to_udc_req(struct usb_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) return container_of(req, struct isp1760_request, req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) static inline u32 isp1760_udc_read(struct isp1760_udc *udc, u16 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) return isp1760_read32(udc->regs, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) static inline void isp1760_udc_write(struct isp1760_udc *udc, u16 reg, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) isp1760_write32(udc->regs, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /* -----------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * Endpoint Management
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) static struct isp1760_ep *isp1760_udc_find_ep(struct isp1760_udc *udc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) u16 index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) if (index == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) return &udc->ep[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) for (i = 1; i < ARRAY_SIZE(udc->ep); ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) if (udc->ep[i].addr == index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) return udc->ep[i].desc ? &udc->ep[i] : NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) static void __isp1760_udc_select_ep(struct isp1760_ep *ep, int dir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) isp1760_udc_write(ep->udc, DC_EPINDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) DC_ENDPIDX(ep->addr & USB_ENDPOINT_NUMBER_MASK) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) (dir == USB_DIR_IN ? DC_EPDIR : 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * isp1760_udc_select_ep - Select an endpoint for register access
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * @ep: The endpoint
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * The ISP1761 endpoint registers are banked. This function selects the target
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * endpoint for banked register access. The selection remains valid until the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * next call to this function, the next direct access to the EPINDEX register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * or the next reset, whichever comes first.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * Called with the UDC spinlock held.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) static void isp1760_udc_select_ep(struct isp1760_ep *ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) __isp1760_udc_select_ep(ep, ep->addr & USB_ENDPOINT_DIR_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /* Called with the UDC spinlock held. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static void isp1760_udc_ctrl_send_status(struct isp1760_ep *ep, int dir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) struct isp1760_udc *udc = ep->udc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * Proceed to the status stage. The status stage data packet flows in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * the direction opposite to the data stage data packets, we thus need
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) * to select the OUT/IN endpoint for IN/OUT transfers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) isp1760_udc_write(udc, DC_EPINDEX, DC_ENDPIDX(0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) (dir == USB_DIR_IN ? 0 : DC_EPDIR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) isp1760_udc_write(udc, DC_CTRLFUNC, DC_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * The hardware will terminate the request automatically and go back to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * the setup stage without notifying us.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) udc->ep0_state = ISP1760_CTRL_SETUP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) /* Called without the UDC spinlock held. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static void isp1760_udc_request_complete(struct isp1760_ep *ep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) struct isp1760_request *req,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) int status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) struct isp1760_udc *udc = ep->udc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) dev_dbg(ep->udc->isp->dev, "completing request %p with status %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) req, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) req->ep = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) req->req.status = status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) req->req.complete(&ep->ep, &req->req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) spin_lock_irqsave(&udc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) * When completing control OUT requests, move to the status stage after
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) * calling the request complete callback. This gives the gadget an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) * opportunity to stall the control transfer if needed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) if (status == 0 && ep->addr == 0 && udc->ep0_dir == USB_DIR_OUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) isp1760_udc_ctrl_send_status(ep, USB_DIR_OUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) spin_unlock_irqrestore(&udc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static void isp1760_udc_ctrl_send_stall(struct isp1760_ep *ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) struct isp1760_udc *udc = ep->udc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) dev_dbg(ep->udc->isp->dev, "%s(ep%02x)\n", __func__, ep->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) spin_lock_irqsave(&udc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /* Stall both the IN and OUT endpoints. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) __isp1760_udc_select_ep(ep, USB_DIR_OUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) isp1760_udc_write(udc, DC_CTRLFUNC, DC_STALL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) __isp1760_udc_select_ep(ep, USB_DIR_IN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) isp1760_udc_write(udc, DC_CTRLFUNC, DC_STALL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /* A protocol stall completes the control transaction. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) udc->ep0_state = ISP1760_CTRL_SETUP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) spin_unlock_irqrestore(&udc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /* -----------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) * Data Endpoints
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /* Called with the UDC spinlock held. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static bool isp1760_udc_receive(struct isp1760_ep *ep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) struct isp1760_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) struct isp1760_udc *udc = ep->udc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) unsigned int len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) u32 *buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) isp1760_udc_select_ep(ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) len = isp1760_udc_read(udc, DC_BUFLEN) & DC_DATACOUNT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) dev_dbg(udc->isp->dev, "%s: received %u bytes (%u/%u done)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) __func__, len, req->req.actual, req->req.length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) len = min(len, req->req.length - req->req.actual);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) if (!len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) * There's no data to be read from the FIFO, acknowledge the RX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) * interrupt by clearing the buffer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) * TODO: What if another packet arrives in the meantime ? The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) * datasheet doesn't clearly document how this should be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) * handled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) isp1760_udc_write(udc, DC_CTRLFUNC, DC_CLBUF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) buf = req->req.buf + req->req.actual;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) * Make sure not to read more than one extra byte, otherwise data from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) * the next packet might be removed from the FIFO.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) for (i = len; i > 2; i -= 4, ++buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) *buf = le32_to_cpu(isp1760_udc_read(udc, DC_DATAPORT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) if (i > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) *(u16 *)buf = le16_to_cpu(readw(udc->regs + DC_DATAPORT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) req->req.actual += len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) * TODO: The short_not_ok flag isn't supported yet, but isn't used by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) * any gadget driver either.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) dev_dbg(udc->isp->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) "%s: req %p actual/length %u/%u maxpacket %u packet size %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) __func__, req, req->req.actual, req->req.length, ep->maxpacket,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) ep->rx_pending = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) * Complete the request if all data has been received or if a short
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) * packet has been received.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) if (req->req.actual == req->req.length || len < ep->maxpacket) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) list_del(&req->queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) static void isp1760_udc_transmit(struct isp1760_ep *ep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) struct isp1760_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) struct isp1760_udc *udc = ep->udc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) u32 *buf = req->req.buf + req->req.actual;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) req->packet_size = min(req->req.length - req->req.actual,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) ep->maxpacket);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) dev_dbg(udc->isp->dev, "%s: transferring %u bytes (%u/%u done)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) __func__, req->packet_size, req->req.actual,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) req->req.length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) __isp1760_udc_select_ep(ep, USB_DIR_IN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) if (req->packet_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) isp1760_udc_write(udc, DC_BUFLEN, req->packet_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) * Make sure not to write more than one extra byte, otherwise extra data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) * will stay in the FIFO and will be transmitted during the next control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) * request. The endpoint control CLBUF bit is supposed to allow flushing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) * the FIFO for this kind of conditions, but doesn't seem to work.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) for (i = req->packet_size; i > 2; i -= 4, ++buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) isp1760_udc_write(udc, DC_DATAPORT, cpu_to_le32(*buf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) if (i > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) writew(cpu_to_le16(*(u16 *)buf), udc->regs + DC_DATAPORT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) if (ep->addr == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) isp1760_udc_write(udc, DC_CTRLFUNC, DC_DSEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) if (!req->packet_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) isp1760_udc_write(udc, DC_CTRLFUNC, DC_VENDP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) static void isp1760_ep_rx_ready(struct isp1760_ep *ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) struct isp1760_udc *udc = ep->udc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) struct isp1760_request *req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) bool complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) spin_lock(&udc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) if (ep->addr == 0 && udc->ep0_state != ISP1760_CTRL_DATA_OUT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) spin_unlock(&udc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) dev_dbg(udc->isp->dev, "%s: invalid ep0 state %u\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) udc->ep0_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) if (ep->addr != 0 && !ep->desc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) spin_unlock(&udc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) dev_dbg(udc->isp->dev, "%s: ep%02x is disabled\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) ep->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) if (list_empty(&ep->queue)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) ep->rx_pending = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) spin_unlock(&udc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) dev_dbg(udc->isp->dev, "%s: ep%02x (%p) has no request queued\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) __func__, ep->addr, ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) req = list_first_entry(&ep->queue, struct isp1760_request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) complete = isp1760_udc_receive(ep, req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) spin_unlock(&udc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) if (complete)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) isp1760_udc_request_complete(ep, req, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) static void isp1760_ep_tx_complete(struct isp1760_ep *ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) struct isp1760_udc *udc = ep->udc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) struct isp1760_request *complete = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) struct isp1760_request *req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) bool need_zlp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) spin_lock(&udc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) if (ep->addr == 0 && udc->ep0_state != ISP1760_CTRL_DATA_IN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) spin_unlock(&udc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) dev_dbg(udc->isp->dev, "TX IRQ: invalid endpoint state %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) udc->ep0_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) if (list_empty(&ep->queue)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) * This can happen for the control endpoint when the reply to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) * the GET_STATUS IN control request is sent directly by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) * setup IRQ handler. Just proceed to the status stage.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) if (ep->addr == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) isp1760_udc_ctrl_send_status(ep, USB_DIR_IN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) spin_unlock(&udc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) spin_unlock(&udc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) dev_dbg(udc->isp->dev, "%s: ep%02x has no request queued\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) __func__, ep->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) req = list_first_entry(&ep->queue, struct isp1760_request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) req->req.actual += req->packet_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) need_zlp = req->req.actual == req->req.length &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) !(req->req.length % ep->maxpacket) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) req->packet_size && req->req.zero;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) dev_dbg(udc->isp->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) "TX IRQ: req %p actual/length %u/%u maxpacket %u packet size %u zero %u need zlp %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) req, req->req.actual, req->req.length, ep->maxpacket,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) req->packet_size, req->req.zero, need_zlp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) * Complete the request if all data has been sent and we don't need to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) * transmit a zero length packet.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) if (req->req.actual == req->req.length && !need_zlp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) complete = req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) list_del(&req->queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) if (ep->addr == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) isp1760_udc_ctrl_send_status(ep, USB_DIR_IN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) if (!list_empty(&ep->queue))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) req = list_first_entry(&ep->queue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) struct isp1760_request, queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) req = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) * Transmit the next packet or start the next request, if any.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) * TODO: If the endpoint is stalled the next request shouldn't be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) * started, but what about the next packet ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) if (req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) isp1760_udc_transmit(ep, req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) spin_unlock(&udc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) if (complete)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) isp1760_udc_request_complete(ep, complete, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) static int __isp1760_udc_set_halt(struct isp1760_ep *ep, bool halt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) struct isp1760_udc *udc = ep->udc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) dev_dbg(udc->isp->dev, "%s: %s halt on ep%02x\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) halt ? "set" : "clear", ep->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) if (ep->desc && usb_endpoint_xfer_isoc(ep->desc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) dev_dbg(udc->isp->dev, "%s: ep%02x is isochronous\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) ep->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) isp1760_udc_select_ep(ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) isp1760_udc_write(udc, DC_CTRLFUNC, halt ? DC_STALL : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) if (ep->addr == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) /* When halting the control endpoint, stall both IN and OUT. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) __isp1760_udc_select_ep(ep, USB_DIR_IN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) isp1760_udc_write(udc, DC_CTRLFUNC, halt ? DC_STALL : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) } else if (!halt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) /* Reset the data PID by cycling the endpoint enable bit. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) u16 eptype = isp1760_udc_read(udc, DC_EPTYPE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) isp1760_udc_write(udc, DC_EPTYPE, eptype & ~DC_EPENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) isp1760_udc_write(udc, DC_EPTYPE, eptype);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) * Disabling the endpoint emptied the transmit FIFO, fill it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) * again if a request is pending.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) * TODO: Does the gadget framework require synchronizatino with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) * the TX IRQ handler ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) if ((ep->addr & USB_DIR_IN) && !list_empty(&ep->queue)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) struct isp1760_request *req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) req = list_first_entry(&ep->queue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) struct isp1760_request, queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) isp1760_udc_transmit(ep, req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) ep->halted = halt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) /* -----------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) * Control Endpoint
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) static int isp1760_udc_get_status(struct isp1760_udc *udc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) const struct usb_ctrlrequest *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) struct isp1760_ep *ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) u16 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) if (req->wLength != cpu_to_le16(2) || req->wValue != cpu_to_le16(0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) switch (req->bRequestType) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) case USB_DIR_IN | USB_RECIP_DEVICE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) status = udc->devstatus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) case USB_DIR_IN | USB_RECIP_INTERFACE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) case USB_DIR_IN | USB_RECIP_ENDPOINT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) ep = isp1760_udc_find_ep(udc, le16_to_cpu(req->wIndex));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) if (!ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) if (ep->halted)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) status |= 1 << USB_ENDPOINT_HALT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) isp1760_udc_write(udc, DC_EPINDEX, DC_ENDPIDX(0) | DC_EPDIR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) isp1760_udc_write(udc, DC_BUFLEN, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) writew(cpu_to_le16(status), udc->regs + DC_DATAPORT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) isp1760_udc_write(udc, DC_CTRLFUNC, DC_DSEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) dev_dbg(udc->isp->dev, "%s: status 0x%04x\n", __func__, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) static int isp1760_udc_set_address(struct isp1760_udc *udc, u16 addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) if (addr > 127) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) dev_dbg(udc->isp->dev, "invalid device address %u\n", addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) if (udc->gadget.state != USB_STATE_DEFAULT &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) udc->gadget.state != USB_STATE_ADDRESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) dev_dbg(udc->isp->dev, "can't set address in state %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) udc->gadget.state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) usb_gadget_set_state(&udc->gadget, addr ? USB_STATE_ADDRESS :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) USB_STATE_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) isp1760_udc_write(udc, DC_ADDRESS, DC_DEVEN | addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) spin_lock(&udc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) isp1760_udc_ctrl_send_status(&udc->ep[0], USB_DIR_OUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) spin_unlock(&udc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) static bool isp1760_ep0_setup_standard(struct isp1760_udc *udc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) struct usb_ctrlrequest *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) bool stall;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) switch (req->bRequest) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) case USB_REQ_GET_STATUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) return isp1760_udc_get_status(udc, req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) case USB_REQ_CLEAR_FEATURE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) switch (req->bRequestType) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) case USB_DIR_OUT | USB_RECIP_DEVICE: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) /* TODO: Handle remote wakeup feature. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) case USB_DIR_OUT | USB_RECIP_ENDPOINT: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) u16 index = le16_to_cpu(req->wIndex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) struct isp1760_ep *ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) if (req->wLength != cpu_to_le16(0) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) req->wValue != cpu_to_le16(USB_ENDPOINT_HALT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) ep = isp1760_udc_find_ep(udc, index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) if (!ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) spin_lock(&udc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) * If the endpoint is wedged only the gadget can clear
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) * the halt feature. Pretend success in that case, but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) * keep the endpoint halted.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) if (!ep->wedged)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) stall = __isp1760_udc_set_halt(ep, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) stall = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) if (!stall)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) isp1760_udc_ctrl_send_status(&udc->ep[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) USB_DIR_OUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) spin_unlock(&udc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) return stall;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) case USB_REQ_SET_FEATURE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) switch (req->bRequestType) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) case USB_DIR_OUT | USB_RECIP_DEVICE: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) /* TODO: Handle remote wakeup and test mode features */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) case USB_DIR_OUT | USB_RECIP_ENDPOINT: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) u16 index = le16_to_cpu(req->wIndex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) struct isp1760_ep *ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) if (req->wLength != cpu_to_le16(0) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) req->wValue != cpu_to_le16(USB_ENDPOINT_HALT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) ep = isp1760_udc_find_ep(udc, index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) if (!ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) spin_lock(&udc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) stall = __isp1760_udc_set_halt(ep, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) if (!stall)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) isp1760_udc_ctrl_send_status(&udc->ep[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) USB_DIR_OUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) spin_unlock(&udc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) return stall;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) case USB_REQ_SET_ADDRESS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) if (req->bRequestType != (USB_DIR_OUT | USB_RECIP_DEVICE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) return isp1760_udc_set_address(udc, le16_to_cpu(req->wValue));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) case USB_REQ_SET_CONFIGURATION:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) if (req->bRequestType != (USB_DIR_OUT | USB_RECIP_DEVICE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) if (udc->gadget.state != USB_STATE_ADDRESS &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) udc->gadget.state != USB_STATE_CONFIGURED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) stall = udc->driver->setup(&udc->gadget, req) < 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) if (stall)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) usb_gadget_set_state(&udc->gadget, req->wValue ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) USB_STATE_CONFIGURED : USB_STATE_ADDRESS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) * SET_CONFIGURATION (and SET_INTERFACE) must reset the halt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) * feature on all endpoints. There is however no need to do so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) * explicitly here as the gadget driver will disable and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) * reenable endpoints, clearing the halt feature.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) return udc->driver->setup(&udc->gadget, req) < 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) static void isp1760_ep0_setup(struct isp1760_udc *udc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) struct usb_ctrlrequest r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) u32 data[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) } req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) unsigned int count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) bool stall = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) spin_lock(&udc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) isp1760_udc_write(udc, DC_EPINDEX, DC_EP0SETUP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) count = isp1760_udc_read(udc, DC_BUFLEN) & DC_DATACOUNT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) if (count != sizeof(req)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) spin_unlock(&udc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) dev_err(udc->isp->dev, "invalid length %u for setup packet\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) isp1760_udc_ctrl_send_stall(&udc->ep[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) req.data[0] = isp1760_udc_read(udc, DC_DATAPORT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) req.data[1] = isp1760_udc_read(udc, DC_DATAPORT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) if (udc->ep0_state != ISP1760_CTRL_SETUP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) spin_unlock(&udc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) dev_dbg(udc->isp->dev, "unexpected SETUP packet\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) /* Move to the data stage. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) if (!req.r.wLength)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) udc->ep0_state = ISP1760_CTRL_STATUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) else if (req.r.bRequestType & USB_DIR_IN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) udc->ep0_state = ISP1760_CTRL_DATA_IN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) udc->ep0_state = ISP1760_CTRL_DATA_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) udc->ep0_dir = req.r.bRequestType & USB_DIR_IN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) udc->ep0_length = le16_to_cpu(req.r.wLength);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) spin_unlock(&udc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) dev_dbg(udc->isp->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) "%s: bRequestType 0x%02x bRequest 0x%02x wValue 0x%04x wIndex 0x%04x wLength 0x%04x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) __func__, req.r.bRequestType, req.r.bRequest,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) le16_to_cpu(req.r.wValue), le16_to_cpu(req.r.wIndex),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) le16_to_cpu(req.r.wLength));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) if ((req.r.bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) stall = isp1760_ep0_setup_standard(udc, &req.r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) stall = udc->driver->setup(&udc->gadget, &req.r) < 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) if (stall)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) isp1760_udc_ctrl_send_stall(&udc->ep[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) /* -----------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) * Gadget Endpoint Operations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) static int isp1760_ep_enable(struct usb_ep *ep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) const struct usb_endpoint_descriptor *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) struct isp1760_ep *uep = ep_to_udc_ep(ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) struct isp1760_udc *udc = uep->udc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) unsigned int type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) dev_dbg(uep->udc->isp->dev, "%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) * Validate the descriptor. The control endpoint can't be enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) * manually.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) if (desc->bDescriptorType != USB_DT_ENDPOINT ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) desc->bEndpointAddress == 0 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) desc->bEndpointAddress != uep->addr ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) le16_to_cpu(desc->wMaxPacketSize) > ep->maxpacket) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) dev_dbg(udc->isp->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) "%s: invalid descriptor type %u addr %02x ep addr %02x max packet size %u/%u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) __func__, desc->bDescriptorType,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) desc->bEndpointAddress, uep->addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) le16_to_cpu(desc->wMaxPacketSize), ep->maxpacket);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) switch (usb_endpoint_type(desc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) case USB_ENDPOINT_XFER_ISOC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) type = DC_ENDPTYP_ISOC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) case USB_ENDPOINT_XFER_BULK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) type = DC_ENDPTYP_BULK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) case USB_ENDPOINT_XFER_INT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) type = DC_ENDPTYP_INTERRUPT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) case USB_ENDPOINT_XFER_CONTROL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) dev_dbg(udc->isp->dev, "%s: control endpoints unsupported\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) spin_lock_irqsave(&udc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) uep->desc = desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) uep->maxpacket = le16_to_cpu(desc->wMaxPacketSize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) uep->rx_pending = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) uep->halted = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) uep->wedged = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) isp1760_udc_select_ep(uep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) isp1760_udc_write(udc, DC_EPMAXPKTSZ, uep->maxpacket);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) isp1760_udc_write(udc, DC_BUFLEN, uep->maxpacket);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) isp1760_udc_write(udc, DC_EPTYPE, DC_EPENABLE | type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) spin_unlock_irqrestore(&udc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) static int isp1760_ep_disable(struct usb_ep *ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) struct isp1760_ep *uep = ep_to_udc_ep(ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) struct isp1760_udc *udc = uep->udc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) struct isp1760_request *req, *nreq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) LIST_HEAD(req_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) dev_dbg(udc->isp->dev, "%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) spin_lock_irqsave(&udc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) if (!uep->desc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) dev_dbg(udc->isp->dev, "%s: endpoint not enabled\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) spin_unlock_irqrestore(&udc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) uep->desc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) uep->maxpacket = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) isp1760_udc_select_ep(uep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) isp1760_udc_write(udc, DC_EPTYPE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) /* TODO Synchronize with the IRQ handler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) list_splice_init(&uep->queue, &req_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) spin_unlock_irqrestore(&udc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) list_for_each_entry_safe(req, nreq, &req_list, queue) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) list_del(&req->queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) isp1760_udc_request_complete(uep, req, -ESHUTDOWN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) static struct usb_request *isp1760_ep_alloc_request(struct usb_ep *ep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) gfp_t gfp_flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) struct isp1760_request *req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) req = kzalloc(sizeof(*req), gfp_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) if (!req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) return &req->req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) static void isp1760_ep_free_request(struct usb_ep *ep, struct usb_request *_req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) struct isp1760_request *req = req_to_udc_req(_req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) kfree(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) static int isp1760_ep_queue(struct usb_ep *ep, struct usb_request *_req,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) gfp_t gfp_flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) struct isp1760_request *req = req_to_udc_req(_req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) struct isp1760_ep *uep = ep_to_udc_ep(ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) struct isp1760_udc *udc = uep->udc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) bool complete = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) _req->status = -EINPROGRESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) _req->actual = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) spin_lock_irqsave(&udc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) dev_dbg(udc->isp->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) "%s: req %p (%u bytes%s) ep %p(0x%02x)\n", __func__, _req,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) _req->length, _req->zero ? " (zlp)" : "", uep, uep->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) req->ep = uep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) if (uep->addr == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) if (_req->length != udc->ep0_length &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) udc->ep0_state != ISP1760_CTRL_DATA_IN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) dev_dbg(udc->isp->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) "%s: invalid length %u for req %p\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) __func__, _req->length, req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) switch (udc->ep0_state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) case ISP1760_CTRL_DATA_IN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) dev_dbg(udc->isp->dev, "%s: transmitting req %p\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) __func__, req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) list_add_tail(&req->queue, &uep->queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) isp1760_udc_transmit(uep, req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) case ISP1760_CTRL_DATA_OUT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) list_add_tail(&req->queue, &uep->queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) __isp1760_udc_select_ep(uep, USB_DIR_OUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) isp1760_udc_write(udc, DC_CTRLFUNC, DC_DSEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) case ISP1760_CTRL_STATUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) complete = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) dev_dbg(udc->isp->dev, "%s: invalid ep0 state\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) } else if (uep->desc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) bool empty = list_empty(&uep->queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) list_add_tail(&req->queue, &uep->queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) if ((uep->addr & USB_DIR_IN) && !uep->halted && empty)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) isp1760_udc_transmit(uep, req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) else if (!(uep->addr & USB_DIR_IN) && uep->rx_pending)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) complete = isp1760_udc_receive(uep, req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) dev_dbg(udc->isp->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) "%s: can't queue request to disabled ep%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) __func__, uep->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) ret = -ESHUTDOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) req->ep = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) spin_unlock_irqrestore(&udc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) if (complete)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) isp1760_udc_request_complete(uep, req, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) static int isp1760_ep_dequeue(struct usb_ep *ep, struct usb_request *_req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) struct isp1760_request *req = req_to_udc_req(_req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) struct isp1760_ep *uep = ep_to_udc_ep(ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) struct isp1760_udc *udc = uep->udc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) dev_dbg(uep->udc->isp->dev, "%s(ep%02x)\n", __func__, uep->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) spin_lock_irqsave(&udc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) if (req->ep != uep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) req = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) list_del(&req->queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) spin_unlock_irqrestore(&udc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) if (!req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) isp1760_udc_request_complete(uep, req, -ECONNRESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) static int __isp1760_ep_set_halt(struct isp1760_ep *uep, bool stall, bool wedge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) struct isp1760_udc *udc = uep->udc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) if (!uep->addr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) * Halting the control endpoint is only valid as a delayed error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) * response to a SETUP packet. Make sure EP0 is in the right
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) * stage and that the gadget isn't trying to clear the halt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) * condition.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) if (WARN_ON(udc->ep0_state == ISP1760_CTRL_SETUP || !stall ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) wedge)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) if (uep->addr && !uep->desc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) dev_dbg(udc->isp->dev, "%s: ep%02x is disabled\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) uep->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) if (uep->addr & USB_DIR_IN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) /* Refuse to halt IN endpoints with active transfers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) if (!list_empty(&uep->queue)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) dev_dbg(udc->isp->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) "%s: ep%02x has request pending\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) uep->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) ret = __isp1760_udc_set_halt(uep, stall);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) if (!uep->addr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) * Stalling EP0 completes the control transaction, move back to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) * the SETUP state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) udc->ep0_state = ISP1760_CTRL_SETUP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) if (wedge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) uep->wedged = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) else if (!stall)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) uep->wedged = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) static int isp1760_ep_set_halt(struct usb_ep *ep, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) struct isp1760_ep *uep = ep_to_udc_ep(ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) dev_dbg(uep->udc->isp->dev, "%s: %s halt on ep%02x\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) value ? "set" : "clear", uep->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) spin_lock_irqsave(&uep->udc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) ret = __isp1760_ep_set_halt(uep, value, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) spin_unlock_irqrestore(&uep->udc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) static int isp1760_ep_set_wedge(struct usb_ep *ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) struct isp1760_ep *uep = ep_to_udc_ep(ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) dev_dbg(uep->udc->isp->dev, "%s: set wedge on ep%02x)\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) uep->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) spin_lock_irqsave(&uep->udc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) ret = __isp1760_ep_set_halt(uep, true, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) spin_unlock_irqrestore(&uep->udc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) static void isp1760_ep_fifo_flush(struct usb_ep *ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) struct isp1760_ep *uep = ep_to_udc_ep(ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) struct isp1760_udc *udc = uep->udc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) spin_lock_irqsave(&udc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) isp1760_udc_select_ep(uep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) * Set the CLBUF bit twice to flush both buffers in case double
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) * buffering is enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) isp1760_udc_write(udc, DC_CTRLFUNC, DC_CLBUF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) isp1760_udc_write(udc, DC_CTRLFUNC, DC_CLBUF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) spin_unlock_irqrestore(&udc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) static const struct usb_ep_ops isp1760_ep_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) .enable = isp1760_ep_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) .disable = isp1760_ep_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) .alloc_request = isp1760_ep_alloc_request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) .free_request = isp1760_ep_free_request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) .queue = isp1760_ep_queue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) .dequeue = isp1760_ep_dequeue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) .set_halt = isp1760_ep_set_halt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) .set_wedge = isp1760_ep_set_wedge,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) .fifo_flush = isp1760_ep_fifo_flush,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) /* -----------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) * Device States
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) /* Called with the UDC spinlock held. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) static void isp1760_udc_connect(struct isp1760_udc *udc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) usb_gadget_set_state(&udc->gadget, USB_STATE_POWERED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) mod_timer(&udc->vbus_timer, jiffies + ISP1760_VBUS_POLL_INTERVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) /* Called with the UDC spinlock held. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) static void isp1760_udc_disconnect(struct isp1760_udc *udc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) if (udc->gadget.state < USB_STATE_POWERED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) dev_dbg(udc->isp->dev, "Device disconnected in state %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) udc->gadget.state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) udc->gadget.speed = USB_SPEED_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) usb_gadget_set_state(&udc->gadget, USB_STATE_ATTACHED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) if (udc->driver->disconnect)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) udc->driver->disconnect(&udc->gadget);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) del_timer(&udc->vbus_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) /* TODO Reset all endpoints ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) static void isp1760_udc_init_hw(struct isp1760_udc *udc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) * The device controller currently shares its interrupt with the host
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) * controller, the DC_IRQ polarity and signaling mode are ignored. Set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) * the to active-low level-triggered.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) * Configure the control, in and out pipes to generate interrupts on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) * ACK tokens only (and NYET for the out pipe). The default
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) * configuration also generates an interrupt on the first NACK token.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) isp1760_udc_write(udc, DC_INTCONF, DC_CDBGMOD_ACK | DC_DDBGMODIN_ACK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) DC_DDBGMODOUT_ACK_NYET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) isp1760_udc_write(udc, DC_INTENABLE, DC_IEPRXTX(7) | DC_IEPRXTX(6) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) DC_IEPRXTX(5) | DC_IEPRXTX(4) | DC_IEPRXTX(3) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) DC_IEPRXTX(2) | DC_IEPRXTX(1) | DC_IEPRXTX(0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) DC_IEP0SETUP | DC_IEVBUS | DC_IERESM | DC_IESUSP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) DC_IEHS_STA | DC_IEBRST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) if (udc->connected)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) isp1760_set_pullup(udc->isp, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) isp1760_udc_write(udc, DC_ADDRESS, DC_DEVEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) static void isp1760_udc_reset(struct isp1760_udc *udc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) spin_lock_irqsave(&udc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) * The bus reset has reset most registers to their default value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) * reinitialize the UDC hardware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) isp1760_udc_init_hw(udc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) udc->ep0_state = ISP1760_CTRL_SETUP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) udc->gadget.speed = USB_SPEED_FULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) usb_gadget_udc_reset(&udc->gadget, udc->driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) spin_unlock_irqrestore(&udc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) static void isp1760_udc_suspend(struct isp1760_udc *udc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) if (udc->gadget.state < USB_STATE_DEFAULT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) if (udc->driver->suspend)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) udc->driver->suspend(&udc->gadget);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) static void isp1760_udc_resume(struct isp1760_udc *udc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) if (udc->gadget.state < USB_STATE_DEFAULT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) if (udc->driver->resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) udc->driver->resume(&udc->gadget);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) /* -----------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) * Gadget Operations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) static int isp1760_udc_get_frame(struct usb_gadget *gadget)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) struct isp1760_udc *udc = gadget_to_udc(gadget);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) return isp1760_udc_read(udc, DC_FRAMENUM) & ((1 << 11) - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) static int isp1760_udc_wakeup(struct usb_gadget *gadget)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) struct isp1760_udc *udc = gadget_to_udc(gadget);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) dev_dbg(udc->isp->dev, "%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) static int isp1760_udc_set_selfpowered(struct usb_gadget *gadget,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) int is_selfpowered)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) struct isp1760_udc *udc = gadget_to_udc(gadget);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) if (is_selfpowered)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) udc->devstatus |= 1 << USB_DEVICE_SELF_POWERED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) udc->devstatus &= ~(1 << USB_DEVICE_SELF_POWERED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) static int isp1760_udc_pullup(struct usb_gadget *gadget, int is_on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) struct isp1760_udc *udc = gadget_to_udc(gadget);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) isp1760_set_pullup(udc->isp, is_on);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) udc->connected = is_on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) static int isp1760_udc_start(struct usb_gadget *gadget,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) struct usb_gadget_driver *driver)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) struct isp1760_udc *udc = gadget_to_udc(gadget);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) /* The hardware doesn't support low speed. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) if (driver->max_speed < USB_SPEED_FULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) dev_err(udc->isp->dev, "Invalid gadget driver\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) spin_lock_irqsave(&udc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) if (udc->driver) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) dev_err(udc->isp->dev, "UDC already has a gadget driver\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) spin_unlock_irqrestore(&udc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) udc->driver = driver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) spin_unlock_irqrestore(&udc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) dev_dbg(udc->isp->dev, "starting UDC with driver %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) driver->function);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) udc->devstatus = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) udc->connected = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) usb_gadget_set_state(&udc->gadget, USB_STATE_ATTACHED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) /* DMA isn't supported yet, don't enable the DMA clock. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) isp1760_udc_write(udc, DC_MODE, DC_GLINTENA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) isp1760_udc_init_hw(udc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) dev_dbg(udc->isp->dev, "UDC started with driver %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) driver->function);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) static int isp1760_udc_stop(struct usb_gadget *gadget)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) struct isp1760_udc *udc = gadget_to_udc(gadget);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) dev_dbg(udc->isp->dev, "%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) del_timer_sync(&udc->vbus_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) isp1760_udc_write(udc, DC_MODE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) spin_lock_irqsave(&udc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) udc->driver = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) spin_unlock_irqrestore(&udc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) static const struct usb_gadget_ops isp1760_udc_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) .get_frame = isp1760_udc_get_frame,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) .wakeup = isp1760_udc_wakeup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) .set_selfpowered = isp1760_udc_set_selfpowered,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) .pullup = isp1760_udc_pullup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) .udc_start = isp1760_udc_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) .udc_stop = isp1760_udc_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) /* -----------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) * Interrupt Handling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) static irqreturn_t isp1760_udc_irq(int irq, void *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) struct isp1760_udc *udc = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) status = isp1760_udc_read(udc, DC_INTERRUPT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) & isp1760_udc_read(udc, DC_INTENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) isp1760_udc_write(udc, DC_INTERRUPT, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) if (status & DC_IEVBUS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) dev_dbg(udc->isp->dev, "%s(VBUS)\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) /* The VBUS interrupt is only triggered when VBUS appears. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) spin_lock(&udc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) isp1760_udc_connect(udc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) spin_unlock(&udc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) if (status & DC_IEBRST) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) dev_dbg(udc->isp->dev, "%s(BRST)\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) isp1760_udc_reset(udc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) for (i = 0; i <= 7; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) struct isp1760_ep *ep = &udc->ep[i*2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) if (status & DC_IEPTX(i)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) dev_dbg(udc->isp->dev, "%s(EPTX%u)\n", __func__, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) isp1760_ep_tx_complete(ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) if (status & DC_IEPRX(i)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) dev_dbg(udc->isp->dev, "%s(EPRX%u)\n", __func__, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) isp1760_ep_rx_ready(i ? ep - 1 : ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) if (status & DC_IEP0SETUP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) dev_dbg(udc->isp->dev, "%s(EP0SETUP)\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) isp1760_ep0_setup(udc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) if (status & DC_IERESM) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) dev_dbg(udc->isp->dev, "%s(RESM)\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) isp1760_udc_resume(udc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) if (status & DC_IESUSP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) dev_dbg(udc->isp->dev, "%s(SUSP)\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) spin_lock(&udc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) if (!(isp1760_udc_read(udc, DC_MODE) & DC_VBUSSTAT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) isp1760_udc_disconnect(udc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) isp1760_udc_suspend(udc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) spin_unlock(&udc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) if (status & DC_IEHS_STA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) dev_dbg(udc->isp->dev, "%s(HS_STA)\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) udc->gadget.speed = USB_SPEED_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) return status ? IRQ_HANDLED : IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) static void isp1760_udc_vbus_poll(struct timer_list *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) struct isp1760_udc *udc = from_timer(udc, t, vbus_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) spin_lock_irqsave(&udc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) if (!(isp1760_udc_read(udc, DC_MODE) & DC_VBUSSTAT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) isp1760_udc_disconnect(udc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) else if (udc->gadget.state >= USB_STATE_POWERED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) mod_timer(&udc->vbus_timer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) jiffies + ISP1760_VBUS_POLL_INTERVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) spin_unlock_irqrestore(&udc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) /* -----------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) * Registration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) static void isp1760_udc_init_eps(struct isp1760_udc *udc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) INIT_LIST_HEAD(&udc->gadget.ep_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) for (i = 0; i < ARRAY_SIZE(udc->ep); ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) struct isp1760_ep *ep = &udc->ep[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) unsigned int ep_num = (i + 1) / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) bool is_in = !(i & 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) ep->udc = udc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) INIT_LIST_HEAD(&ep->queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) ep->addr = (ep_num && is_in ? USB_DIR_IN : USB_DIR_OUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) | ep_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) ep->desc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) sprintf(ep->name, "ep%u%s", ep_num,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) ep_num ? (is_in ? "in" : "out") : "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) ep->ep.ops = &isp1760_ep_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) ep->ep.name = ep->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) * Hardcode the maximum packet sizes for now, to 64 bytes for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) * the control endpoint and 512 bytes for all other endpoints.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) * This fits in the 8kB FIFO without double-buffering.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) if (ep_num == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) usb_ep_set_maxpacket_limit(&ep->ep, 64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) ep->ep.caps.type_control = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) ep->ep.caps.dir_in = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) ep->ep.caps.dir_out = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) ep->maxpacket = 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) udc->gadget.ep0 = &ep->ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) usb_ep_set_maxpacket_limit(&ep->ep, 512);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) ep->ep.caps.type_iso = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) ep->ep.caps.type_bulk = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) ep->ep.caps.type_int = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) ep->maxpacket = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) if (is_in)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) ep->ep.caps.dir_in = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) ep->ep.caps.dir_out = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) static int isp1760_udc_init(struct isp1760_udc *udc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) u16 scratch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) u32 chipid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) * Check that the controller is present by writing to the scratch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) * register, modifying the bus pattern by reading from the chip ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) * register, and reading the scratch register value back. The chip ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) * and scratch register contents must match the expected values.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) isp1760_udc_write(udc, DC_SCRATCH, 0xbabe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) chipid = isp1760_udc_read(udc, DC_CHIPID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) scratch = isp1760_udc_read(udc, DC_SCRATCH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) if (scratch != 0xbabe) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) dev_err(udc->isp->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) "udc: scratch test failed (0x%04x/0x%08x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) scratch, chipid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) if (chipid != 0x00011582 && chipid != 0x00158210) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) dev_err(udc->isp->dev, "udc: invalid chip ID 0x%08x\n", chipid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) /* Reset the device controller. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) isp1760_udc_write(udc, DC_MODE, DC_SFRESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) usleep_range(10000, 11000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) isp1760_udc_write(udc, DC_MODE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) usleep_range(10000, 11000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) int isp1760_udc_register(struct isp1760_device *isp, int irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) unsigned long irqflags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) struct isp1760_udc *udc = &isp->udc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) udc->irq = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) udc->isp = isp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) udc->regs = isp->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) spin_lock_init(&udc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) timer_setup(&udc->vbus_timer, isp1760_udc_vbus_poll, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) ret = isp1760_udc_init(udc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) udc->irqname = kasprintf(GFP_KERNEL, "%s (udc)", dev_name(isp->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) if (!udc->irqname)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) ret = request_irq(irq, isp1760_udc_irq, IRQF_SHARED | irqflags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) udc->irqname, udc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) udc->irq = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) * Initialize the gadget static fields and register its device. Gadget
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) * fields that vary during the life time of the gadget are initialized
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) * by the UDC core.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) udc->gadget.ops = &isp1760_udc_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) udc->gadget.speed = USB_SPEED_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) udc->gadget.max_speed = USB_SPEED_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) udc->gadget.name = "isp1761_udc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) isp1760_udc_init_eps(udc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) ret = usb_add_gadget_udc(isp->dev, &udc->gadget);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) if (udc->irq >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) free_irq(udc->irq, udc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) kfree(udc->irqname);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) void isp1760_udc_unregister(struct isp1760_device *isp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) struct isp1760_udc *udc = &isp->udc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) if (!udc->isp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) usb_del_gadget_udc(&udc->gadget);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) free_irq(udc->irq, udc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) kfree(udc->irqname);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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