^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * xHCI host controller driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2008 Intel Corp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Author: Sarah Sharp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Some code borrowed from the Linux EHCI driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #ifndef __LINUX_XHCI_HCD_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define __LINUX_XHCI_HCD_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/usb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/timer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/usb/hcd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/io-64-nonatomic-lo-hi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/android_kabi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /* Code sharing between pci-quirks and xhci hcd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include "xhci-ext-caps.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include "pci-quirks.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* max buffer size for trace and debug messages */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define XHCI_MSG_MAX 500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /* xHCI PCI Configuration Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define XHCI_SBRN_OFFSET (0x60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /* Max number of USB devices for any host controller - limit in section 6.1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define MAX_HC_SLOTS 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /* Section 5.3.3 - MaxPorts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define MAX_HC_PORTS 127
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * xHCI register interface.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * This corresponds to the eXtensible Host Controller Interface (xHCI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * Revision 0.95 specification
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * struct xhci_cap_regs - xHCI Host Controller Capability Registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * @hc_capbase: length of the capabilities register and HC version number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * @hcs_params1: HCSPARAMS1 - Structural Parameters 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * @hcs_params2: HCSPARAMS2 - Structural Parameters 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * @hcs_params3: HCSPARAMS3 - Structural Parameters 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * @hcc_params: HCCPARAMS - Capability Parameters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * @db_off: DBOFF - Doorbell array offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * @run_regs_off: RTSOFF - Runtime register space offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * @hcc_params2: HCCPARAMS2 Capability Parameters 2, xhci 1.1 only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) struct xhci_cap_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) __le32 hc_capbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) __le32 hcs_params1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) __le32 hcs_params2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) __le32 hcs_params3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) __le32 hcc_params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) __le32 db_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) __le32 run_regs_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) __le32 hcc_params2; /* xhci 1.1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /* Reserved up to (CAPLENGTH - 0x1C) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /* hc_capbase bitmasks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /* bits 7:0 - how long is the Capabilities register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define HC_LENGTH(p) XHCI_HC_LENGTH(p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /* bits 31:16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define HC_VERSION(p) (((p) >> 16) & 0xffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* HCSPARAMS1 - hcs_params1 - bitmasks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /* bits 0:7, Max Device Slots */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define HCS_MAX_SLOTS(p) (((p) >> 0) & 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define HCS_SLOTS_MASK 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /* bits 8:18, Max Interrupters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define HCS_MAX_INTRS(p) (((p) >> 8) & 0x7ff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /* bits 24:31, Max Ports - max value is 0x7F = 127 ports */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define HCS_MAX_PORTS(p) (((p) >> 24) & 0x7f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /* HCSPARAMS2 - hcs_params2 - bitmasks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /* bits 0:3, frames or uframes that SW needs to queue transactions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * ahead of the HW to meet periodic deadlines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define HCS_IST(p) (((p) >> 0) & 0xf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /* bits 4:7, max number of Event Ring segments */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define HCS_ERST_MAX(p) (((p) >> 4) & 0xf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* bits 21:25 Hi 5 bits of Scratchpad buffers SW must allocate for the HW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /* bit 26 Scratchpad restore - for save/restore HW state - not used yet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /* bits 27:31 Lo 5 bits of Scratchpad buffers SW must allocate for the HW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define HCS_MAX_SCRATCHPAD(p) ((((p) >> 16) & 0x3e0) | (((p) >> 27) & 0x1f))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /* HCSPARAMS3 - hcs_params3 - bitmasks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /* bits 0:7, Max U1 to U0 latency for the roothub ports */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define HCS_U1_LATENCY(p) (((p) >> 0) & 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /* bits 16:31, Max U2 to U0 latency for the roothub ports */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define HCS_U2_LATENCY(p) (((p) >> 16) & 0xffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /* HCCPARAMS - hcc_params - bitmasks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /* true: HC can use 64-bit address pointers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define HCC_64BIT_ADDR(p) ((p) & (1 << 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /* true: HC can do bandwidth negotiation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define HCC_BANDWIDTH_NEG(p) ((p) & (1 << 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /* true: HC uses 64-byte Device Context structures
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * FIXME 64-byte context structures aren't supported yet.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define HCC_64BYTE_CONTEXT(p) ((p) & (1 << 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /* true: HC has port power switches */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define HCC_PPC(p) ((p) & (1 << 3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /* true: HC has port indicators */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define HCS_INDICATOR(p) ((p) & (1 << 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /* true: HC has Light HC Reset Capability */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define HCC_LIGHT_RESET(p) ((p) & (1 << 5))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /* true: HC supports latency tolerance messaging */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define HCC_LTC(p) ((p) & (1 << 6))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /* true: no secondary Stream ID Support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define HCC_NSS(p) ((p) & (1 << 7))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /* true: HC supports Stopped - Short Packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define HCC_SPC(p) ((p) & (1 << 9))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /* true: HC has Contiguous Frame ID Capability */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define HCC_CFC(p) ((p) & (1 << 11))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /* Max size for Primary Stream Arrays - 2^(n+1), where n is bits 12:15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define HCC_MAX_PSA(p) (1 << ((((p) >> 12) & 0xf) + 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /* Extended Capabilities pointer from PCI base - section 5.3.6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define HCC_EXT_CAPS(p) XHCI_HCC_EXT_CAPS(p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define CTX_SIZE(_hcc) (HCC_64BYTE_CONTEXT(_hcc) ? 64 : 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /* db_off bitmask - bits 0:1 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define DBOFF_MASK (~0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /* run_regs_off bitmask - bits 0:4 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define RTSOFF_MASK (~0x1f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /* HCCPARAMS2 - hcc_params2 - bitmasks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /* true: HC supports U3 entry Capability */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define HCC2_U3C(p) ((p) & (1 << 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /* true: HC supports Configure endpoint command Max exit latency too large */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define HCC2_CMC(p) ((p) & (1 << 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) /* true: HC supports Force Save context Capability */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define HCC2_FSC(p) ((p) & (1 << 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /* true: HC supports Compliance Transition Capability */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define HCC2_CTC(p) ((p) & (1 << 3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /* true: HC support Large ESIT payload Capability > 48k */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define HCC2_LEC(p) ((p) & (1 << 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) /* true: HC support Configuration Information Capability */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define HCC2_CIC(p) ((p) & (1 << 5))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /* true: HC support Extended TBC Capability, Isoc burst count > 65535 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define HCC2_ETC(p) ((p) & (1 << 6))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) /* Number of registers per port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define NUM_PORT_REGS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define PORTSC 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define PORTPMSC 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define PORTLI 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define PORTHLPMC 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) * struct xhci_op_regs - xHCI Host Controller Operational Registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) * @command: USBCMD - xHC command register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) * @status: USBSTS - xHC status register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) * @page_size: This indicates the page size that the host controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * supports. If bit n is set, the HC supports a page size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) * of 2^(n+12), up to a 128MB page size.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) * 4K is the minimum page size.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * @cmd_ring: CRP - 64-bit Command Ring Pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) * @dcbaa_ptr: DCBAAP - 64-bit Device Context Base Address Array Pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) * @config_reg: CONFIG - Configure Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) * @port_status_base: PORTSCn - base address for Port Status and Control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) * Each port has a Port Status and Control register,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) * followed by a Port Power Management Status and Control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) * register, a Port Link Info register, and a reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) * register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) * @port_power_base: PORTPMSCn - base address for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) * Port Power Management Status and Control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) * @port_link_base: PORTLIn - base address for Port Link Info (current
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) * Link PM state and control) for USB 2.1 and USB 3.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) * devices.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) struct xhci_op_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) __le32 command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) __le32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) __le32 page_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) __le32 reserved1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) __le32 reserved2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) __le32 dev_notification;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) __le64 cmd_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /* rsvd: offset 0x20-2F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) __le32 reserved3[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) __le64 dcbaa_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) __le32 config_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /* rsvd: offset 0x3C-3FF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) __le32 reserved4[241];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) /* port 1 registers, which serve as a base address for other ports */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) __le32 port_status_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) __le32 port_power_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) __le32 port_link_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) __le32 reserved5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) /* registers for ports 2-255 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) __le32 reserved6[NUM_PORT_REGS*254];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) /* USBCMD - USB command - command bitmasks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) /* start/stop HC execution - do not write unless HC is halted*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define CMD_RUN XHCI_CMD_RUN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) /* Reset HC - resets internal HC state machine and all registers (except
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) * PCI config regs). HC does NOT drive a USB reset on the downstream ports.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) * The xHCI driver must reinitialize the xHC after setting this bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define CMD_RESET (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) /* Event Interrupt Enable - a '1' allows interrupts from the host controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define CMD_EIE XHCI_CMD_EIE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /* Host System Error Interrupt Enable - get out-of-band signal for HC errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define CMD_HSEIE XHCI_CMD_HSEIE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) /* bits 4:6 are reserved (and should be preserved on writes). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) /* light reset (port status stays unchanged) - reset completed when this is 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define CMD_LRESET (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) /* host controller save/restore state. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define CMD_CSS (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define CMD_CRS (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) /* Enable Wrap Event - '1' means xHC generates an event when MFINDEX wraps. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define CMD_EWE XHCI_CMD_EWE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) /* MFINDEX power management - '1' means xHC can stop MFINDEX counter if all root
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) * hubs are in U3 (selective suspend), disconnect, disabled, or powered-off.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) * '0' means the xHC can power it off if all ports are in the disconnect,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) * disabled, or powered-off state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define CMD_PM_INDEX (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) /* bit 14 Extended TBC Enable, changes Isoc TRB fields to support larger TBC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define CMD_ETE (1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) /* bits 15:31 are reserved (and should be preserved on writes). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define XHCI_RESET_LONG_USEC (10 * 1000 * 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define XHCI_RESET_SHORT_USEC (250 * 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) /* IMAN - Interrupt Management Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define IMAN_IE (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define IMAN_IP (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) /* USBSTS - USB status - status bitmasks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) /* HC not running - set to 1 when run/stop bit is cleared. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define STS_HALT XHCI_STS_HALT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) /* serious error, e.g. PCI parity error. The HC will clear the run/stop bit. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define STS_FATAL (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) /* event interrupt - clear this prior to clearing any IP flags in IR set*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define STS_EINT (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) /* port change detect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define STS_PORT (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) /* bits 5:7 reserved and zeroed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) /* save state status - '1' means xHC is saving state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define STS_SAVE (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) /* restore state status - '1' means xHC is restoring state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define STS_RESTORE (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) /* true: save or restore error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define STS_SRE (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) /* true: Controller Not Ready to accept doorbell or op reg writes after reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define STS_CNR XHCI_STS_CNR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) /* true: internal Host Controller Error - SW needs to reset and reinitialize */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define STS_HCE (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) /* bits 13:31 reserved and should be preserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) * DNCTRL - Device Notification Control Register - dev_notification bitmasks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) * Generate a device notification event when the HC sees a transaction with a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) * notification type that matches a bit set in this bit field.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define DEV_NOTE_MASK (0xffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define ENABLE_DEV_NOTE(x) (1 << (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) /* Most of the device notification types should only be used for debug.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) * SW does need to pay attention to function wake notifications.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define DEV_NOTE_FWAKE ENABLE_DEV_NOTE(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) /* CRCR - Command Ring Control Register - cmd_ring bitmasks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) /* bit 0 is the command ring cycle state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) /* stop ring operation after completion of the currently executing command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define CMD_RING_PAUSE (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) /* stop ring immediately - abort the currently executing command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define CMD_RING_ABORT (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) /* true: command ring is running */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define CMD_RING_RUNNING (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) /* bits 4:5 reserved and should be preserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) /* Command Ring pointer - bit mask for the lower 32 bits. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define CMD_RING_RSVD_BITS (0x3f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) /* CONFIG - Configure Register - config_reg bitmasks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) /* bits 0:7 - maximum number of device slots enabled (NumSlotsEn) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define MAX_DEVS(p) ((p) & 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) /* bit 8: U3 Entry Enabled, assert PLC when root port enters U3, xhci 1.1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define CONFIG_U3E (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) /* bit 9: Configuration Information Enable, xhci 1.1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define CONFIG_CIE (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) /* bits 10:31 - reserved and should be preserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) /* PORTSC - Port Status and Control Register - port_status_base bitmasks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) /* true: device connected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define PORT_CONNECT (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) /* true: port enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define PORT_PE (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) /* bit 2 reserved and zeroed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) /* true: port has an over-current condition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define PORT_OC (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) /* true: port reset signaling asserted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define PORT_RESET (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) /* Port Link State - bits 5:8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) * A read gives the current link PM state of the port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) * a write with Link State Write Strobe set sets the link state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define PORT_PLS_MASK (0xf << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define XDEV_U0 (0x0 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define XDEV_U1 (0x1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define XDEV_U2 (0x2 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define XDEV_U3 (0x3 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define XDEV_DISABLED (0x4 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define XDEV_RXDETECT (0x5 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define XDEV_INACTIVE (0x6 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define XDEV_POLLING (0x7 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define XDEV_RECOVERY (0x8 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define XDEV_HOT_RESET (0x9 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define XDEV_COMP_MODE (0xa << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define XDEV_TEST_MODE (0xb << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define XDEV_RESUME (0xf << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) /* true: port has power (see HCC_PPC) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define PORT_POWER (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) /* bits 10:13 indicate device speed:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) * 0 - undefined speed - port hasn't be initialized by a reset yet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) * 1 - full speed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) * 2 - low speed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) * 3 - high speed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) * 4 - super speed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) * 5-15 reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define DEV_SPEED_MASK (0xf << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define XDEV_FS (0x1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define XDEV_LS (0x2 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define XDEV_HS (0x3 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define XDEV_SS (0x4 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define XDEV_SSP (0x5 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define DEV_UNDEFSPEED(p) (((p) & DEV_SPEED_MASK) == (0x0<<10))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define DEV_FULLSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_FS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define DEV_LOWSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_LS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define DEV_HIGHSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_HS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define DEV_SUPERSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_SS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define DEV_SUPERSPEEDPLUS(p) (((p) & DEV_SPEED_MASK) == XDEV_SSP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define DEV_SUPERSPEED_ANY(p) (((p) & DEV_SPEED_MASK) >= XDEV_SS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define DEV_PORT_SPEED(p) (((p) >> 10) & 0x0f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) /* Bits 20:23 in the Slot Context are the speed for the device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define SLOT_SPEED_FS (XDEV_FS << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define SLOT_SPEED_LS (XDEV_LS << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define SLOT_SPEED_HS (XDEV_HS << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define SLOT_SPEED_SS (XDEV_SS << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define SLOT_SPEED_SSP (XDEV_SSP << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) /* Port Indicator Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define PORT_LED_OFF (0 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define PORT_LED_AMBER (1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define PORT_LED_GREEN (2 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define PORT_LED_MASK (3 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) /* Port Link State Write Strobe - set this when changing link state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define PORT_LINK_STROBE (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) /* true: connect status change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define PORT_CSC (1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) /* true: port enable change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define PORT_PEC (1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) /* true: warm reset for a USB 3.0 device is done. A "hot" reset puts the port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) * into an enabled state, and the device into the default state. A "warm" reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) * also resets the link, forcing the device through the link training sequence.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) * SW can also look at the Port Reset register to see when warm reset is done.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define PORT_WRC (1 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) /* true: over-current change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define PORT_OCC (1 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) /* true: reset change - 1 to 0 transition of PORT_RESET */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define PORT_RC (1 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) /* port link status change - set on some port link state transitions:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) * Transition Reason
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) * ------------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) * - U3 to Resume Wakeup signaling from a device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) * - Resume to Recovery to U0 USB 3.0 device resume
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) * - Resume to U0 USB 2.0 device resume
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) * - U3 to Recovery to U0 Software resume of USB 3.0 device complete
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) * - U3 to U0 Software resume of USB 2.0 device complete
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) * - U2 to U0 L1 resume of USB 2.1 device complete
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) * - U0 to U0 (???) L1 entry rejection by USB 2.1 device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) * - U0 to disabled L1 entry error with USB 2.1 device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) * - Any state to inactive Error on USB 3.0 port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define PORT_PLC (1 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) /* port configure error change - port failed to configure its link partner */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define PORT_CEC (1 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define PORT_CHANGE_MASK (PORT_CSC | PORT_PEC | PORT_WRC | PORT_OCC | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) PORT_RC | PORT_PLC | PORT_CEC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) /* Cold Attach Status - xHC can set this bit to report device attached during
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) * Sx state. Warm port reset should be perfomed to clear this bit and move port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) * to connected state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define PORT_CAS (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) /* wake on connect (enable) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #define PORT_WKCONN_E (1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) /* wake on disconnect (enable) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #define PORT_WKDISC_E (1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) /* wake on over-current (enable) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define PORT_WKOC_E (1 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) /* bits 28:29 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) /* true: device is non-removable - for USB 3.0 roothub emulation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #define PORT_DEV_REMOVE (1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) /* Initiate a warm port reset - complete when PORT_WRC is '1' */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #define PORT_WR (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) /* We mark duplicate entries with -1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) #define DUPLICATE_ENTRY ((u8)(-1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) /* Port Power Management Status and Control - port_power_base bitmasks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) /* Inactivity timer value for transitions into U1, in microseconds.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) * Timeout can be up to 127us. 0xFF means an infinite timeout.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) #define PORT_U1_TIMEOUT(p) ((p) & 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) #define PORT_U1_TIMEOUT_MASK 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) /* Inactivity timer value for transitions into U2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #define PORT_U2_TIMEOUT(p) (((p) & 0xff) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) #define PORT_U2_TIMEOUT_MASK (0xff << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) /* Bits 24:31 for port testing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) /* USB2 Protocol PORTSPMSC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) #define PORT_L1S_MASK 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) #define PORT_L1S_SUCCESS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) #define PORT_RWE (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) #define PORT_HIRD(p) (((p) & 0xf) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) #define PORT_HIRD_MASK (0xf << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) #define PORT_L1DS_MASK (0xff << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) #define PORT_L1DS(p) (((p) & 0xff) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) #define PORT_HLE (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) #define PORT_TEST_MODE_SHIFT 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) /* USB3 Protocol PORTLI Port Link Information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) #define PORT_RX_LANES(p) (((p) >> 16) & 0xf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) #define PORT_TX_LANES(p) (((p) >> 20) & 0xf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) /* USB2 Protocol PORTHLPMC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) #define PORT_HIRDM(p)((p) & 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) #define PORT_L1_TIMEOUT(p)(((p) & 0xff) << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) #define PORT_BESLD(p)(((p) & 0xf) << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) /* use 512 microseconds as USB2 LPM L1 default timeout. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) #define XHCI_L1_TIMEOUT 512
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) /* Set default HIRD/BESL value to 4 (350/400us) for USB2 L1 LPM resume latency.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) * Safe to use with mixed HIRD and BESL systems (host and device) and is used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) * by other operating systems.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) * XHCI 1.0 errata 8/14/12 Table 13 notes:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) * "Software should choose xHC BESL/BESLD field values that do not violate a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) * device's resume latency requirements,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) * e.g. not program values > '4' if BLC = '1' and a HIRD device is attached,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) * or not program values < '4' if BLC = '0' and a BESL device is attached.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) #define XHCI_DEFAULT_BESL 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) * USB3 specification define a 360ms tPollingLFPSTiemout for USB3 ports
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) * to complete link training. usually link trainig completes much faster
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) * so check status 10 times with 36ms sleep in places we need to wait for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) * polling to complete.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) #define XHCI_PORT_POLLING_LFPS_TIME 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) * struct xhci_intr_reg - Interrupt Register Set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) * @irq_pending: IMAN - Interrupt Management Register. Used to enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) * interrupts and check for pending interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) * @irq_control: IMOD - Interrupt Moderation Register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) * Used to throttle interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) * @erst_size: Number of segments in the Event Ring Segment Table (ERST).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) * @erst_base: ERST base address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) * @erst_dequeue: Event ring dequeue pointer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) * Each interrupter (defined by a MSI-X vector) has an event ring and an Event
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) * Ring Segment Table (ERST) associated with it. The event ring is comprised of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) * multiple segments of the same size. The HC places events on the ring and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) * "updates the Cycle bit in the TRBs to indicate to software the current
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) * position of the Enqueue Pointer." The HCD (Linux) processes those events and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) * updates the dequeue pointer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) struct xhci_intr_reg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) __le32 irq_pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) __le32 irq_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) __le32 erst_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) __le32 rsvd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) __le64 erst_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) __le64 erst_dequeue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) /* irq_pending bitmasks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) #define ER_IRQ_PENDING(p) ((p) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) /* bits 2:31 need to be preserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) /* THIS IS BUGGY - FIXME - IP IS WRITE 1 TO CLEAR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) #define ER_IRQ_CLEAR(p) ((p) & 0xfffffffe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) #define ER_IRQ_ENABLE(p) ((ER_IRQ_CLEAR(p)) | 0x2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) #define ER_IRQ_DISABLE(p) ((ER_IRQ_CLEAR(p)) & ~(0x2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) /* irq_control bitmasks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) /* Minimum interval between interrupts (in 250ns intervals). The interval
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) * between interrupts will be longer if there are no events on the event ring.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) * Default is 4000 (1 ms).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) #define ER_IRQ_INTERVAL_MASK (0xffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) /* Counter used to count down the time to the next interrupt - HW use only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) #define ER_IRQ_COUNTER_MASK (0xffff << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) /* erst_size bitmasks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) /* Preserve bits 16:31 of erst_size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) #define ERST_SIZE_MASK (0xffff << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) /* erst_dequeue bitmasks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) /* Dequeue ERST Segment Index (DESI) - Segment number (or alias)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) * where the current dequeue pointer lies. This is an optional HW hint.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) #define ERST_DESI_MASK (0x7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) /* Event Handler Busy (EHB) - is the event ring scheduled to be serviced by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) * a work queue (or delayed service routine)?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) #define ERST_EHB (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) #define ERST_PTR_MASK (0xf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) * struct xhci_run_regs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) * @microframe_index:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) * MFINDEX - current microframe number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) * Section 5.5 Host Controller Runtime Registers:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) * "Software should read and write these registers using only Dword (32 bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) * or larger accesses"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) struct xhci_run_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) __le32 microframe_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) __le32 rsvd[7];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) struct xhci_intr_reg ir_set[128];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) * struct doorbell_array
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) * Bits 0 - 7: Endpoint target
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) * Bits 8 - 15: RsvdZ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) * Bits 16 - 31: Stream ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) * Section 5.6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) struct xhci_doorbell_array {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) __le32 doorbell[256];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) #define DB_VALUE(ep, stream) ((((ep) + 1) & 0xff) | ((stream) << 16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) #define DB_VALUE_HOST 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) * struct xhci_protocol_caps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) * @revision: major revision, minor revision, capability ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) * and next capability pointer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) * @name_string: Four ASCII characters to say which spec this xHC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) * follows, typically "USB ".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) * @port_info: Port offset, count, and protocol-defined information.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) struct xhci_protocol_caps {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) u32 revision;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) u32 name_string;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) u32 port_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) #define XHCI_EXT_PORT_MAJOR(x) (((x) >> 24) & 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) #define XHCI_EXT_PORT_MINOR(x) (((x) >> 16) & 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) #define XHCI_EXT_PORT_PSIC(x) (((x) >> 28) & 0x0f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) #define XHCI_EXT_PORT_OFF(x) ((x) & 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) #define XHCI_EXT_PORT_COUNT(x) (((x) >> 8) & 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) #define XHCI_EXT_PORT_PSIV(x) (((x) >> 0) & 0x0f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) #define XHCI_EXT_PORT_PSIE(x) (((x) >> 4) & 0x03)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) #define XHCI_EXT_PORT_PLT(x) (((x) >> 6) & 0x03)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) #define XHCI_EXT_PORT_PFD(x) (((x) >> 8) & 0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) #define XHCI_EXT_PORT_LP(x) (((x) >> 14) & 0x03)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) #define XHCI_EXT_PORT_PSIM(x) (((x) >> 16) & 0xffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) #define PLT_MASK (0x03 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) #define PLT_SYM (0x00 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) #define PLT_ASYM_RX (0x02 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) #define PLT_ASYM_TX (0x03 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) * struct xhci_container_ctx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) * @type: Type of context. Used to calculated offsets to contained contexts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) * @size: Size of the context data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) * @bytes: The raw context data given to HW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) * @dma: dma address of the bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) * Represents either a Device or Input context. Holds a pointer to the raw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) * memory used for the context (bytes) and dma address of it (dma).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) struct xhci_container_ctx {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) unsigned type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) #define XHCI_CTX_TYPE_DEVICE 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) #define XHCI_CTX_TYPE_INPUT 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) int size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) u8 *bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) dma_addr_t dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) * struct xhci_slot_ctx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) * @dev_info: Route string, device speed, hub info, and last valid endpoint
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) * @dev_info2: Max exit latency for device number, root hub port number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) * @tt_info: tt_info is used to construct split transaction tokens
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) * @dev_state: slot state and device address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) * Slot Context - section 6.2.1.1. This assumes the HC uses 32-byte context
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) * reserved at the end of the slot context for HC internal use.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) struct xhci_slot_ctx {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) __le32 dev_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) __le32 dev_info2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) __le32 tt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) __le32 dev_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) /* offset 0x10 to 0x1f reserved for HC internal use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) __le32 reserved[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) /* dev_info bitmasks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) /* Route String - 0:19 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) #define ROUTE_STRING_MASK (0xfffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) /* Device speed - values defined by PORTSC Device Speed field - 20:23 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) #define DEV_SPEED (0xf << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) #define GET_DEV_SPEED(n) (((n) & DEV_SPEED) >> 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) /* bit 24 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) /* Is this LS/FS device connected through a HS hub? - bit 25 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) #define DEV_MTT (0x1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) /* Set if the device is a hub - bit 26 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) #define DEV_HUB (0x1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) /* Index of the last valid endpoint context in this device context - 27:31 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) #define LAST_CTX_MASK (0x1f << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) #define LAST_CTX(p) ((p) << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) #define LAST_CTX_TO_EP_NUM(p) (((p) >> 27) - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) #define SLOT_FLAG (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) #define EP0_FLAG (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) /* dev_info2 bitmasks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) /* Max Exit Latency (ms) - worst case time to wake up all links in dev path */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) #define MAX_EXIT (0xffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) /* Root hub port number that is needed to access the USB device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) #define ROOT_HUB_PORT(p) (((p) & 0xff) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) #define DEVINFO_TO_ROOT_HUB_PORT(p) (((p) >> 16) & 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) /* Maximum number of ports under a hub device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) #define XHCI_MAX_PORTS(p) (((p) & 0xff) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) #define DEVINFO_TO_MAX_PORTS(p) (((p) & (0xff << 24)) >> 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) /* tt_info bitmasks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) * TT Hub Slot ID - for low or full speed devices attached to a high-speed hub
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) * The Slot ID of the hub that isolates the high speed signaling from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) * this low or full-speed device. '0' if attached to root hub port.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) #define TT_SLOT (0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) * The number of the downstream facing port of the high-speed hub
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) * '0' if the device is not low or full speed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) #define TT_PORT (0xff << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) #define TT_THINK_TIME(p) (((p) & 0x3) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) #define GET_TT_THINK_TIME(p) (((p) & (0x3 << 16)) >> 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) /* dev_state bitmasks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) /* USB device address - assigned by the HC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) #define DEV_ADDR_MASK (0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) /* bits 8:26 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) /* Slot state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) #define SLOT_STATE (0x1f << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) #define GET_SLOT_STATE(p) (((p) & (0x1f << 27)) >> 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) #define SLOT_STATE_DISABLED 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) #define SLOT_STATE_ENABLED SLOT_STATE_DISABLED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) #define SLOT_STATE_DEFAULT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) #define SLOT_STATE_ADDRESSED 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) #define SLOT_STATE_CONFIGURED 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) * struct xhci_ep_ctx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) * @ep_info: endpoint state, streams, mult, and interval information.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) * @ep_info2: information on endpoint type, max packet size, max burst size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) * error count, and whether the HC will force an event for all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) * transactions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) * @deq: 64-bit ring dequeue pointer address. If the endpoint only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) * defines one stream, this points to the endpoint transfer ring.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) * Otherwise, it points to a stream context array, which has a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) * ring pointer for each flow.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) * @tx_info:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) * Average TRB lengths for the endpoint ring and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) * max payload within an Endpoint Service Interval Time (ESIT).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) * Endpoint Context - section 6.2.1.2. This assumes the HC uses 32-byte context
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) * reserved at the end of the endpoint context for HC internal use.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) struct xhci_ep_ctx {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) __le32 ep_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) __le32 ep_info2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) __le64 deq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) __le32 tx_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) /* offset 0x14 - 0x1f reserved for HC internal use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) __le32 reserved[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) /* ep_info bitmasks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) * Endpoint State - bits 0:2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) * 0 - disabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) * 1 - running
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) * 2 - halted due to halt condition - ok to manipulate endpoint ring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) * 3 - stopped
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) * 4 - TRB error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) * 5-7 - reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) #define EP_STATE_MASK (0x7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) #define EP_STATE_DISABLED 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) #define EP_STATE_RUNNING 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) #define EP_STATE_HALTED 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) #define EP_STATE_STOPPED 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) #define EP_STATE_ERROR 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) #define GET_EP_CTX_STATE(ctx) (le32_to_cpu((ctx)->ep_info) & EP_STATE_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) /* Mult - Max number of burtst within an interval, in EP companion desc. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) #define EP_MULT(p) (((p) & 0x3) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) #define CTX_TO_EP_MULT(p) (((p) >> 8) & 0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) /* bits 10:14 are Max Primary Streams */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) /* bit 15 is Linear Stream Array */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) /* Interval - period between requests to an endpoint - 125u increments. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) #define EP_INTERVAL(p) (((p) & 0xff) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) #define EP_INTERVAL_TO_UFRAMES(p) (1 << (((p) >> 16) & 0xff))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) #define CTX_TO_EP_INTERVAL(p) (((p) >> 16) & 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) #define EP_MAXPSTREAMS_MASK (0x1f << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) #define EP_MAXPSTREAMS(p) (((p) << 10) & EP_MAXPSTREAMS_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) #define CTX_TO_EP_MAXPSTREAMS(p) (((p) & EP_MAXPSTREAMS_MASK) >> 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) /* Endpoint is set up with a Linear Stream Array (vs. Secondary Stream Array) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) #define EP_HAS_LSA (1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) /* hosts with LEC=1 use bits 31:24 as ESIT high bits. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) #define CTX_TO_MAX_ESIT_PAYLOAD_HI(p) (((p) >> 24) & 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) /* ep_info2 bitmasks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) * Force Event - generate transfer events for all TRBs for this endpoint
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) * This will tell the HC to ignore the IOC and ISP flags (for debugging only).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) #define FORCE_EVENT (0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) #define ERROR_COUNT(p) (((p) & 0x3) << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) #define CTX_TO_EP_TYPE(p) (((p) >> 3) & 0x7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) #define EP_TYPE(p) ((p) << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) #define ISOC_OUT_EP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) #define BULK_OUT_EP 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) #define INT_OUT_EP 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) #define CTRL_EP 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) #define ISOC_IN_EP 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) #define BULK_IN_EP 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) #define INT_IN_EP 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) /* bit 6 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) /* bit 7 is Host Initiate Disable - for disabling stream selection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) #define MAX_BURST(p) (((p)&0xff) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) #define CTX_TO_MAX_BURST(p) (((p) >> 8) & 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) #define MAX_PACKET(p) (((p)&0xffff) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) #define MAX_PACKET_MASK (0xffff << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) #define MAX_PACKET_DECODED(p) (((p) >> 16) & 0xffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) /* tx_info bitmasks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) #define EP_AVG_TRB_LENGTH(p) ((p) & 0xffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) #define EP_MAX_ESIT_PAYLOAD_LO(p) (((p) & 0xffff) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) #define EP_MAX_ESIT_PAYLOAD_HI(p) ((((p) >> 16) & 0xff) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) #define CTX_TO_MAX_ESIT_PAYLOAD(p) (((p) >> 16) & 0xffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) /* deq bitmasks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) #define EP_CTX_CYCLE_MASK (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) #define SCTX_DEQ_MASK (~0xfL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) * struct xhci_input_control_context
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) * Input control context; see section 6.2.5.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) * @drop_context: set the bit of the endpoint context you want to disable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) * @add_context: set the bit of the endpoint context you want to enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) struct xhci_input_control_ctx {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) __le32 drop_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) __le32 add_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) __le32 rsvd2[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) #define EP_IS_ADDED(ctrl_ctx, i) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) (le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) #define EP_IS_DROPPED(ctrl_ctx, i) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) (le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) /* Represents everything that is needed to issue a command on the command ring.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) * It's useful to pre-allocate these for commands that cannot fail due to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) * out-of-memory errors, like freeing streams.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) struct xhci_command {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) /* Input context for changing device state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) struct xhci_container_ctx *in_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) int slot_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) /* If completion is null, no one is waiting on this command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) * and the structure can be freed after the command completes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) struct completion *completion;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) union xhci_trb *command_trb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) struct list_head cmd_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) ANDROID_KABI_RESERVE(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) ANDROID_KABI_RESERVE(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) /* drop context bitmasks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) #define DROP_EP(x) (0x1 << x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) /* add context bitmasks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) #define ADD_EP(x) (0x1 << x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) struct xhci_stream_ctx {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) /* 64-bit stream ring address, cycle state, and stream type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) __le64 stream_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) /* offset 0x14 - 0x1f reserved for HC internal use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) __le32 reserved[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) /* Stream Context Types (section 6.4.1) - bits 3:1 of stream ctx deq ptr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) #define SCT_FOR_CTX(p) (((p) & 0x7) << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) /* Secondary stream array type, dequeue pointer is to a transfer ring */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) #define SCT_SEC_TR 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) /* Primary stream array type, dequeue pointer is to a transfer ring */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) #define SCT_PRI_TR 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) /* Dequeue pointer is for a secondary stream array (SSA) with 8 entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) #define SCT_SSA_8 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) #define SCT_SSA_16 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) #define SCT_SSA_32 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) #define SCT_SSA_64 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) #define SCT_SSA_128 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) #define SCT_SSA_256 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) /* Assume no secondary streams for now */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) struct xhci_stream_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) struct xhci_ring **stream_rings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) /* Number of streams, including stream 0 (which drivers can't use) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) unsigned int num_streams;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) /* The stream context array may be bigger than
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) * the number of streams the driver asked for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) struct xhci_stream_ctx *stream_ctx_array;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) unsigned int num_stream_ctxs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) dma_addr_t ctx_array_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) /* For mapping physical TRB addresses to segments in stream rings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) struct radix_tree_root trb_address_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) struct xhci_command *free_streams_command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) #define SMALL_STREAM_ARRAY_SIZE 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) #define MEDIUM_STREAM_ARRAY_SIZE 1024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) /* Some Intel xHCI host controllers need software to keep track of the bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) * bandwidth. Keep track of endpoint info here. Each root port is allocated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) * the full bus bandwidth. We must also treat TTs (including each port under a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) * multi-TT hub) as a separate bandwidth domain. The direct memory interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) * (DMI) also limits the total bandwidth (across all domains) that can be used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) struct xhci_bw_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) /* ep_interval is zero-based */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) unsigned int ep_interval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) /* mult and num_packets are one-based */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) unsigned int mult;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) unsigned int num_packets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) unsigned int max_packet_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) unsigned int max_esit_payload;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) unsigned int type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) /* "Block" sizes in bytes the hardware uses for different device speeds.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) * The logic in this part of the hardware limits the number of bits the hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) * can use, so must represent bandwidth in a less precise manner to mimic what
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) * the scheduler hardware computes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) #define FS_BLOCK 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) #define HS_BLOCK 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) #define SS_BLOCK 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) #define DMI_BLOCK 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) /* Each device speed has a protocol overhead (CRC, bit stuffing, etc) associated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) * with each byte transferred. SuperSpeed devices have an initial overhead to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) * set up bursts. These are in blocks, see above. LS overhead has already been
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) * translated into FS blocks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) #define DMI_OVERHEAD 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) #define DMI_OVERHEAD_BURST 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) #define SS_OVERHEAD 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) #define SS_OVERHEAD_BURST 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) #define HS_OVERHEAD 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) #define FS_OVERHEAD 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) #define LS_OVERHEAD 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) /* The TTs need to claim roughly twice as much bandwidth (94 bytes per
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) * microframe ~= 24Mbps) of the HS bus as the devices can actually use because
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) * of overhead associated with split transfers crossing microframe boundaries.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) * 31 blocks is pure protocol overhead.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) #define TT_HS_OVERHEAD (31 + 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) #define TT_DMI_OVERHEAD (25 + 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) /* Bandwidth limits in blocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) #define FS_BW_LIMIT 1285
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) #define TT_BW_LIMIT 1320
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) #define HS_BW_LIMIT 1607
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) #define SS_BW_LIMIT_IN 3906
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) #define DMI_BW_LIMIT_IN 3906
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) #define SS_BW_LIMIT_OUT 3906
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) #define DMI_BW_LIMIT_OUT 3906
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) /* Percentage of bus bandwidth reserved for non-periodic transfers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) #define FS_BW_RESERVED 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) #define HS_BW_RESERVED 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) #define SS_BW_RESERVED 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) struct xhci_virt_ep {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) struct xhci_virt_device *vdev; /* parent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) unsigned int ep_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) struct xhci_ring *ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) /* Related to endpoints that are configured to use stream IDs only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) struct xhci_stream_info *stream_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) /* Temporary storage in case the configure endpoint command fails and we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) * have to restore the device state to the previous state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) struct xhci_ring *new_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) unsigned int ep_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) #define SET_DEQ_PENDING (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) #define EP_HALTED (1 << 1) /* For stall handling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) #define EP_STOP_CMD_PENDING (1 << 2) /* For URB cancellation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) /* Transitioning the endpoint to using streams, don't enqueue URBs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) #define EP_GETTING_STREAMS (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) #define EP_HAS_STREAMS (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) /* Transitioning the endpoint to not using streams, don't enqueue URBs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) #define EP_GETTING_NO_STREAMS (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) #define EP_HARD_CLEAR_TOGGLE (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) #define EP_SOFT_CLEAR_TOGGLE (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) /* usb_hub_clear_tt_buffer is in progress */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) #define EP_CLEARING_TT (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) /* ---- Related to URB cancellation ---- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) struct list_head cancelled_td_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) /* Watchdog timer for stop endpoint command to cancel URBs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) struct timer_list stop_cmd_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) struct xhci_hcd *xhci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) /* Dequeue pointer and dequeue segment for a submitted Set TR Dequeue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) * command. We'll need to update the ring's dequeue segment and dequeue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) * pointer after the command completes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) struct xhci_segment *queued_deq_seg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) union xhci_trb *queued_deq_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) * Sometimes the xHC can not process isochronous endpoint ring quickly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) * enough, and it will miss some isoc tds on the ring and generate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) * a Missed Service Error Event.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) * Set skip flag when receive a Missed Service Error Event and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) * process the missed tds on the endpoint ring.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) bool skip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) /* Bandwidth checking storage */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) struct xhci_bw_info bw_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) struct list_head bw_endpoint_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) /* Isoch Frame ID checking storage */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) int next_frame_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) /* Use new Isoch TRB layout needed for extended TBC support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) bool use_extended_tbc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) enum xhci_overhead_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) LS_OVERHEAD_TYPE = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) FS_OVERHEAD_TYPE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) HS_OVERHEAD_TYPE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) struct xhci_interval_bw {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) unsigned int num_packets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) /* Sorted by max packet size.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) * Head of the list is the greatest max packet size.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) struct list_head endpoints;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) /* How many endpoints of each speed are present. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) unsigned int overhead[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) #define XHCI_MAX_INTERVAL 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) struct xhci_interval_bw_table {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) unsigned int interval0_esit_payload;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) struct xhci_interval_bw interval_bw[XHCI_MAX_INTERVAL];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) /* Includes reserved bandwidth for async endpoints */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) unsigned int bw_used;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) unsigned int ss_bw_in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) unsigned int ss_bw_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) #define EP_CTX_PER_DEV 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) struct xhci_virt_device {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) int slot_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) struct usb_device *udev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) * Commands to the hardware are passed an "input context" that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) * tells the hardware what to change in its data structures.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) * The hardware will return changes in an "output context" that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) * software must allocate for the hardware. We need to keep
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) * track of input and output contexts separately because
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) * these commands might fail and we don't trust the hardware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) struct xhci_container_ctx *out_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) /* Used for addressing devices and configuration changes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) struct xhci_container_ctx *in_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) struct xhci_virt_ep eps[EP_CTX_PER_DEV];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) u8 fake_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) u8 real_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) struct xhci_interval_bw_table *bw_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) struct xhci_tt_bw_info *tt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) * flags for state tracking based on events and issued commands.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) * Software can not rely on states from output contexts because of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) * latency between events and xHC updating output context values.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) * See xhci 1.1 section 4.8.3 for more details
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) #define VDEV_PORT_ERROR BIT(0) /* Port error, link inactive */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) /* The current max exit latency for the enabled USB3 link states. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) u16 current_mel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) /* Used for the debugfs interfaces. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) void *debugfs_private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) * For each roothub, keep track of the bandwidth information for each periodic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) * interval.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) * If a high speed hub is attached to the roothub, each TT associated with that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) * hub is a separate bandwidth domain. The interval information for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) * endpoints on the devices under that TT will appear in the TT structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) struct xhci_root_port_bw_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) struct list_head tts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) unsigned int num_active_tts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) struct xhci_interval_bw_table bw_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) struct xhci_tt_bw_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) struct list_head tt_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) int slot_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) int ttport;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) struct xhci_interval_bw_table bw_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) int active_eps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) * struct xhci_device_context_array
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) * @dev_context_ptr array of 64-bit DMA addresses for device contexts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) struct xhci_device_context_array {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) /* 64-bit device addresses; we only write 32-bit addresses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) __le64 dev_context_ptrs[MAX_HC_SLOTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) /* private xHCD pointers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) dma_addr_t dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) /* TODO: write function to set the 64-bit device DMA address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) * TODO: change this to be dynamically sized at HC mem init time since the HC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) * might not be able to handle the maximum number of devices possible.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) struct xhci_transfer_event {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) /* 64-bit buffer address, or immediate data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) __le64 buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) __le32 transfer_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) /* This field is interpreted differently based on the type of TRB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) __le32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) /* Transfer event TRB length bit mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) /* bits 0:23 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) #define EVENT_TRB_LEN(p) ((p) & 0xffffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) /** Transfer Event bit fields **/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) #define TRB_TO_EP_ID(p) (((p) >> 16) & 0x1f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) /* Completion Code - only applicable for some types of TRBs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) #define COMP_CODE_MASK (0xff << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) #define GET_COMP_CODE(p) (((p) & COMP_CODE_MASK) >> 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) #define COMP_INVALID 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) #define COMP_SUCCESS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) #define COMP_DATA_BUFFER_ERROR 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) #define COMP_BABBLE_DETECTED_ERROR 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) #define COMP_USB_TRANSACTION_ERROR 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) #define COMP_TRB_ERROR 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) #define COMP_STALL_ERROR 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) #define COMP_RESOURCE_ERROR 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) #define COMP_BANDWIDTH_ERROR 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) #define COMP_NO_SLOTS_AVAILABLE_ERROR 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) #define COMP_INVALID_STREAM_TYPE_ERROR 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) #define COMP_SLOT_NOT_ENABLED_ERROR 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) #define COMP_ENDPOINT_NOT_ENABLED_ERROR 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) #define COMP_SHORT_PACKET 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) #define COMP_RING_UNDERRUN 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) #define COMP_RING_OVERRUN 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) #define COMP_VF_EVENT_RING_FULL_ERROR 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) #define COMP_PARAMETER_ERROR 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) #define COMP_BANDWIDTH_OVERRUN_ERROR 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) #define COMP_CONTEXT_STATE_ERROR 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) #define COMP_NO_PING_RESPONSE_ERROR 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) #define COMP_EVENT_RING_FULL_ERROR 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) #define COMP_INCOMPATIBLE_DEVICE_ERROR 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) #define COMP_MISSED_SERVICE_ERROR 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) #define COMP_COMMAND_RING_STOPPED 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) #define COMP_COMMAND_ABORTED 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) #define COMP_STOPPED 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) #define COMP_STOPPED_LENGTH_INVALID 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) #define COMP_STOPPED_SHORT_PACKET 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) #define COMP_MAX_EXIT_LATENCY_TOO_LARGE_ERROR 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) #define COMP_ISOCH_BUFFER_OVERRUN 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) #define COMP_EVENT_LOST_ERROR 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) #define COMP_UNDEFINED_ERROR 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) #define COMP_INVALID_STREAM_ID_ERROR 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) #define COMP_SECONDARY_BANDWIDTH_ERROR 35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) #define COMP_SPLIT_TRANSACTION_ERROR 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) static inline const char *xhci_trb_comp_code_string(u8 status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) switch (status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) case COMP_INVALID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) return "Invalid";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) case COMP_SUCCESS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) return "Success";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) case COMP_DATA_BUFFER_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) return "Data Buffer Error";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) case COMP_BABBLE_DETECTED_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) return "Babble Detected";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) case COMP_USB_TRANSACTION_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) return "USB Transaction Error";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) case COMP_TRB_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) return "TRB Error";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) case COMP_STALL_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) return "Stall Error";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) case COMP_RESOURCE_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) return "Resource Error";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) case COMP_BANDWIDTH_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) return "Bandwidth Error";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) case COMP_NO_SLOTS_AVAILABLE_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) return "No Slots Available Error";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) case COMP_INVALID_STREAM_TYPE_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) return "Invalid Stream Type Error";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) case COMP_SLOT_NOT_ENABLED_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) return "Slot Not Enabled Error";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) case COMP_ENDPOINT_NOT_ENABLED_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) return "Endpoint Not Enabled Error";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) case COMP_SHORT_PACKET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) return "Short Packet";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) case COMP_RING_UNDERRUN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) return "Ring Underrun";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) case COMP_RING_OVERRUN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) return "Ring Overrun";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) case COMP_VF_EVENT_RING_FULL_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) return "VF Event Ring Full Error";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) case COMP_PARAMETER_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) return "Parameter Error";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) case COMP_BANDWIDTH_OVERRUN_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) return "Bandwidth Overrun Error";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) case COMP_CONTEXT_STATE_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) return "Context State Error";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) case COMP_NO_PING_RESPONSE_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) return "No Ping Response Error";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) case COMP_EVENT_RING_FULL_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) return "Event Ring Full Error";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) case COMP_INCOMPATIBLE_DEVICE_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) return "Incompatible Device Error";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) case COMP_MISSED_SERVICE_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) return "Missed Service Error";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) case COMP_COMMAND_RING_STOPPED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) return "Command Ring Stopped";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) case COMP_COMMAND_ABORTED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) return "Command Aborted";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) case COMP_STOPPED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) return "Stopped";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) case COMP_STOPPED_LENGTH_INVALID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) return "Stopped - Length Invalid";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) case COMP_STOPPED_SHORT_PACKET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) return "Stopped - Short Packet";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) case COMP_MAX_EXIT_LATENCY_TOO_LARGE_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) return "Max Exit Latency Too Large Error";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) case COMP_ISOCH_BUFFER_OVERRUN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) return "Isoch Buffer Overrun";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) case COMP_EVENT_LOST_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) return "Event Lost Error";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) case COMP_UNDEFINED_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) return "Undefined Error";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) case COMP_INVALID_STREAM_ID_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) return "Invalid Stream ID Error";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) case COMP_SECONDARY_BANDWIDTH_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) return "Secondary Bandwidth Error";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) case COMP_SPLIT_TRANSACTION_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) return "Split Transaction Error";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) return "Unknown!!";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) struct xhci_link_trb {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) /* 64-bit segment pointer*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) __le64 segment_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) __le32 intr_target;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) __le32 control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) /* control bitfields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) #define LINK_TOGGLE (0x1<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) /* Command completion event TRB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) struct xhci_event_cmd {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) /* Pointer to command TRB, or the value passed by the event data trb */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) __le64 cmd_trb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) __le32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) __le32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) /* flags bitmasks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) /* Address device - disable SetAddress */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) #define TRB_BSR (1<<9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) /* Configure Endpoint - Deconfigure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) #define TRB_DC (1<<9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) /* Stop Ring - Transfer State Preserve */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) #define TRB_TSP (1<<9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) enum xhci_ep_reset_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) EP_HARD_RESET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) EP_SOFT_RESET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) /* Force Event */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) #define TRB_TO_VF_INTR_TARGET(p) (((p) & (0x3ff << 22)) >> 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) #define TRB_TO_VF_ID(p) (((p) & (0xff << 16)) >> 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) /* Set Latency Tolerance Value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) #define TRB_TO_BELT(p) (((p) & (0xfff << 16)) >> 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) /* Get Port Bandwidth */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) #define TRB_TO_DEV_SPEED(p) (((p) & (0xf << 16)) >> 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) /* Force Header */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) #define TRB_TO_PACKET_TYPE(p) ((p) & 0x1f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) #define TRB_TO_ROOTHUB_PORT(p) (((p) & (0xff << 24)) >> 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) enum xhci_setup_dev {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) SETUP_CONTEXT_ONLY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) SETUP_CONTEXT_ADDRESS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) /* bits 16:23 are the virtual function ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) /* bits 24:31 are the slot ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) #define TRB_TO_SLOT_ID(p) (((p) & (0xff<<24)) >> 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) #define SLOT_ID_FOR_TRB(p) (((p) & 0xff) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) /* Stop Endpoint TRB - ep_index to endpoint ID for this TRB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) #define TRB_TO_EP_INDEX(p) ((((p) & (0x1f << 16)) >> 16) - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) #define EP_ID_FOR_TRB(p) ((((p) + 1) & 0x1f) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) #define SUSPEND_PORT_FOR_TRB(p) (((p) & 1) << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) #define TRB_TO_SUSPEND_PORT(p) (((p) & (1 << 23)) >> 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) #define LAST_EP_INDEX 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) /* Set TR Dequeue Pointer command TRB fields, 6.4.3.9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) #define TRB_TO_STREAM_ID(p) ((((p) & (0xffff << 16)) >> 16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) #define STREAM_ID_FOR_TRB(p) ((((p)) & 0xffff) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) #define SCT_FOR_TRB(p) (((p) << 1) & 0x7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) /* Link TRB specific fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) #define TRB_TC (1<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) /* Port Status Change Event TRB fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) /* Port ID - bits 31:24 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) #define GET_PORT_ID(p) (((p) & (0xff << 24)) >> 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) #define EVENT_DATA (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) /* Normal TRB fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) /* transfer_len bitmasks - bits 0:16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) #define TRB_LEN(p) ((p) & 0x1ffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) /* TD Size, packets remaining in this TD, bits 21:17 (5 bits, so max 31) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) #define TRB_TD_SIZE(p) (min((p), (u32)31) << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) #define GET_TD_SIZE(p) (((p) & 0x3e0000) >> 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) /* xhci 1.1 uses the TD_SIZE field for TBC if Extended TBC is enabled (ETE) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) #define TRB_TD_SIZE_TBC(p) (min((p), (u32)31) << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) /* Interrupter Target - which MSI-X vector to target the completion event at */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) #define TRB_INTR_TARGET(p) (((p) & 0x3ff) << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) #define GET_INTR_TARGET(p) (((p) >> 22) & 0x3ff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) /* Total burst count field, Rsvdz on xhci 1.1 with Extended TBC enabled (ETE) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) #define TRB_TBC(p) (((p) & 0x3) << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) #define TRB_TLBPC(p) (((p) & 0xf) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) /* Cycle bit - indicates TRB ownership by HC or HCD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) #define TRB_CYCLE (1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) * Force next event data TRB to be evaluated before task switch.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) * Used to pass OS data back after a TD completes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) #define TRB_ENT (1<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) /* Interrupt on short packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) #define TRB_ISP (1<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) /* Set PCIe no snoop attribute */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) #define TRB_NO_SNOOP (1<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) /* Chain multiple TRBs into a TD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) #define TRB_CHAIN (1<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) /* Interrupt on completion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) #define TRB_IOC (1<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) /* The buffer pointer contains immediate data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) #define TRB_IDT (1<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) /* TDs smaller than this might use IDT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) #define TRB_IDT_MAX_SIZE 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) /* Block Event Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) #define TRB_BEI (1<<9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) /* Control transfer TRB specific fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) #define TRB_DIR_IN (1<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) #define TRB_TX_TYPE(p) ((p) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) #define TRB_DATA_OUT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) #define TRB_DATA_IN 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) /* Isochronous TRB specific fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) #define TRB_SIA (1<<31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) #define TRB_FRAME_ID(p) (((p) & 0x7ff) << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) struct xhci_generic_trb {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) __le32 field[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) union xhci_trb {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) struct xhci_link_trb link;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) struct xhci_transfer_event trans_event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) struct xhci_event_cmd event_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) struct xhci_generic_trb generic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) /* TRB bit mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) #define TRB_TYPE_BITMASK (0xfc00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) #define TRB_TYPE(p) ((p) << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) #define TRB_FIELD_TO_TYPE(p) (((p) & TRB_TYPE_BITMASK) >> 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) /* TRB type IDs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) /* bulk, interrupt, isoc scatter/gather, and control data stage */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) #define TRB_NORMAL 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) /* setup stage for control transfers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) #define TRB_SETUP 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) /* data stage for control transfers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) #define TRB_DATA 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) /* status stage for control transfers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) #define TRB_STATUS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) /* isoc transfers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) #define TRB_ISOC 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) /* TRB for linking ring segments */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) #define TRB_LINK 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) #define TRB_EVENT_DATA 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) /* Transfer Ring No-op (not for the command ring) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) #define TRB_TR_NOOP 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) /* Command TRBs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) /* Enable Slot Command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) #define TRB_ENABLE_SLOT 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) /* Disable Slot Command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) #define TRB_DISABLE_SLOT 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) /* Address Device Command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) #define TRB_ADDR_DEV 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) /* Configure Endpoint Command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) #define TRB_CONFIG_EP 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) /* Evaluate Context Command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) #define TRB_EVAL_CONTEXT 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) /* Reset Endpoint Command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) #define TRB_RESET_EP 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) /* Stop Transfer Ring Command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) #define TRB_STOP_RING 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) /* Set Transfer Ring Dequeue Pointer Command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) #define TRB_SET_DEQ 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) /* Reset Device Command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) #define TRB_RESET_DEV 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) /* Force Event Command (opt) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) #define TRB_FORCE_EVENT 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) /* Negotiate Bandwidth Command (opt) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) #define TRB_NEG_BANDWIDTH 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) /* Set Latency Tolerance Value Command (opt) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) #define TRB_SET_LT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) /* Get port bandwidth Command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) #define TRB_GET_BW 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) /* Force Header Command - generate a transaction or link management packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) #define TRB_FORCE_HEADER 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) /* No-op Command - not for transfer rings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) #define TRB_CMD_NOOP 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) /* TRB IDs 24-31 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) /* Event TRBS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) /* Transfer Event */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) #define TRB_TRANSFER 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) /* Command Completion Event */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) #define TRB_COMPLETION 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) /* Port Status Change Event */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) #define TRB_PORT_STATUS 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) /* Bandwidth Request Event (opt) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) #define TRB_BANDWIDTH_EVENT 35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) /* Doorbell Event (opt) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) #define TRB_DOORBELL 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) /* Host Controller Event */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) #define TRB_HC_EVENT 37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) /* Device Notification Event - device sent function wake notification */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) #define TRB_DEV_NOTE 38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) /* MFINDEX Wrap Event - microframe counter wrapped */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) #define TRB_MFINDEX_WRAP 39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) /* TRB IDs 40-47 reserved, 48-63 is vendor-defined */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) #define TRB_VENDOR_DEFINED_LOW 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) /* Nec vendor-specific command completion event. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) #define TRB_NEC_CMD_COMP 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) /* Get NEC firmware revision. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) #define TRB_NEC_GET_FW 49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) static inline const char *xhci_trb_type_string(u8 type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) case TRB_NORMAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) return "Normal";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) case TRB_SETUP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) return "Setup Stage";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) case TRB_DATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) return "Data Stage";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) case TRB_STATUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) return "Status Stage";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) case TRB_ISOC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) return "Isoch";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) case TRB_LINK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) return "Link";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) case TRB_EVENT_DATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) return "Event Data";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) case TRB_TR_NOOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) return "No-Op";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) case TRB_ENABLE_SLOT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) return "Enable Slot Command";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) case TRB_DISABLE_SLOT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) return "Disable Slot Command";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) case TRB_ADDR_DEV:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) return "Address Device Command";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) case TRB_CONFIG_EP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) return "Configure Endpoint Command";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) case TRB_EVAL_CONTEXT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) return "Evaluate Context Command";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) case TRB_RESET_EP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) return "Reset Endpoint Command";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) case TRB_STOP_RING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) return "Stop Ring Command";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) case TRB_SET_DEQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) return "Set TR Dequeue Pointer Command";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) case TRB_RESET_DEV:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) return "Reset Device Command";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) case TRB_FORCE_EVENT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) return "Force Event Command";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) case TRB_NEG_BANDWIDTH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) return "Negotiate Bandwidth Command";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) case TRB_SET_LT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) return "Set Latency Tolerance Value Command";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) case TRB_GET_BW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) return "Get Port Bandwidth Command";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) case TRB_FORCE_HEADER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) return "Force Header Command";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) case TRB_CMD_NOOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) return "No-Op Command";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) case TRB_TRANSFER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) return "Transfer Event";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) case TRB_COMPLETION:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) return "Command Completion Event";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) case TRB_PORT_STATUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) return "Port Status Change Event";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) case TRB_BANDWIDTH_EVENT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) return "Bandwidth Request Event";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) case TRB_DOORBELL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) return "Doorbell Event";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) case TRB_HC_EVENT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) return "Host Controller Event";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) case TRB_DEV_NOTE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) return "Device Notification Event";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) case TRB_MFINDEX_WRAP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) return "MFINDEX Wrap Event";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) case TRB_NEC_CMD_COMP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) return "NEC Command Completion Event";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) case TRB_NEC_GET_FW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) return "NET Get Firmware Revision Command";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) return "UNKNOWN";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) #define TRB_TYPE_LINK(x) (((x) & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) /* Above, but for __le32 types -- can avoid work by swapping constants: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) #define TRB_TYPE_LINK_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) cpu_to_le32(TRB_TYPE(TRB_LINK)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) #define TRB_TYPE_NOOP_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) cpu_to_le32(TRB_TYPE(TRB_TR_NOOP)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) #define NEC_FW_MINOR(p) (((p) >> 0) & 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) #define NEC_FW_MAJOR(p) (((p) >> 8) & 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) * TRBS_PER_SEGMENT must be a multiple of 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) * since the command ring is 64-byte aligned.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) * It must also be greater than 16.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) #define TRBS_PER_SEGMENT 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) /* Allow two commands + a link TRB, along with any reserved command TRBs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) #define MAX_RSVD_CMD_TRBS (TRBS_PER_SEGMENT - 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) #define TRB_SEGMENT_SIZE (TRBS_PER_SEGMENT*16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) #define TRB_SEGMENT_SHIFT (ilog2(TRB_SEGMENT_SIZE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) /* TRB buffer pointers can't cross 64KB boundaries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) #define TRB_MAX_BUFF_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) #define TRB_MAX_BUFF_SIZE (1 << TRB_MAX_BUFF_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) /* How much data is left before the 64KB boundary? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) #define TRB_BUFF_LEN_UP_TO_BOUNDARY(addr) (TRB_MAX_BUFF_SIZE - \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) (addr & (TRB_MAX_BUFF_SIZE - 1)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) #define MAX_SOFT_RETRY 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) struct xhci_segment {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) union xhci_trb *trbs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) /* private to HCD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) struct xhci_segment *next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) dma_addr_t dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) /* Max packet sized bounce buffer for td-fragmant alignment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) dma_addr_t bounce_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) void *bounce_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) unsigned int bounce_offs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) unsigned int bounce_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) ANDROID_KABI_RESERVE(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) enum xhci_cancelled_td_status {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) TD_DIRTY = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) TD_HALTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) TD_CLEARING_CACHE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) TD_CLEARED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) struct xhci_td {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) struct list_head td_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) struct list_head cancelled_td_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) enum xhci_cancelled_td_status cancel_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) struct urb *urb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) struct xhci_segment *start_seg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) union xhci_trb *first_trb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) union xhci_trb *last_trb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) struct xhci_segment *last_trb_seg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) struct xhci_segment *bounce_seg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) /* actual_length of the URB has already been set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) bool urb_length_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) unsigned int num_trbs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) /* xHCI command default timeout value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) #define XHCI_CMD_DEFAULT_TIMEOUT (5 * HZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) /* command descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) struct xhci_cd {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) struct xhci_command *command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) union xhci_trb *cmd_trb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) enum xhci_ring_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) TYPE_CTRL = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) TYPE_ISOC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) TYPE_BULK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) TYPE_INTR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) TYPE_STREAM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) TYPE_COMMAND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) TYPE_EVENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) static inline const char *xhci_ring_type_string(enum xhci_ring_type type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) case TYPE_CTRL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) return "CTRL";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) case TYPE_ISOC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) return "ISOC";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) case TYPE_BULK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) return "BULK";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) case TYPE_INTR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) return "INTR";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) case TYPE_STREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) return "STREAM";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) case TYPE_COMMAND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) return "CMD";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) case TYPE_EVENT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) return "EVENT";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) return "UNKNOWN";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) struct xhci_ring {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) struct xhci_segment *first_seg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) struct xhci_segment *last_seg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) union xhci_trb *enqueue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) struct xhci_segment *enq_seg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) union xhci_trb *dequeue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) struct xhci_segment *deq_seg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) struct list_head td_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) * Write the cycle state into the TRB cycle field to give ownership of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) * the TRB to the host controller (if we are the producer), or to check
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) * if we own the TRB (if we are the consumer). See section 4.9.1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) u32 cycle_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) unsigned int err_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) unsigned int stream_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) unsigned int num_segs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) unsigned int num_trbs_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) unsigned int num_trbs_free_temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) unsigned int bounce_buf_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) enum xhci_ring_type type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) bool last_td_was_short;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) struct radix_tree_root *trb_address_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) ANDROID_KABI_RESERVE(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) ANDROID_KABI_RESERVE(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) struct xhci_erst_entry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) /* 64-bit event ring segment address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) __le64 seg_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) __le32 seg_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) /* Set to zero */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) __le32 rsvd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) struct xhci_erst {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) struct xhci_erst_entry *entries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) unsigned int num_entries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) /* xhci->event_ring keeps track of segment dma addresses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) dma_addr_t erst_dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) /* Num entries the ERST can contain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) unsigned int erst_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) ANDROID_KABI_RESERVE(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) struct xhci_scratchpad {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) u64 *sp_array;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) dma_addr_t sp_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) void **sp_buffers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) struct urb_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) int num_tds;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) int num_tds_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) struct xhci_td td[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) * Each segment table entry is 4*32bits long. 1K seems like an ok size:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) * (1K bytes * 8bytes/bit) / (4*32 bits) = 64 segment entries in the table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) * meaning 64 ring segments.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) * Initial allocated size of the ERST, in number of entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) #define ERST_NUM_SEGS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) /* Initial allocated size of the ERST, in number of entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) #define ERST_SIZE 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) /* Initial number of event segment rings allocated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) #define ERST_ENTRIES 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) /* Poll every 60 seconds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) #define POLL_TIMEOUT 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) /* Stop endpoint command timeout (secs) for URB cancellation watchdog timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) #define XHCI_STOP_EP_CMD_TIMEOUT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) /* XXX: Make these module parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) struct s3_save {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) u32 command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) u32 dev_nt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) u64 dcbaa_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) u32 config_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) u32 irq_pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) u32 irq_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) u32 erst_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) u64 erst_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) u64 erst_dequeue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) /* Use for lpm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) struct dev_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) u32 dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) struct list_head list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) struct xhci_bus_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) unsigned long bus_suspended;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) unsigned long next_statechange;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) /* Port suspend arrays are indexed by the portnum of the fake roothub */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) /* ports suspend status arrays - max 31 ports for USB2, 15 for USB3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) u32 port_c_suspend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) u32 suspended_ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) u32 port_remote_wakeup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) unsigned long resume_done[USB_MAXCHILDREN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) /* which ports have started to resume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) unsigned long resuming_ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) /* Which ports are waiting on RExit to U0 transition. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) unsigned long rexit_ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) struct completion rexit_done[USB_MAXCHILDREN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) struct completion u3exit_done[USB_MAXCHILDREN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) * It can take up to 20 ms to transition from RExit to U0 on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) * Intel Lynx Point LP xHCI host.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) #define XHCI_MAX_REXIT_TIMEOUT_MS 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) struct xhci_port_cap {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) u32 *psi; /* array of protocol speed ID entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) u8 psi_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) u8 psi_uid_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) u8 maj_rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) u8 min_rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) struct xhci_port {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) __le32 __iomem *addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) int hw_portnum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) int hcd_portnum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) struct xhci_hub *rhub;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) struct xhci_port_cap *port_cap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) struct xhci_hub {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) struct xhci_port **ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) unsigned int num_ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) struct usb_hcd *hcd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) /* keep track of bus suspend info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) struct xhci_bus_state bus_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) /* supported prococol extended capabiliy values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) u8 maj_rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) u8 min_rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) /* There is one xhci_hcd structure per controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) struct xhci_hcd {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) struct usb_hcd *main_hcd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) struct usb_hcd *shared_hcd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) /* glue to PCI and HCD framework */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) struct xhci_cap_regs __iomem *cap_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) struct xhci_op_regs __iomem *op_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) struct xhci_run_regs __iomem *run_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) struct xhci_doorbell_array __iomem *dba;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) /* Our HCD's current interrupter register set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) struct xhci_intr_reg __iomem *ir_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) /* Cached register copies of read-only HC data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) __u32 hcs_params1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) __u32 hcs_params2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) __u32 hcs_params3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) __u32 hcc_params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) __u32 hcc_params2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) /* packed release number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) u8 sbrn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) u16 hci_version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) u8 max_slots;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) u8 max_interrupters;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) u8 max_ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) u8 isoc_threshold;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) /* imod_interval in ns (I * 250ns) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) u32 imod_interval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) int event_ring_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) /* 4KB min, 128MB max */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) int page_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) /* Valid values are 12 to 20, inclusive */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) int page_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) /* msi-x vectors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) int msix_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) /* optional clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) struct clk *reg_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) /* optional reset controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) struct reset_control *reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) /* data structures */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) struct xhci_device_context_array *dcbaa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) struct xhci_ring *cmd_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) unsigned int cmd_ring_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) #define CMD_RING_STATE_RUNNING (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) #define CMD_RING_STATE_ABORTED (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) #define CMD_RING_STATE_STOPPED (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) struct list_head cmd_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) unsigned int cmd_ring_reserved_trbs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) struct delayed_work cmd_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) struct completion cmd_ring_stop_completion;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) struct xhci_command *current_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) struct xhci_ring *event_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) struct xhci_erst erst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) /* Scratchpad */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) struct xhci_scratchpad *scratchpad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) /* Store LPM test failed devices' information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) struct list_head lpm_failed_devs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) /* slot enabling and address device helpers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) /* these are not thread safe so use mutex */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) struct mutex mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) /* For USB 3.0 LPM enable/disable. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) struct xhci_command *lpm_command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) /* Internal mirror of the HW's dcbaa */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) struct xhci_virt_device *devs[MAX_HC_SLOTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) /* For keeping track of bandwidth domains per roothub. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) struct xhci_root_port_bw_info *rh_bw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) /* DMA pools */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) struct dma_pool *device_pool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) struct dma_pool *segment_pool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) struct dma_pool *small_streams_pool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) struct dma_pool *medium_streams_pool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) /* Host controller watchdog timer structures */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) unsigned int xhc_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) u32 command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) struct s3_save s3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) /* Host controller is dying - not responding to commands. "I'm not dead yet!"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) * xHC interrupts have been disabled and a watchdog timer will (or has already)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) * halt the xHCI host, and complete all URBs with an -ESHUTDOWN code. Any code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) * that sees this status (other than the timer that set it) should stop touching
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) * hardware immediately. Interrupt handlers should return immediately when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) * they see this status (any time they drop and re-acquire xhci->lock).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) * xhci_urb_dequeue() should call usb_hcd_check_unlink_urb() and return without
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) * putting the TD on the canceled list, etc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) * There are no reports of xHCI host controllers that display this issue.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) #define XHCI_STATE_DYING (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) #define XHCI_STATE_HALTED (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) #define XHCI_STATE_REMOVING (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) unsigned long long quirks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) #define XHCI_LINK_TRB_QUIRK BIT_ULL(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) #define XHCI_RESET_EP_QUIRK BIT_ULL(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) #define XHCI_NEC_HOST BIT_ULL(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) #define XHCI_AMD_PLL_FIX BIT_ULL(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) #define XHCI_SPURIOUS_SUCCESS BIT_ULL(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) * Certain Intel host controllers have a limit to the number of endpoint
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) * contexts they can handle. Ideally, they would signal that they can't handle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) * anymore endpoint contexts by returning a Resource Error for the Configure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) * Endpoint command, but they don't. Instead they expect software to keep track
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) * of the number of active endpoints for them, across configure endpoint
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) * commands, reset device commands, disable slot commands, and address device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) * commands.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) #define XHCI_EP_LIMIT_QUIRK BIT_ULL(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) #define XHCI_BROKEN_MSI BIT_ULL(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) #define XHCI_RESET_ON_RESUME BIT_ULL(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) #define XHCI_SW_BW_CHECKING BIT_ULL(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) #define XHCI_AMD_0x96_HOST BIT_ULL(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) #define XHCI_TRUST_TX_LENGTH BIT_ULL(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) #define XHCI_LPM_SUPPORT BIT_ULL(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) #define XHCI_INTEL_HOST BIT_ULL(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) #define XHCI_SPURIOUS_REBOOT BIT_ULL(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) #define XHCI_COMP_MODE_QUIRK BIT_ULL(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) #define XHCI_AVOID_BEI BIT_ULL(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) #define XHCI_PLAT BIT_ULL(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) #define XHCI_SLOW_SUSPEND BIT_ULL(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) #define XHCI_SPURIOUS_WAKEUP BIT_ULL(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) /* For controllers with a broken beyond repair streams implementation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) #define XHCI_BROKEN_STREAMS BIT_ULL(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) #define XHCI_PME_STUCK_QUIRK BIT_ULL(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) #define XHCI_MTK_HOST BIT_ULL(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) #define XHCI_SSIC_PORT_UNUSED BIT_ULL(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) #define XHCI_NO_64BIT_SUPPORT BIT_ULL(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) #define XHCI_MISSING_CAS BIT_ULL(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) /* For controller with a broken Port Disable implementation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) #define XHCI_BROKEN_PORT_PED BIT_ULL(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) #define XHCI_LIMIT_ENDPOINT_INTERVAL_7 BIT_ULL(26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) #define XHCI_U2_DISABLE_WAKE BIT_ULL(27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) #define XHCI_ASMEDIA_MODIFY_FLOWCONTROL BIT_ULL(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) #define XHCI_HW_LPM_DISABLE BIT_ULL(29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) #define XHCI_SUSPEND_DELAY BIT_ULL(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) #define XHCI_INTEL_USB_ROLE_SW BIT_ULL(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) #define XHCI_ZERO_64B_REGS BIT_ULL(32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) #define XHCI_DEFAULT_PM_RUNTIME_ALLOW BIT_ULL(33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) #define XHCI_RESET_PLL_ON_DISCONNECT BIT_ULL(34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) #define XHCI_SNPS_BROKEN_SUSPEND BIT_ULL(35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) #define XHCI_RENESAS_FW_QUIRK BIT_ULL(36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) #define XHCI_SKIP_PHY_INIT BIT_ULL(37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) #define XHCI_DISABLE_SPARSE BIT_ULL(38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) #define XHCI_SG_TRB_CACHE_SIZE_QUIRK BIT_ULL(39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) #define XHCI_NO_SOFT_RETRY BIT_ULL(40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) #define XHCI_EP_CTX_BROKEN_DCS BIT_ULL(42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) #define XHCI_U2_BROKEN_SUSPEND BIT_ULL(43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) unsigned int num_active_eps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) unsigned int limit_active_eps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) struct xhci_port *hw_ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) struct xhci_hub usb2_rhub;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) struct xhci_hub usb3_rhub;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) /* support xHCI 1.0 spec USB2 hardware LPM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) unsigned hw_lpm_support:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) /* Broken Suspend flag for SNPS Suspend resume issue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) unsigned broken_suspend:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) /* cached usb2 extened protocol capabilites */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) u32 *ext_caps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) unsigned int num_ext_caps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) /* cached extended protocol port capabilities */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) struct xhci_port_cap *port_caps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) unsigned int num_port_caps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) /* Compliance Mode Recovery Data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) struct timer_list comp_mode_recovery_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) u32 port_status_u0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) u16 test_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) /* Compliance Mode Timer Triggered every 2 seconds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) #define COMP_MODE_RCVRY_MSECS 2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) struct dentry *debugfs_root;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) struct dentry *debugfs_slots;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) struct list_head regset_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) void *dbc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) /* Used for bug 194461020 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) ANDROID_KABI_USE(1, struct xhci_vendor_ops *vendor_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) ANDROID_KABI_RESERVE(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) ANDROID_KABI_RESERVE(3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) ANDROID_KABI_RESERVE(4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) /* platform-specific data -- must come last */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) unsigned long priv[] __aligned(sizeof(s64));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) /* Platform specific overrides to generic XHCI hc_driver ops */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) struct xhci_driver_overrides {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) size_t extra_priv_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) int (*reset)(struct usb_hcd *hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) int (*start)(struct usb_hcd *hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) int (*add_endpoint)(struct usb_hcd *hcd, struct usb_device *udev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) struct usb_host_endpoint *ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) int (*drop_endpoint)(struct usb_hcd *hcd, struct usb_device *udev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) struct usb_host_endpoint *ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) int (*check_bandwidth)(struct usb_hcd *, struct usb_device *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) void (*reset_bandwidth)(struct usb_hcd *, struct usb_device *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) int (*address_device)(struct usb_hcd *hcd, struct usb_device *udev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) int (*bus_suspend)(struct usb_hcd *hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) int (*bus_resume)(struct usb_hcd *hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) #define XHCI_CFC_DELAY 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) /* convert between an HCD pointer and the corresponding EHCI_HCD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) static inline struct xhci_hcd *hcd_to_xhci(struct usb_hcd *hcd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) struct usb_hcd *primary_hcd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) if (usb_hcd_is_primary_hcd(hcd))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) primary_hcd = hcd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) primary_hcd = hcd->primary_hcd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) return (struct xhci_hcd *) (primary_hcd->hcd_priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) static inline struct usb_hcd *xhci_to_hcd(struct xhci_hcd *xhci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) return xhci->main_hcd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) #define xhci_dbg(xhci, fmt, args...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) dev_dbg(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) #define xhci_err(xhci, fmt, args...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) dev_err(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) #define xhci_warn(xhci, fmt, args...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) dev_warn(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) #define xhci_warn_ratelimited(xhci, fmt, args...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) dev_warn_ratelimited(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) #define xhci_info(xhci, fmt, args...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) dev_info(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) * Registers should always be accessed with double word or quad word accesses.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) * Some xHCI implementations may support 64-bit address pointers. Registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) * with 64-bit address pointers should be written to with dword accesses by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) * writing the low dword first (ptr[0]), then the high dword (ptr[1]) second.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) * xHCI implementations that do not support 64-bit address pointers will ignore
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) * the high dword, and write order is irrelevant.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) static inline u64 xhci_read_64(const struct xhci_hcd *xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) __le64 __iomem *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) return lo_hi_readq(regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) static inline void xhci_write_64(struct xhci_hcd *xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) const u64 val, __le64 __iomem *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) lo_hi_writeq(val, regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) static inline int xhci_link_trb_quirk(struct xhci_hcd *xhci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) return xhci->quirks & XHCI_LINK_TRB_QUIRK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) /* xHCI debugging */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) char *xhci_get_slot_state(struct xhci_hcd *xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) struct xhci_container_ctx *ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) void xhci_dbg_trace(struct xhci_hcd *xhci, void (*trace)(struct va_format *),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) const char *fmt, ...);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) /* xHCI memory management */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) void xhci_mem_cleanup(struct xhci_hcd *xhci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) void xhci_free_virt_device(struct xhci_hcd *xhci, int slot_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) int xhci_alloc_virt_device(struct xhci_hcd *xhci, int slot_id, struct usb_device *udev, gfp_t flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) int xhci_setup_addressable_virt_dev(struct xhci_hcd *xhci, struct usb_device *udev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) void xhci_copy_ep0_dequeue_into_input_ctx(struct xhci_hcd *xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) struct usb_device *udev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) unsigned int xhci_get_endpoint_address(unsigned int ep_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) unsigned int xhci_last_valid_endpoint(u32 added_ctxs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) void xhci_endpoint_zero(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev, struct usb_host_endpoint *ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) void xhci_update_tt_active_eps(struct xhci_hcd *xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) struct xhci_virt_device *virt_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) int old_active_eps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) void xhci_clear_endpoint_bw_info(struct xhci_bw_info *bw_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) void xhci_update_bw_info(struct xhci_hcd *xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) struct xhci_container_ctx *in_ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) struct xhci_input_control_ctx *ctrl_ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) struct xhci_virt_device *virt_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) void xhci_endpoint_copy(struct xhci_hcd *xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) struct xhci_container_ctx *in_ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) struct xhci_container_ctx *out_ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) unsigned int ep_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) void xhci_slot_copy(struct xhci_hcd *xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) struct xhci_container_ctx *in_ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) struct xhci_container_ctx *out_ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) int xhci_endpoint_init(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) struct usb_device *udev, struct usb_host_endpoint *ep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) gfp_t mem_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) struct xhci_ring *xhci_ring_alloc(struct xhci_hcd *xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) unsigned int num_segs, unsigned int cycle_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) enum xhci_ring_type type, unsigned int max_packet, gfp_t flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) void xhci_ring_free(struct xhci_hcd *xhci, struct xhci_ring *ring);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) int xhci_ring_expansion(struct xhci_hcd *xhci, struct xhci_ring *ring,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) unsigned int num_trbs, gfp_t flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) int xhci_alloc_erst(struct xhci_hcd *xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) struct xhci_ring *evt_ring,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) struct xhci_erst *erst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) gfp_t flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) void xhci_initialize_ring_info(struct xhci_ring *ring,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) unsigned int cycle_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) void xhci_free_erst(struct xhci_hcd *xhci, struct xhci_erst *erst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) void xhci_free_endpoint_ring(struct xhci_hcd *xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) struct xhci_virt_device *virt_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) unsigned int ep_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) struct xhci_stream_info *xhci_alloc_stream_info(struct xhci_hcd *xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) unsigned int num_stream_ctxs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) unsigned int num_streams,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) unsigned int max_packet, gfp_t flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) void xhci_free_stream_info(struct xhci_hcd *xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) struct xhci_stream_info *stream_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) void xhci_setup_streams_ep_input_ctx(struct xhci_hcd *xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) struct xhci_ep_ctx *ep_ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) struct xhci_stream_info *stream_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) void xhci_setup_no_streams_ep_input_ctx(struct xhci_ep_ctx *ep_ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) struct xhci_virt_ep *ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) void xhci_free_device_endpoint_resources(struct xhci_hcd *xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) struct xhci_virt_device *virt_dev, bool drop_control_ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) struct xhci_ring *xhci_dma_to_transfer_ring(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) struct xhci_virt_ep *ep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) u64 address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) struct xhci_command *xhci_alloc_command(struct xhci_hcd *xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) bool allocate_completion, gfp_t mem_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) struct xhci_command *xhci_alloc_command_with_ctx(struct xhci_hcd *xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) bool allocate_completion, gfp_t mem_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) void xhci_urb_free_priv(struct urb_priv *urb_priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) void xhci_free_command(struct xhci_hcd *xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) struct xhci_command *command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) struct xhci_container_ctx *xhci_alloc_container_ctx(struct xhci_hcd *xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) int type, gfp_t flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) void xhci_free_container_ctx(struct xhci_hcd *xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) struct xhci_container_ctx *ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) /* xHCI host controller glue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) typedef void (*xhci_get_quirks_t)(struct device *, struct xhci_hcd *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) int xhci_handshake(void __iomem *ptr, u32 mask, u32 done, u64 timeout_us);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) void xhci_quiesce(struct xhci_hcd *xhci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) int xhci_halt(struct xhci_hcd *xhci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) int xhci_start(struct xhci_hcd *xhci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) int xhci_reset(struct xhci_hcd *xhci, u64 timeout_us);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) int xhci_run(struct usb_hcd *hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) void xhci_shutdown(struct usb_hcd *hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) void xhci_init_driver(struct hc_driver *drv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) const struct xhci_driver_overrides *over);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) struct usb_host_endpoint *ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) struct usb_host_endpoint *ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) int xhci_address_device(struct usb_hcd *hcd, struct usb_device *udev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) int xhci_disable_slot(struct xhci_hcd *xhci, u32 slot_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) int xhci_ext_cap_init(struct xhci_hcd *xhci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) int xhci_suspend(struct xhci_hcd *xhci, bool do_wakeup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) int xhci_resume(struct xhci_hcd *xhci, bool hibernated);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) irqreturn_t xhci_irq(struct usb_hcd *hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) irqreturn_t xhci_msi_irq(int irq, void *hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) int xhci_alloc_tt_info(struct xhci_hcd *xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) struct xhci_virt_device *virt_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) struct usb_device *hdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) struct usb_tt *tt, gfp_t mem_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) /* xHCI ring, segment, TRB, and TD functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg, union xhci_trb *trb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) struct xhci_segment *trb_in_td(struct xhci_hcd *xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) struct xhci_segment *start_seg, union xhci_trb *start_trb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) union xhci_trb *end_trb, dma_addr_t suspect_dma, bool debug);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) void xhci_ring_cmd_db(struct xhci_hcd *xhci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) int xhci_queue_slot_control(struct xhci_hcd *xhci, struct xhci_command *cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) u32 trb_type, u32 slot_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) int xhci_queue_address_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) dma_addr_t in_ctx_ptr, u32 slot_id, enum xhci_setup_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) int xhci_queue_vendor_command(struct xhci_hcd *xhci, struct xhci_command *cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) u32 field1, u32 field2, u32 field3, u32 field4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, struct xhci_command *cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) int slot_id, unsigned int ep_index, int suspend);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) int slot_id, unsigned int ep_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) int slot_id, unsigned int ep_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) int slot_id, unsigned int ep_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) struct urb *urb, int slot_id, unsigned int ep_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) int xhci_queue_configure_endpoint(struct xhci_hcd *xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) struct xhci_command *cmd, dma_addr_t in_ctx_ptr, u32 slot_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) bool command_must_succeed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) int xhci_queue_evaluate_context(struct xhci_hcd *xhci, struct xhci_command *cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) dma_addr_t in_ctx_ptr, u32 slot_id, bool command_must_succeed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) int xhci_queue_reset_ep(struct xhci_hcd *xhci, struct xhci_command *cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) int slot_id, unsigned int ep_index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) enum xhci_ep_reset_type reset_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) int xhci_queue_reset_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) u32 slot_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) void xhci_cleanup_stalled_ring(struct xhci_hcd *xhci, unsigned int slot_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) unsigned int ep_index, unsigned int stream_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) struct xhci_td *td);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) void xhci_stop_endpoint_command_watchdog(struct timer_list *t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) void xhci_handle_command_timeout(struct work_struct *work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) void xhci_ring_ep_doorbell(struct xhci_hcd *xhci, unsigned int slot_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) unsigned int ep_index, unsigned int stream_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) void xhci_ring_doorbell_for_active_rings(struct xhci_hcd *xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) unsigned int slot_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) unsigned int ep_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) void xhci_cleanup_command_queue(struct xhci_hcd *xhci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) unsigned int count_trbs(u64 addr, u64 len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) /* xHCI roothub code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) void xhci_set_link_state(struct xhci_hcd *xhci, struct xhci_port *port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) u32 link_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) void xhci_test_and_clear_bit(struct xhci_hcd *xhci, struct xhci_port *port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) u32 port_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, u16 wIndex,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) char *buf, u16 wLength);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) int xhci_hub_status_data(struct usb_hcd *hcd, char *buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) int xhci_find_raw_port_number(struct usb_hcd *hcd, int port1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) struct xhci_hub *xhci_get_rhub(struct usb_hcd *hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) void xhci_hc_died(struct xhci_hcd *xhci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) int xhci_bus_suspend(struct usb_hcd *hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) int xhci_bus_resume(struct usb_hcd *hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) unsigned long xhci_get_resuming_ports(struct usb_hcd *hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) #define xhci_bus_suspend NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) #define xhci_bus_resume NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) #define xhci_get_resuming_ports NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) #endif /* CONFIG_PM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) u32 xhci_port_state_to_neutral(u32 state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) int xhci_find_slot_id_by_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) u16 port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) void xhci_ring_device(struct xhci_hcd *xhci, int slot_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) /* xHCI contexts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) struct xhci_input_control_ctx *xhci_get_input_control_ctx(struct xhci_container_ctx *ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx, unsigned int ep_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) unsigned int slot_id, unsigned int ep_index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) unsigned int stream_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) static inline struct xhci_ring *xhci_urb_to_transfer_ring(struct xhci_hcd *xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) struct urb *urb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) return xhci_triad_to_transfer_ring(xhci, urb->dev->slot_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) xhci_get_endpoint_index(&urb->ep->desc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) urb->stream_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) * struct xhci_vendor_ops - function callbacks for vendor specific operations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) * @vendor_init: called for vendor init process
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) * @vendor_cleanup: called for vendor cleanup process
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) * @is_usb_offload_enabled: called to check if usb offload enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) * @queue_irq_work: called to queue vendor specific irq work
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) * @alloc_dcbaa: called when allocating vendor specific dcbaa
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) * @free_dcbaa: called to free vendor specific dcbaa
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) * @alloc_transfer_ring: called when remote transfer ring allocation is required
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) * @free_transfer_ring: called to free vendor specific transfer ring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) * @sync_dev_ctx: called when synchronization for device context is required
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) * @alloc_container_ctx: called when allocating vendor specific container context
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) * @free_container_ctx: called to free vendor specific container context
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) struct xhci_vendor_ops {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) int (*vendor_init)(struct xhci_hcd *xhci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) void (*vendor_cleanup)(struct xhci_hcd *xhci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) bool (*is_usb_offload_enabled)(struct xhci_hcd *xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) struct xhci_virt_device *vdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) unsigned int ep_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) irqreturn_t (*queue_irq_work)(struct xhci_hcd *xhci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) struct xhci_device_context_array *(*alloc_dcbaa)(struct xhci_hcd *xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) gfp_t flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) void (*free_dcbaa)(struct xhci_hcd *xhci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) struct xhci_ring *(*alloc_transfer_ring)(struct xhci_hcd *xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) u32 endpoint_type, enum xhci_ring_type ring_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) unsigned int max_packet, gfp_t mem_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) void (*free_transfer_ring)(struct xhci_hcd *xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) struct xhci_virt_device *virt_dev, unsigned int ep_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) int (*sync_dev_ctx)(struct xhci_hcd *xhci, unsigned int slot_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) bool (*usb_offload_skip_urb)(struct xhci_hcd *xhci, struct urb *urb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) void (*alloc_container_ctx)(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) int type, gfp_t flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) void (*free_container_ctx)(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) struct xhci_vendor_ops *xhci_vendor_get_ops(struct xhci_hcd *xhci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) int xhci_vendor_sync_dev_ctx(struct xhci_hcd *xhci, unsigned int slot_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) bool xhci_vendor_usb_offload_skip_urb(struct xhci_hcd *xhci, struct urb *urb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) void xhci_vendor_free_transfer_ring(struct xhci_hcd *xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) struct xhci_virt_device *virt_dev, unsigned int ep_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) bool xhci_vendor_is_usb_offload_enabled(struct xhci_hcd *xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) struct xhci_virt_device *virt_dev, unsigned int ep_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) * TODO: As per spec Isochronous IDT transmissions are supported. We bypass
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) * them anyways as we where unable to find a device that matches the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) * constraints.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) static inline bool xhci_urb_suitable_for_idt(struct urb *urb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) if (!usb_endpoint_xfer_isoc(&urb->ep->desc) && usb_urb_dir_out(urb) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) usb_endpoint_maxp(&urb->ep->desc) >= TRB_IDT_MAX_SIZE &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) urb->transfer_buffer_length <= TRB_IDT_MAX_SIZE &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) !(urb->transfer_flags & URB_NO_TRANSFER_DMA_MAP) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) !urb->num_sgs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) static inline char *xhci_slot_state_string(u32 state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) switch (state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) case SLOT_STATE_ENABLED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) return "enabled/disabled";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) case SLOT_STATE_DEFAULT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) return "default";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) case SLOT_STATE_ADDRESSED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) return "addressed";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) case SLOT_STATE_CONFIGURED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) return "configured";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) return "reserved";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) static inline const char *xhci_decode_trb(char *str, size_t size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) u32 field0, u32 field1, u32 field2, u32 field3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) int type = TRB_FIELD_TO_TYPE(field3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) case TRB_LINK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) snprintf(str, size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) "LINK %08x%08x intr %d type '%s' flags %c:%c:%c:%c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) field1, field0, GET_INTR_TARGET(field2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) xhci_trb_type_string(type),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) field3 & TRB_IOC ? 'I' : 'i',
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) field3 & TRB_CHAIN ? 'C' : 'c',
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) field3 & TRB_TC ? 'T' : 't',
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) field3 & TRB_CYCLE ? 'C' : 'c');
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) case TRB_TRANSFER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) case TRB_COMPLETION:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) case TRB_PORT_STATUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) case TRB_BANDWIDTH_EVENT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) case TRB_DOORBELL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) case TRB_HC_EVENT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) case TRB_DEV_NOTE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) case TRB_MFINDEX_WRAP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) snprintf(str, size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) "TRB %08x%08x status '%s' len %d slot %d ep %d type '%s' flags %c:%c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) field1, field0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) xhci_trb_comp_code_string(GET_COMP_CODE(field2)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) EVENT_TRB_LEN(field2), TRB_TO_SLOT_ID(field3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) /* Macro decrements 1, maybe it shouldn't?!? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) TRB_TO_EP_INDEX(field3) + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) xhci_trb_type_string(type),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) field3 & EVENT_DATA ? 'E' : 'e',
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) field3 & TRB_CYCLE ? 'C' : 'c');
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) case TRB_SETUP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) snprintf(str, size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) "bRequestType %02x bRequest %02x wValue %02x%02x wIndex %02x%02x wLength %d length %d TD size %d intr %d type '%s' flags %c:%c:%c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) field0 & 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) (field0 & 0xff00) >> 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) (field0 & 0xff000000) >> 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) (field0 & 0xff0000) >> 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) (field1 & 0xff00) >> 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) field1 & 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) (field1 & 0xff000000) >> 16 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) (field1 & 0xff0000) >> 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) TRB_LEN(field2), GET_TD_SIZE(field2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) GET_INTR_TARGET(field2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) xhci_trb_type_string(type),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) field3 & TRB_IDT ? 'I' : 'i',
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) field3 & TRB_IOC ? 'I' : 'i',
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) field3 & TRB_CYCLE ? 'C' : 'c');
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) case TRB_DATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) snprintf(str, size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) "Buffer %08x%08x length %d TD size %d intr %d type '%s' flags %c:%c:%c:%c:%c:%c:%c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) field1, field0, TRB_LEN(field2), GET_TD_SIZE(field2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) GET_INTR_TARGET(field2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) xhci_trb_type_string(type),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) field3 & TRB_IDT ? 'I' : 'i',
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) field3 & TRB_IOC ? 'I' : 'i',
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) field3 & TRB_CHAIN ? 'C' : 'c',
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) field3 & TRB_NO_SNOOP ? 'S' : 's',
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) field3 & TRB_ISP ? 'I' : 'i',
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) field3 & TRB_ENT ? 'E' : 'e',
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) field3 & TRB_CYCLE ? 'C' : 'c');
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) case TRB_STATUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) snprintf(str, size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) "Buffer %08x%08x length %d TD size %d intr %d type '%s' flags %c:%c:%c:%c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) field1, field0, TRB_LEN(field2), GET_TD_SIZE(field2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) GET_INTR_TARGET(field2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) xhci_trb_type_string(type),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) field3 & TRB_IOC ? 'I' : 'i',
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) field3 & TRB_CHAIN ? 'C' : 'c',
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) field3 & TRB_ENT ? 'E' : 'e',
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) field3 & TRB_CYCLE ? 'C' : 'c');
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) case TRB_NORMAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) case TRB_ISOC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) case TRB_EVENT_DATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) case TRB_TR_NOOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) snprintf(str, size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) "Buffer %08x%08x length %d TD size %d intr %d type '%s' flags %c:%c:%c:%c:%c:%c:%c:%c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) field1, field0, TRB_LEN(field2), GET_TD_SIZE(field2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) GET_INTR_TARGET(field2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) xhci_trb_type_string(type),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) field3 & TRB_BEI ? 'B' : 'b',
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) field3 & TRB_IDT ? 'I' : 'i',
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) field3 & TRB_IOC ? 'I' : 'i',
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) field3 & TRB_CHAIN ? 'C' : 'c',
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) field3 & TRB_NO_SNOOP ? 'S' : 's',
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) field3 & TRB_ISP ? 'I' : 'i',
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) field3 & TRB_ENT ? 'E' : 'e',
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) field3 & TRB_CYCLE ? 'C' : 'c');
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) case TRB_CMD_NOOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) case TRB_ENABLE_SLOT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) snprintf(str, size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) "%s: flags %c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) xhci_trb_type_string(type),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) field3 & TRB_CYCLE ? 'C' : 'c');
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) case TRB_DISABLE_SLOT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) case TRB_NEG_BANDWIDTH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) snprintf(str, size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) "%s: slot %d flags %c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) xhci_trb_type_string(type),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) TRB_TO_SLOT_ID(field3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) field3 & TRB_CYCLE ? 'C' : 'c');
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) case TRB_ADDR_DEV:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) snprintf(str, size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) "%s: ctx %08x%08x slot %d flags %c:%c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) xhci_trb_type_string(type),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) field1, field0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) TRB_TO_SLOT_ID(field3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) field3 & TRB_BSR ? 'B' : 'b',
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) field3 & TRB_CYCLE ? 'C' : 'c');
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) case TRB_CONFIG_EP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) snprintf(str, size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) "%s: ctx %08x%08x slot %d flags %c:%c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) xhci_trb_type_string(type),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) field1, field0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) TRB_TO_SLOT_ID(field3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) field3 & TRB_DC ? 'D' : 'd',
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) field3 & TRB_CYCLE ? 'C' : 'c');
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) case TRB_EVAL_CONTEXT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) snprintf(str, size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) "%s: ctx %08x%08x slot %d flags %c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) xhci_trb_type_string(type),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) field1, field0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) TRB_TO_SLOT_ID(field3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) field3 & TRB_CYCLE ? 'C' : 'c');
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) case TRB_RESET_EP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) snprintf(str, size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) "%s: ctx %08x%08x slot %d ep %d flags %c:%c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) xhci_trb_type_string(type),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) field1, field0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) TRB_TO_SLOT_ID(field3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) /* Macro decrements 1, maybe it shouldn't?!? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) TRB_TO_EP_INDEX(field3) + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) field3 & TRB_TSP ? 'T' : 't',
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) field3 & TRB_CYCLE ? 'C' : 'c');
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) case TRB_STOP_RING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) sprintf(str,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) "%s: slot %d sp %d ep %d flags %c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) xhci_trb_type_string(type),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) TRB_TO_SLOT_ID(field3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) TRB_TO_SUSPEND_PORT(field3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) /* Macro decrements 1, maybe it shouldn't?!? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) TRB_TO_EP_INDEX(field3) + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) field3 & TRB_CYCLE ? 'C' : 'c');
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) case TRB_SET_DEQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) snprintf(str, size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) "%s: deq %08x%08x stream %d slot %d ep %d flags %c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) xhci_trb_type_string(type),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) field1, field0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) TRB_TO_STREAM_ID(field2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) TRB_TO_SLOT_ID(field3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) /* Macro decrements 1, maybe it shouldn't?!? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) TRB_TO_EP_INDEX(field3) + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) field3 & TRB_CYCLE ? 'C' : 'c');
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) case TRB_RESET_DEV:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) snprintf(str, size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) "%s: slot %d flags %c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) xhci_trb_type_string(type),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483) TRB_TO_SLOT_ID(field3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) field3 & TRB_CYCLE ? 'C' : 'c');
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) case TRB_FORCE_EVENT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) snprintf(str, size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) "%s: event %08x%08x vf intr %d vf id %d flags %c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) xhci_trb_type_string(type),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490) field1, field0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) TRB_TO_VF_INTR_TARGET(field2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) TRB_TO_VF_ID(field3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) field3 & TRB_CYCLE ? 'C' : 'c');
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) case TRB_SET_LT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) snprintf(str, size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497) "%s: belt %d flags %c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) xhci_trb_type_string(type),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) TRB_TO_BELT(field3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) field3 & TRB_CYCLE ? 'C' : 'c');
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) case TRB_GET_BW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) snprintf(str, size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504) "%s: ctx %08x%08x slot %d speed %d flags %c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505) xhci_trb_type_string(type),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) field1, field0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507) TRB_TO_SLOT_ID(field3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) TRB_TO_DEV_SPEED(field3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) field3 & TRB_CYCLE ? 'C' : 'c');
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) case TRB_FORCE_HEADER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) snprintf(str, size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513) "%s: info %08x%08x%08x pkt type %d roothub port %d flags %c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514) xhci_trb_type_string(type),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) field2, field1, field0 & 0xffffffe0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) TRB_TO_PACKET_TYPE(field0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517) TRB_TO_ROOTHUB_PORT(field3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) field3 & TRB_CYCLE ? 'C' : 'c');
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) snprintf(str, size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) "type '%s' -> raw %08x %08x %08x %08x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) xhci_trb_type_string(type),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524) field0, field1, field2, field3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) return str;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530) static inline const char *xhci_decode_ctrl_ctx(char *str,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531) unsigned long drop, unsigned long add)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) unsigned int bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) str[0] = '\0';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538) if (drop) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539) ret = sprintf(str, "Drop:");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540) for_each_set_bit(bit, &drop, 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) ret += sprintf(str + ret, " %d%s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542) bit / 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543) bit % 2 ? "in":"out");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) ret += sprintf(str + ret, ", ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547) if (add) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) ret += sprintf(str + ret, "Add:%s%s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549) (add & SLOT_FLAG) ? " slot":"",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) (add & EP0_FLAG) ? " ep0":"");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551) add &= ~(SLOT_FLAG | EP0_FLAG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552) for_each_set_bit(bit, &add, 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553) ret += sprintf(str + ret, " %d%s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554) bit / 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555) bit % 2 ? "in":"out");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557) return str;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560) static inline const char *xhci_decode_slot_context(char *str,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561) u32 info, u32 info2, u32 tt_info, u32 state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563) u32 speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564) u32 hub;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565) u32 mtt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568) speed = info & DEV_SPEED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569) hub = info & DEV_HUB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570) mtt = info & DEV_MTT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572) ret = sprintf(str, "RS %05x %s%s%s Ctx Entries %d MEL %d us Port# %d/%d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) info & ROUTE_STRING_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574) ({ char *s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575) switch (speed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576) case SLOT_SPEED_FS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577) s = "full-speed";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579) case SLOT_SPEED_LS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580) s = "low-speed";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582) case SLOT_SPEED_HS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583) s = "high-speed";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) case SLOT_SPEED_SS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586) s = "super-speed";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588) case SLOT_SPEED_SSP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589) s = "super-speed plus";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592) s = "UNKNOWN speed";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593) } s; }),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) mtt ? " multi-TT" : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595) hub ? " Hub" : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596) (info & LAST_CTX_MASK) >> 27,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597) info2 & MAX_EXIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598) DEVINFO_TO_ROOT_HUB_PORT(info2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599) DEVINFO_TO_MAX_PORTS(info2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601) ret += sprintf(str + ret, " [TT Slot %d Port# %d TTT %d Intr %d] Addr %d State %s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602) tt_info & TT_SLOT, (tt_info & TT_PORT) >> 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603) GET_TT_THINK_TIME(tt_info), GET_INTR_TARGET(tt_info),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604) state & DEV_ADDR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605) xhci_slot_state_string(GET_SLOT_STATE(state)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607) return str;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611) static inline const char *xhci_portsc_link_state_string(u32 portsc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613) switch (portsc & PORT_PLS_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614) case XDEV_U0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615) return "U0";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616) case XDEV_U1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617) return "U1";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618) case XDEV_U2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619) return "U2";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620) case XDEV_U3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621) return "U3";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622) case XDEV_DISABLED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623) return "Disabled";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624) case XDEV_RXDETECT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625) return "RxDetect";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626) case XDEV_INACTIVE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627) return "Inactive";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628) case XDEV_POLLING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629) return "Polling";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630) case XDEV_RECOVERY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631) return "Recovery";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632) case XDEV_HOT_RESET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633) return "Hot Reset";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634) case XDEV_COMP_MODE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635) return "Compliance mode";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636) case XDEV_TEST_MODE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637) return "Test mode";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638) case XDEV_RESUME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639) return "Resume";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643) return "Unknown";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646) static inline const char *xhci_decode_portsc(char *str, u32 portsc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650) ret = sprintf(str, "%s %s %s Link:%s PortSpeed:%d ",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651) portsc & PORT_POWER ? "Powered" : "Powered-off",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652) portsc & PORT_CONNECT ? "Connected" : "Not-connected",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653) portsc & PORT_PE ? "Enabled" : "Disabled",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654) xhci_portsc_link_state_string(portsc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655) DEV_PORT_SPEED(portsc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657) if (portsc & PORT_OC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658) ret += sprintf(str + ret, "OverCurrent ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659) if (portsc & PORT_RESET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660) ret += sprintf(str + ret, "In-Reset ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662) ret += sprintf(str + ret, "Change: ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663) if (portsc & PORT_CSC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664) ret += sprintf(str + ret, "CSC ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665) if (portsc & PORT_PEC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666) ret += sprintf(str + ret, "PEC ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667) if (portsc & PORT_WRC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668) ret += sprintf(str + ret, "WRC ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669) if (portsc & PORT_OCC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670) ret += sprintf(str + ret, "OCC ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671) if (portsc & PORT_RC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672) ret += sprintf(str + ret, "PRC ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673) if (portsc & PORT_PLC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674) ret += sprintf(str + ret, "PLC ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675) if (portsc & PORT_CEC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2676) ret += sprintf(str + ret, "CEC ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2677) if (portsc & PORT_CAS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2678) ret += sprintf(str + ret, "CAS ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2680) ret += sprintf(str + ret, "Wake: ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2681) if (portsc & PORT_WKCONN_E)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2682) ret += sprintf(str + ret, "WCE ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2683) if (portsc & PORT_WKDISC_E)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2684) ret += sprintf(str + ret, "WDE ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2685) if (portsc & PORT_WKOC_E)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2686) ret += sprintf(str + ret, "WOE ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2688) return str;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2689) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2691) static inline const char *xhci_decode_usbsts(char *str, u32 usbsts)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2692) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2693) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2695) ret = sprintf(str, " 0x%08x", usbsts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2697) if (usbsts == ~(u32)0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2698) return str;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2700) if (usbsts & STS_HALT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2701) ret += sprintf(str + ret, " HCHalted");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2702) if (usbsts & STS_FATAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2703) ret += sprintf(str + ret, " HSE");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2704) if (usbsts & STS_EINT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2705) ret += sprintf(str + ret, " EINT");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2706) if (usbsts & STS_PORT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2707) ret += sprintf(str + ret, " PCD");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2708) if (usbsts & STS_SAVE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2709) ret += sprintf(str + ret, " SSS");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2710) if (usbsts & STS_RESTORE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2711) ret += sprintf(str + ret, " RSS");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2712) if (usbsts & STS_SRE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2713) ret += sprintf(str + ret, " SRE");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2714) if (usbsts & STS_CNR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2715) ret += sprintf(str + ret, " CNR");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2716) if (usbsts & STS_HCE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2717) ret += sprintf(str + ret, " HCE");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2719) return str;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2720) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2722) static inline const char *xhci_decode_doorbell(char *str, u32 slot, u32 doorbell)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2723) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2724) u8 ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2725) u16 stream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2726) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2728) ep = (doorbell & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2729) stream = doorbell >> 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2731) if (slot == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2732) sprintf(str, "Command Ring %d", doorbell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2733) return str;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2734) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2735) ret = sprintf(str, "Slot %d ", slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2736) if (ep > 0 && ep < 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2737) ret = sprintf(str + ret, "ep%d%s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2738) ep / 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2739) ep % 2 ? "in" : "out");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2740) else if (ep == 0 || ep < 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2741) ret = sprintf(str + ret, "Reserved %d", ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2742) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2743) ret = sprintf(str + ret, "Vendor Defined %d", ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2744) if (stream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2745) ret = sprintf(str + ret, " Stream %d", stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2747) return str;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2748) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2750) static inline const char *xhci_ep_state_string(u8 state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2751) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2752) switch (state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2753) case EP_STATE_DISABLED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2754) return "disabled";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2755) case EP_STATE_RUNNING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2756) return "running";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2757) case EP_STATE_HALTED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2758) return "halted";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2759) case EP_STATE_STOPPED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2760) return "stopped";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2761) case EP_STATE_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2762) return "error";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2763) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2764) return "INVALID";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2765) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2766) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2768) static inline const char *xhci_ep_type_string(u8 type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2769) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2770) switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2771) case ISOC_OUT_EP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2772) return "Isoc OUT";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2773) case BULK_OUT_EP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2774) return "Bulk OUT";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2775) case INT_OUT_EP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2776) return "Int OUT";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2777) case CTRL_EP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2778) return "Ctrl";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2779) case ISOC_IN_EP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2780) return "Isoc IN";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2781) case BULK_IN_EP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2782) return "Bulk IN";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2783) case INT_IN_EP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2784) return "Int IN";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2785) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2786) return "INVALID";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2787) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2788) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2790) static inline const char *xhci_decode_ep_context(char *str, u32 info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2791) u32 info2, u64 deq, u32 tx_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2792) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2793) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2795) u32 esit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2796) u16 maxp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2797) u16 avg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2799) u8 max_pstr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2800) u8 ep_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2801) u8 interval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2802) u8 ep_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2803) u8 burst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2804) u8 cerr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2805) u8 mult;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2807) bool lsa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2808) bool hid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2810) esit = CTX_TO_MAX_ESIT_PAYLOAD_HI(info) << 16 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2811) CTX_TO_MAX_ESIT_PAYLOAD(tx_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2813) ep_state = info & EP_STATE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2814) max_pstr = CTX_TO_EP_MAXPSTREAMS(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2815) interval = CTX_TO_EP_INTERVAL(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2816) mult = CTX_TO_EP_MULT(info) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2817) lsa = !!(info & EP_HAS_LSA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2819) cerr = (info2 & (3 << 1)) >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2820) ep_type = CTX_TO_EP_TYPE(info2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2821) hid = !!(info2 & (1 << 7));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2822) burst = CTX_TO_MAX_BURST(info2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2823) maxp = MAX_PACKET_DECODED(info2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2825) avg = EP_AVG_TRB_LENGTH(tx_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2827) ret = sprintf(str, "State %s mult %d max P. Streams %d %s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2828) xhci_ep_state_string(ep_state), mult,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2829) max_pstr, lsa ? "LSA " : "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2831) ret += sprintf(str + ret, "interval %d us max ESIT payload %d CErr %d ",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2832) (1 << interval) * 125, esit, cerr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2834) ret += sprintf(str + ret, "Type %s %sburst %d maxp %d deq %016llx ",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2835) xhci_ep_type_string(ep_type), hid ? "HID" : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2836) burst, maxp, deq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2838) ret += sprintf(str + ret, "avg trb len %d", avg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2840) return str;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2841) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2843) #endif /* __LINUX_XHCI_HCD_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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