^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * xHCI host controller driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2008 Intel Corp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author: Sarah Sharp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Some code borrowed from the Linux EHCI driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/iopoll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/log2.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/moduleparam.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/dmi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "xhci.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "xhci-trace.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include "xhci-debugfs.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include "xhci-dbgcap.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define DRIVER_AUTHOR "Sarah Sharp"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define DRIVER_DESC "'eXtensible' Host Controller (xHC) Driver"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define PORT_WAKE_BITS (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /* Some 0.95 hardware can't handle the chain bit on a Link TRB being cleared */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) static int link_quirk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) module_param(link_quirk, int, S_IRUGO | S_IWUSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) MODULE_PARM_DESC(link_quirk, "Don't clear the chain bit on a link TRB");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) static unsigned long long quirks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) module_param(quirks, ullong, S_IRUGO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) MODULE_PARM_DESC(quirks, "Bit flags for quirks to be enabled as default");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) static bool td_on_ring(struct xhci_td *td, struct xhci_ring *ring)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) struct xhci_segment *seg = ring->first_seg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) if (!td || !td->start_seg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) if (seg == td->start_seg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) seg = seg->next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) } while (seg && seg != ring->first_seg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * xhci_handshake - spin reading hc until handshake completes or fails
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * @ptr: address of hc register to be read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * @mask: bits to look at in result of read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * @done: value of those bits when handshake succeeds
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * @usec: timeout in microseconds
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * Returns negative errno, or zero on success
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * Success happens when the "mask" bits have the specified value (hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * handshake done). There are two failure modes: "usec" have passed (major
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * hardware flakeout), or the register reads as all-ones (hardware removed).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) int xhci_handshake(void __iomem *ptr, u32 mask, u32 done, u64 timeout_us)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) u32 result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) ret = readl_poll_timeout_atomic(ptr, result,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) (result & mask) == done ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) result == U32_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) 1, timeout_us);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) if (result == U32_MAX) /* card removed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * Disable interrupts and begin the xHCI halting process.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) void xhci_quiesce(struct xhci_hcd *xhci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) u32 halted;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) u32 cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) mask = ~(XHCI_IRQS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) halted = readl(&xhci->op_regs->status) & STS_HALT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) if (!halted)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) mask &= ~CMD_RUN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) cmd = readl(&xhci->op_regs->command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) cmd &= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) writel(cmd, &xhci->op_regs->command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * Force HC into halt state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * Disable any IRQs and clear the run/stop bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * HC will complete any current and actively pipelined transactions, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * should halt within 16 ms of the run/stop bit being cleared.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * Read HC Halted bit in the status register to see when the HC is finished.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) int xhci_halt(struct xhci_hcd *xhci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Halt the HC");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) xhci_quiesce(xhci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) ret = xhci_handshake(&xhci->op_regs->status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) STS_HALT, STS_HALT, XHCI_MAX_HALT_USEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) xhci_warn(xhci, "Host halt failed, %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) xhci->xhc_state |= XHCI_STATE_HALTED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * Set the run bit and wait for the host to be running.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) int xhci_start(struct xhci_hcd *xhci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) u32 temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) temp = readl(&xhci->op_regs->command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) temp |= (CMD_RUN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Turn on HC, cmd = 0x%x.",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) writel(temp, &xhci->op_regs->command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) * Wait for the HCHalted Status bit to be 0 to indicate the host is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) * running.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) ret = xhci_handshake(&xhci->op_regs->status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) STS_HALT, 0, XHCI_MAX_HALT_USEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) if (ret == -ETIMEDOUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) xhci_err(xhci, "Host took too long to start, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) "waited %u microseconds.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) XHCI_MAX_HALT_USEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /* clear state flags. Including dying, halted or removing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) xhci->xhc_state = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) * Reset a halted HC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) * This resets pipelines, timers, counters, state machines, etc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) * Transactions will be terminated immediately, and operational registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * will be set to their defaults.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) int xhci_reset(struct xhci_hcd *xhci, u64 timeout_us)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) u32 command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) u32 state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) state = readl(&xhci->op_regs->status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) if (state == ~(u32)0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) xhci_warn(xhci, "Host not accessible, reset failed.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) if ((state & STS_HALT) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) xhci_warn(xhci, "Host controller not halted, aborting reset.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Reset the HC");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) command = readl(&xhci->op_regs->command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) command |= CMD_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) writel(command, &xhci->op_regs->command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /* Existing Intel xHCI controllers require a delay of 1 mS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) * after setting the CMD_RESET bit, and before accessing any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) * HC registers. This allows the HC to complete the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) * reset operation and be ready for HC register access.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) * Without this delay, the subsequent HC register access,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) * may result in a system hang very rarely.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) if (xhci->quirks & XHCI_INTEL_HOST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) udelay(1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) ret = xhci_handshake(&xhci->op_regs->command, CMD_RESET, 0, timeout_us);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) if (xhci->quirks & XHCI_ASMEDIA_MODIFY_FLOWCONTROL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) usb_asmedia_modifyflowcontrol(to_pci_dev(xhci_to_hcd(xhci)->self.controller));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) xhci_dbg_trace(xhci, trace_xhci_dbg_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) "Wait for controller to be ready for doorbell rings");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) * xHCI cannot write to any doorbells or operational registers other
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) * than status until the "Controller Not Ready" flag is cleared.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) ret = xhci_handshake(&xhci->op_regs->status, STS_CNR, 0, timeout_us);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) xhci->usb2_rhub.bus_state.port_c_suspend = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) xhci->usb2_rhub.bus_state.suspended_ports = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) xhci->usb2_rhub.bus_state.resuming_ports = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) xhci->usb3_rhub.bus_state.port_c_suspend = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) xhci->usb3_rhub.bus_state.suspended_ports = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) xhci->usb3_rhub.bus_state.resuming_ports = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) static void xhci_zero_64b_regs(struct xhci_hcd *xhci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) int err, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) u64 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) u32 intrs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) * Some Renesas controllers get into a weird state if they are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) * reset while programmed with 64bit addresses (they will preserve
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) * the top half of the address in internal, non visible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) * registers). You end up with half the address coming from the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) * kernel, and the other half coming from the firmware. Also,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) * changing the programming leads to extra accesses even if the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) * controller is supposed to be halted. The controller ends up with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) * a fatal fault, and is then ripe for being properly reset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) * Special care is taken to only apply this if the device is behind
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) * an iommu. Doing anything when there is no iommu is definitely
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) * unsafe...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) if (!(xhci->quirks & XHCI_ZERO_64B_REGS) || !device_iommu_mapped(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) xhci_info(xhci, "Zeroing 64bit base registers, expecting fault\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) /* Clear HSEIE so that faults do not get signaled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) val = readl(&xhci->op_regs->command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) val &= ~CMD_HSEIE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) writel(val, &xhci->op_regs->command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) /* Clear HSE (aka FATAL) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) val = readl(&xhci->op_regs->status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) val |= STS_FATAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) writel(val, &xhci->op_regs->status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) /* Now zero the registers, and brace for impact */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) val = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) if (upper_32_bits(val))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) xhci_write_64(xhci, 0, &xhci->op_regs->dcbaa_ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) val = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) if (upper_32_bits(val))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) xhci_write_64(xhci, 0, &xhci->op_regs->cmd_ring);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) intrs = min_t(u32, HCS_MAX_INTRS(xhci->hcs_params1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) ARRAY_SIZE(xhci->run_regs->ir_set));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) for (i = 0; i < intrs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) struct xhci_intr_reg __iomem *ir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) ir = &xhci->run_regs->ir_set[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) val = xhci_read_64(xhci, &ir->erst_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) if (upper_32_bits(val))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) xhci_write_64(xhci, 0, &ir->erst_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) val= xhci_read_64(xhci, &ir->erst_dequeue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) if (upper_32_bits(val))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) xhci_write_64(xhci, 0, &ir->erst_dequeue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) /* Wait for the fault to appear. It will be cleared on reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) err = xhci_handshake(&xhci->op_regs->status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) STS_FATAL, STS_FATAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) XHCI_MAX_HALT_USEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) if (!err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) xhci_info(xhci, "Fault detected\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #ifdef CONFIG_USB_PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) * Set up MSI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) static int xhci_setup_msi(struct xhci_hcd *xhci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) * TODO:Check with MSI Soc for sysdev
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) xhci_dbg_trace(xhci, trace_xhci_dbg_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) "failed to allocate MSI entry");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) ret = request_irq(pdev->irq, xhci_msi_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 0, "xhci_hcd", xhci_to_hcd(xhci));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) xhci_dbg_trace(xhci, trace_xhci_dbg_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) "disable MSI interrupt");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) pci_free_irq_vectors(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) * Set up MSI-X
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) static int xhci_setup_msix(struct xhci_hcd *xhci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) int i, ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) struct usb_hcd *hcd = xhci_to_hcd(xhci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) * calculate number of msi-x vectors supported.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) * - HCS_MAX_INTRS: the max number of interrupts the host can handle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) * with max number of interrupters based on the xhci HCSPARAMS1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) * - num_online_cpus: maximum msi-x vectors per CPUs core.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) * Add additional 1 vector to ensure always available interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) xhci->msix_count = min(num_online_cpus() + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) HCS_MAX_INTRS(xhci->hcs_params1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) ret = pci_alloc_irq_vectors(pdev, xhci->msix_count, xhci->msix_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) PCI_IRQ_MSIX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) xhci_dbg_trace(xhci, trace_xhci_dbg_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) "Failed to enable MSI-X");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) for (i = 0; i < xhci->msix_count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) ret = request_irq(pci_irq_vector(pdev, i), xhci_msi_irq, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) "xhci_hcd", xhci_to_hcd(xhci));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) goto disable_msix;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) hcd->msix_enabled = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) disable_msix:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) xhci_dbg_trace(xhci, trace_xhci_dbg_init, "disable MSI-X interrupt");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) while (--i >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) free_irq(pci_irq_vector(pdev, i), xhci_to_hcd(xhci));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) pci_free_irq_vectors(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) /* Free any IRQs and disable MSI-X */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) static void xhci_cleanup_msix(struct xhci_hcd *xhci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) struct usb_hcd *hcd = xhci_to_hcd(xhci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) if (xhci->quirks & XHCI_PLAT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) /* return if using legacy interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) if (hcd->irq > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) if (hcd->msix_enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) for (i = 0; i < xhci->msix_count; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) free_irq(pci_irq_vector(pdev, i), xhci_to_hcd(xhci));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) free_irq(pci_irq_vector(pdev, 0), xhci_to_hcd(xhci));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) pci_free_irq_vectors(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) hcd->msix_enabled = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) static void __maybe_unused xhci_msix_sync_irqs(struct xhci_hcd *xhci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) struct usb_hcd *hcd = xhci_to_hcd(xhci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) if (hcd->msix_enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) for (i = 0; i < xhci->msix_count; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) synchronize_irq(pci_irq_vector(pdev, i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) static int xhci_try_enable_msi(struct usb_hcd *hcd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) struct xhci_hcd *xhci = hcd_to_xhci(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) struct pci_dev *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) /* The xhci platform device has set up IRQs through usb_add_hcd. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) if (xhci->quirks & XHCI_PLAT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) * Some Fresco Logic host controllers advertise MSI, but fail to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) * generate interrupts. Don't even try to enable MSI.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) if (xhci->quirks & XHCI_BROKEN_MSI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) goto legacy_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) /* unregister the legacy interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) if (hcd->irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) free_irq(hcd->irq, hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) hcd->irq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) ret = xhci_setup_msix(xhci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) /* fall back to msi*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) ret = xhci_setup_msi(xhci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) hcd->msi_enabled = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) if (!pdev->irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) xhci_err(xhci, "No msi-x/msi found and no IRQ in BIOS\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) legacy_irq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) if (!strlen(hcd->irq_descr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) snprintf(hcd->irq_descr, sizeof(hcd->irq_descr), "%s:usb%d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) hcd->driver->description, hcd->self.busnum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) /* fall back to legacy interrupt*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) ret = request_irq(pdev->irq, &usb_hcd_irq, IRQF_SHARED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) hcd->irq_descr, hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) xhci_err(xhci, "request interrupt %d failed\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) pdev->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) hcd->irq = pdev->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) static inline int xhci_try_enable_msi(struct usb_hcd *hcd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) static inline void xhci_cleanup_msix(struct xhci_hcd *xhci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) static inline void xhci_msix_sync_irqs(struct xhci_hcd *xhci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) static void compliance_mode_recovery(struct timer_list *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) struct xhci_hcd *xhci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) struct usb_hcd *hcd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) struct xhci_hub *rhub;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) u32 temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) xhci = from_timer(xhci, t, comp_mode_recovery_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) rhub = &xhci->usb3_rhub;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) for (i = 0; i < rhub->num_ports; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) temp = readl(rhub->ports[i]->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) if ((temp & PORT_PLS_MASK) == USB_SS_PORT_LS_COMP_MOD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) * Compliance Mode Detected. Letting USB Core
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) * handle the Warm Reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) "Compliance mode detected->port %d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) i + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) "Attempting compliance mode recovery");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) hcd = xhci->shared_hcd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) if (hcd->state == HC_STATE_SUSPENDED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) usb_hcd_resume_root_hub(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) usb_hcd_poll_rh_status(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) if (xhci->port_status_u0 != ((1 << rhub->num_ports) - 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) mod_timer(&xhci->comp_mode_recovery_timer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) jiffies + msecs_to_jiffies(COMP_MODE_RCVRY_MSECS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) * Quirk to work around issue generated by the SN65LVPE502CP USB3.0 re-driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) * that causes ports behind that hardware to enter compliance mode sometimes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) * The quirk creates a timer that polls every 2 seconds the link state of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) * each host controller's port and recovers it by issuing a Warm reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) * if Compliance mode is detected, otherwise the port will become "dead" (no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) * device connections or disconnections will be detected anymore). Becasue no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) * status event is generated when entering compliance mode (per xhci spec),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) * this quirk is needed on systems that have the failing hardware installed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) static void compliance_mode_recovery_timer_init(struct xhci_hcd *xhci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) xhci->port_status_u0 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) timer_setup(&xhci->comp_mode_recovery_timer, compliance_mode_recovery,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) xhci->comp_mode_recovery_timer.expires = jiffies +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) msecs_to_jiffies(COMP_MODE_RCVRY_MSECS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) add_timer(&xhci->comp_mode_recovery_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) "Compliance mode recovery timer initialized");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) * This function identifies the systems that have installed the SN65LVPE502CP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) * USB3.0 re-driver and that need the Compliance Mode Quirk.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) * Systems:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) * Vendor: Hewlett-Packard -> System Models: Z420, Z620 and Z820
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) static bool xhci_compliance_mode_recovery_timer_quirk_check(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) const char *dmi_product_name, *dmi_sys_vendor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) dmi_product_name = dmi_get_system_info(DMI_PRODUCT_NAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) dmi_sys_vendor = dmi_get_system_info(DMI_SYS_VENDOR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) if (!dmi_product_name || !dmi_sys_vendor)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) if (!(strstr(dmi_sys_vendor, "Hewlett-Packard")))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) if (strstr(dmi_product_name, "Z420") ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) strstr(dmi_product_name, "Z620") ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) strstr(dmi_product_name, "Z820") ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) strstr(dmi_product_name, "Z1 Workstation"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) static int xhci_all_ports_seen_u0(struct xhci_hcd *xhci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) return (xhci->port_status_u0 == ((1 << xhci->usb3_rhub.num_ports) - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) * Initialize memory for HCD and xHC (one-time init).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) * Program the PAGESIZE register, initialize the device context array, create
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) * device contexts (?), set up a command ring segment (or two?), create event
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) * ring (one for now).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) static int xhci_init(struct usb_hcd *hcd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) struct xhci_hcd *xhci = hcd_to_xhci(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) int retval = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) xhci_dbg_trace(xhci, trace_xhci_dbg_init, "xhci_init");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) spin_lock_init(&xhci->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) if (xhci->hci_version == 0x95 && link_quirk) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) "QUIRK: Not clearing Link TRB chain bits.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) xhci->quirks |= XHCI_LINK_TRB_QUIRK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) xhci_dbg_trace(xhci, trace_xhci_dbg_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) "xHCI doesn't need link TRB QUIRK");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) retval = xhci_mem_init(xhci, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Finished xhci_init");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) /* Initializing Compliance Mode Recovery Data If Needed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) if (xhci_compliance_mode_recovery_timer_quirk_check()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) xhci->quirks |= XHCI_COMP_MODE_QUIRK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) compliance_mode_recovery_timer_init(xhci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) /*-------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) static int xhci_run_finished(struct xhci_hcd *xhci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) if (xhci_start(xhci)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) xhci_halt(xhci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) xhci->shared_hcd->state = HC_STATE_RUNNING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) xhci->cmd_ring_state = CMD_RING_STATE_RUNNING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) if (xhci->quirks & XHCI_NEC_HOST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) xhci_ring_cmd_db(xhci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) xhci_dbg_trace(xhci, trace_xhci_dbg_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) "Finished xhci_run for USB3 roothub");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) * Start the HC after it was halted.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) * This function is called by the USB core when the HC driver is added.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) * Its opposite is xhci_stop().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) * xhci_init() must be called once before this function can be called.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) * Reset the HC, enable device slot contexts, program DCBAAP, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) * set command ring pointer and event ring pointer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) * Setup MSI-X vectors and enable interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) int xhci_run(struct usb_hcd *hcd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) u32 temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) u64 temp_64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) struct xhci_hcd *xhci = hcd_to_xhci(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) /* Start the xHCI host controller running only after the USB 2.0 roothub
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) * is setup.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) hcd->uses_new_polling = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) if (!usb_hcd_is_primary_hcd(hcd))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) return xhci_run_finished(xhci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) xhci_dbg_trace(xhci, trace_xhci_dbg_init, "xhci_run");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) ret = xhci_try_enable_msi(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) temp_64 &= ~ERST_PTR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) xhci_dbg_trace(xhci, trace_xhci_dbg_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) "ERST deq = 64'h%0lx", (long unsigned int) temp_64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) xhci_dbg_trace(xhci, trace_xhci_dbg_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) "// Set the interrupt modulation register");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) temp = readl(&xhci->ir_set->irq_control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) temp &= ~ER_IRQ_INTERVAL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) temp |= (xhci->imod_interval / 250) & ER_IRQ_INTERVAL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) writel(temp, &xhci->ir_set->irq_control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) /* Set the HCD state before we enable the irqs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) temp = readl(&xhci->op_regs->command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) temp |= (CMD_EIE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) xhci_dbg_trace(xhci, trace_xhci_dbg_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) "// Enable interrupts, cmd = 0x%x.", temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) writel(temp, &xhci->op_regs->command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) temp = readl(&xhci->ir_set->irq_pending);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) xhci_dbg_trace(xhci, trace_xhci_dbg_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) "// Enabling event ring interrupter %p by writing 0x%x to irq_pending",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) xhci->ir_set, (unsigned int) ER_IRQ_ENABLE(temp));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) writel(ER_IRQ_ENABLE(temp), &xhci->ir_set->irq_pending);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) if (xhci->quirks & XHCI_NEC_HOST) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) struct xhci_command *command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) command = xhci_alloc_command(xhci, false, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) if (!command)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) ret = xhci_queue_vendor_command(xhci, command, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) TRB_TYPE(TRB_NEC_GET_FW));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) xhci_free_command(xhci, command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) xhci_dbg_trace(xhci, trace_xhci_dbg_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) "Finished xhci_run for USB2 roothub");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) xhci_dbc_init(xhci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) xhci_debugfs_init(xhci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) EXPORT_SYMBOL_GPL(xhci_run);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) * Stop xHCI driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) * This function is called by the USB core when the HC driver is removed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) * Its opposite is xhci_run().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) * Disable device contexts, disable IRQs, and quiesce the HC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) * Reset the HC, finish any completed transactions, and cleanup memory.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) static void xhci_stop(struct usb_hcd *hcd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) u32 temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) struct xhci_hcd *xhci = hcd_to_xhci(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) mutex_lock(&xhci->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) /* Only halt host and free memory after both hcds are removed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) if (!usb_hcd_is_primary_hcd(hcd)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) mutex_unlock(&xhci->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) xhci_dbc_exit(xhci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) spin_lock_irq(&xhci->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) xhci->xhc_state |= XHCI_STATE_HALTED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) xhci_halt(xhci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) xhci_reset(xhci, XHCI_RESET_SHORT_USEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) spin_unlock_irq(&xhci->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) xhci_cleanup_msix(xhci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) /* Deleting Compliance Mode Recovery Timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) (!(xhci_all_ports_seen_u0(xhci)))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) del_timer_sync(&xhci->comp_mode_recovery_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) "%s: compliance mode recovery timer deleted",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) if (xhci->quirks & XHCI_AMD_PLL_FIX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) usb_amd_dev_put();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) xhci_dbg_trace(xhci, trace_xhci_dbg_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) "// Disabling event ring interrupts");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) temp = readl(&xhci->op_regs->status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) writel((temp & ~0x1fff) | STS_EINT, &xhci->op_regs->status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) temp = readl(&xhci->ir_set->irq_pending);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) writel(ER_IRQ_DISABLE(temp), &xhci->ir_set->irq_pending);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) xhci_dbg_trace(xhci, trace_xhci_dbg_init, "cleaning up memory");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) xhci_mem_cleanup(xhci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) xhci_debugfs_exit(xhci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) xhci_dbg_trace(xhci, trace_xhci_dbg_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) "xhci_stop completed - status = %x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) readl(&xhci->op_regs->status));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) mutex_unlock(&xhci->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) * Shutdown HC (not bus-specific)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) * This is called when the machine is rebooting or halting. We assume that the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) * machine will be powered off, and the HC's internal state will be reset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) * Don't bother to free memory.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) * This will only ever be called with the main usb_hcd (the USB3 roothub).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) void xhci_shutdown(struct usb_hcd *hcd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) struct xhci_hcd *xhci = hcd_to_xhci(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) if (xhci->quirks & XHCI_SPURIOUS_REBOOT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) usb_disable_xhci_ports(to_pci_dev(hcd->self.sysdev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) spin_lock_irq(&xhci->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) xhci_halt(xhci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) /* Workaround for spurious wakeups at shutdown with HSW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) xhci_reset(xhci, XHCI_RESET_SHORT_USEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) spin_unlock_irq(&xhci->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) xhci_cleanup_msix(xhci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) xhci_dbg_trace(xhci, trace_xhci_dbg_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) "xhci_shutdown completed - status = %x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) readl(&xhci->op_regs->status));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) EXPORT_SYMBOL_GPL(xhci_shutdown);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) static void xhci_save_registers(struct xhci_hcd *xhci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) xhci->s3.command = readl(&xhci->op_regs->command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) xhci->s3.dev_nt = readl(&xhci->op_regs->dev_notification);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) xhci->s3.dcbaa_ptr = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) xhci->s3.config_reg = readl(&xhci->op_regs->config_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) xhci->s3.erst_size = readl(&xhci->ir_set->erst_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) xhci->s3.erst_base = xhci_read_64(xhci, &xhci->ir_set->erst_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) xhci->s3.erst_dequeue = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) xhci->s3.irq_pending = readl(&xhci->ir_set->irq_pending);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) xhci->s3.irq_control = readl(&xhci->ir_set->irq_control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) static void xhci_restore_registers(struct xhci_hcd *xhci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) writel(xhci->s3.command, &xhci->op_regs->command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) writel(xhci->s3.dev_nt, &xhci->op_regs->dev_notification);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) xhci_write_64(xhci, xhci->s3.dcbaa_ptr, &xhci->op_regs->dcbaa_ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) writel(xhci->s3.config_reg, &xhci->op_regs->config_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) writel(xhci->s3.erst_size, &xhci->ir_set->erst_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) xhci_write_64(xhci, xhci->s3.erst_base, &xhci->ir_set->erst_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) xhci_write_64(xhci, xhci->s3.erst_dequeue, &xhci->ir_set->erst_dequeue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) writel(xhci->s3.irq_pending, &xhci->ir_set->irq_pending);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) writel(xhci->s3.irq_control, &xhci->ir_set->irq_control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) static void xhci_set_cmd_ring_deq(struct xhci_hcd *xhci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) u64 val_64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) /* step 2: initialize command ring buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) val_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) val_64 = (val_64 & (u64) CMD_RING_RSVD_BITS) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) (xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) xhci->cmd_ring->dequeue) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) (u64) ~CMD_RING_RSVD_BITS) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) xhci->cmd_ring->cycle_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) xhci_dbg_trace(xhci, trace_xhci_dbg_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) "// Setting command ring address to 0x%llx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) (long unsigned long) val_64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) xhci_write_64(xhci, val_64, &xhci->op_regs->cmd_ring);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) * The whole command ring must be cleared to zero when we suspend the host.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) * The host doesn't save the command ring pointer in the suspend well, so we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) * need to re-program it on resume. Unfortunately, the pointer must be 64-byte
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) * aligned, because of the reserved bits in the command ring dequeue pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) * register. Therefore, we can't just set the dequeue pointer back in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) * middle of the ring (TRBs are 16-byte aligned).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) static void xhci_clear_command_ring(struct xhci_hcd *xhci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) struct xhci_ring *ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) struct xhci_segment *seg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) ring = xhci->cmd_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) seg = ring->deq_seg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) memset(seg->trbs, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) sizeof(union xhci_trb) * (TRBS_PER_SEGMENT - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) seg->trbs[TRBS_PER_SEGMENT - 1].link.control &=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) cpu_to_le32(~TRB_CYCLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) seg = seg->next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) } while (seg != ring->deq_seg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) /* Reset the software enqueue and dequeue pointers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) ring->deq_seg = ring->first_seg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) ring->dequeue = ring->first_seg->trbs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) ring->enq_seg = ring->deq_seg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) ring->enqueue = ring->dequeue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) ring->num_trbs_free = ring->num_segs * (TRBS_PER_SEGMENT - 1) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) * Ring is now zeroed, so the HW should look for change of ownership
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) * when the cycle bit is set to 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) ring->cycle_state = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) * Reset the hardware dequeue pointer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) * Yes, this will need to be re-written after resume, but we're paranoid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) * and want to make sure the hardware doesn't access bogus memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) * because, say, the BIOS or an SMI started the host without changing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) * the command ring pointers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) xhci_set_cmd_ring_deq(xhci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) * Disable port wake bits if do_wakeup is not set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) * Also clear a possible internal port wake state left hanging for ports that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) * detected termination but never successfully enumerated (trained to 0U).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) * Internal wake causes immediate xHCI wake after suspend. PORT_CSC write done
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) * at enumeration clears this wake, force one here as well for unconnected ports
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) static void xhci_disable_hub_port_wake(struct xhci_hcd *xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) struct xhci_hub *rhub,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) bool do_wakeup)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) u32 t1, t2, portsc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) spin_lock_irqsave(&xhci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) for (i = 0; i < rhub->num_ports; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) portsc = readl(rhub->ports[i]->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) t1 = xhci_port_state_to_neutral(portsc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) t2 = t1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) /* clear wake bits if do_wake is not set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) if (!do_wakeup)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) t2 &= ~PORT_WAKE_BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) /* Don't touch csc bit if connected or connect change is set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) if (!(portsc & (PORT_CSC | PORT_CONNECT)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) t2 |= PORT_CSC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) if (t1 != t2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) writel(t2, rhub->ports[i]->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) xhci_dbg(xhci, "config port %d-%d wake bits, portsc: 0x%x, write: 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) rhub->hcd->self.busnum, i + 1, portsc, t2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) spin_unlock_irqrestore(&xhci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) static bool xhci_pending_portevent(struct xhci_hcd *xhci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) struct xhci_port **ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) int port_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) u32 portsc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) status = readl(&xhci->op_regs->status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) if (status & STS_EINT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) * Checking STS_EINT is not enough as there is a lag between a change
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) * bit being set and the Port Status Change Event that it generated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) * being written to the Event Ring. See note in xhci 1.1 section 4.19.2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) port_index = xhci->usb2_rhub.num_ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) ports = xhci->usb2_rhub.ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) while (port_index--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) portsc = readl(ports[port_index]->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) if (portsc & PORT_CHANGE_MASK ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) (portsc & PORT_PLS_MASK) == XDEV_RESUME)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) port_index = xhci->usb3_rhub.num_ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) ports = xhci->usb3_rhub.ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) while (port_index--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) portsc = readl(ports[port_index]->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) if (portsc & PORT_CHANGE_MASK ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) (portsc & PORT_PLS_MASK) == XDEV_RESUME)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) * Stop HC (not bus-specific)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) * This is called when the machine transition into S3/S4 mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) int xhci_suspend(struct xhci_hcd *xhci, bool do_wakeup)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) int rc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) unsigned int delay = XHCI_MAX_HALT_USEC * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) struct usb_hcd *hcd = xhci_to_hcd(xhci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) u32 command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) u32 res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) if (!hcd->state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) if (hcd->state != HC_STATE_SUSPENDED ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) xhci->shared_hcd->state != HC_STATE_SUSPENDED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) /* Clear root port wake on bits if wakeup not allowed. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) xhci_disable_hub_port_wake(xhci, &xhci->usb3_rhub, do_wakeup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) xhci_disable_hub_port_wake(xhci, &xhci->usb2_rhub, do_wakeup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) if (!HCD_HW_ACCESSIBLE(hcd))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) xhci_dbc_suspend(xhci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) /* Don't poll the roothubs on bus suspend. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) xhci_dbg(xhci, "%s: stopping usb%d port polling.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) __func__, hcd->self.busnum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) del_timer_sync(&hcd->rh_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) clear_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) del_timer_sync(&xhci->shared_hcd->rh_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) if (xhci->quirks & XHCI_SUSPEND_DELAY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) usleep_range(1000, 1500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) spin_lock_irq(&xhci->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) clear_bit(HCD_FLAG_HW_ACCESSIBLE, &xhci->shared_hcd->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) /* step 1: stop endpoint */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) /* skipped assuming that port suspend has done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) /* step 2: clear Run/Stop bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) command = readl(&xhci->op_regs->command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) command &= ~CMD_RUN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) writel(command, &xhci->op_regs->command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) /* Some chips from Fresco Logic need an extraordinary delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) delay *= (xhci->quirks & XHCI_SLOW_SUSPEND) ? 10 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) if (xhci_handshake(&xhci->op_regs->status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) STS_HALT, STS_HALT, delay)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) xhci_warn(xhci, "WARN: xHC CMD_RUN timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) spin_unlock_irq(&xhci->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) xhci_clear_command_ring(xhci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) /* step 3: save registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) xhci_save_registers(xhci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) /* step 4: set CSS flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) command = readl(&xhci->op_regs->command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) command |= CMD_CSS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) writel(command, &xhci->op_regs->command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) xhci->broken_suspend = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) if (xhci_handshake(&xhci->op_regs->status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) STS_SAVE, 0, 20 * 1000)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) * AMD SNPS xHC 3.0 occasionally does not clear the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) * SSS bit of USBSTS and when driver tries to poll
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) * to see if the xHC clears BIT(8) which never happens
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) * and driver assumes that controller is not responding
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) * and times out. To workaround this, its good to check
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) * if SRE and HCE bits are not set (as per xhci
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) * Section 5.4.2) and bypass the timeout.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) res = readl(&xhci->op_regs->status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) if ((xhci->quirks & XHCI_SNPS_BROKEN_SUSPEND) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) (((res & STS_SRE) == 0) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) ((res & STS_HCE) == 0))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) xhci->broken_suspend = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) xhci_warn(xhci, "WARN: xHC save state timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) spin_unlock_irq(&xhci->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) spin_unlock_irq(&xhci->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) * Deleting Compliance Mode Recovery Timer because the xHCI Host
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) * is about to be suspended.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) (!(xhci_all_ports_seen_u0(xhci)))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) del_timer_sync(&xhci->comp_mode_recovery_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) "%s: compliance mode recovery timer deleted",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) /* step 5: remove core well power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) /* synchronize irq when using MSI-X */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) xhci_msix_sync_irqs(xhci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) EXPORT_SYMBOL_GPL(xhci_suspend);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) * start xHC (not bus-specific)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) * This is called when the machine transition from S3/S4 mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) int xhci_resume(struct xhci_hcd *xhci, bool hibernated)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) u32 command, temp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) struct usb_hcd *hcd = xhci_to_hcd(xhci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) struct usb_hcd *secondary_hcd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) int retval = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) bool comp_timer_running = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) bool pending_portevent = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) bool reinit_xhc = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) if (!hcd->state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) /* Wait a bit if either of the roothubs need to settle from the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) * transition into bus suspend.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) if (time_before(jiffies, xhci->usb2_rhub.bus_state.next_statechange) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) time_before(jiffies, xhci->usb3_rhub.bus_state.next_statechange))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) msleep(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) set_bit(HCD_FLAG_HW_ACCESSIBLE, &xhci->shared_hcd->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) spin_lock_irq(&xhci->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) if (hibernated || xhci->quirks & XHCI_RESET_ON_RESUME || xhci->broken_suspend)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) reinit_xhc = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) if (!reinit_xhc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) * Some controllers might lose power during suspend, so wait
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) * for controller not ready bit to clear, just as in xHC init.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) retval = xhci_handshake(&xhci->op_regs->status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) STS_CNR, 0, 10 * 1000 * 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) if (retval) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) xhci_warn(xhci, "Controller not ready at resume %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) retval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) spin_unlock_irq(&xhci->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) /* step 1: restore register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) xhci_restore_registers(xhci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) /* step 2: initialize command ring buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) xhci_set_cmd_ring_deq(xhci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) /* step 3: restore state and start state*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) /* step 3: set CRS flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) command = readl(&xhci->op_regs->command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) command |= CMD_CRS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) writel(command, &xhci->op_regs->command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) * Some controllers take up to 55+ ms to complete the controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) * restore so setting the timeout to 100ms. Xhci specification
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) * doesn't mention any timeout value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) if (xhci_handshake(&xhci->op_regs->status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) STS_RESTORE, 0, 100 * 1000)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) xhci_warn(xhci, "WARN: xHC restore state timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) spin_unlock_irq(&xhci->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) temp = readl(&xhci->op_regs->status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) /* re-initialize the HC on Restore Error, or Host Controller Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) if (temp & (STS_SRE | STS_HCE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) reinit_xhc = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) xhci_warn(xhci, "xHC error in resume, USBSTS 0x%x, Reinit\n", temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) if (reinit_xhc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) !(xhci_all_ports_seen_u0(xhci))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) del_timer_sync(&xhci->comp_mode_recovery_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) "Compliance Mode Recovery Timer deleted!");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) /* Let the USB core know _both_ roothubs lost power. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) usb_root_hub_lost_power(xhci->main_hcd->self.root_hub);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) usb_root_hub_lost_power(xhci->shared_hcd->self.root_hub);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) xhci_dbg(xhci, "Stop HCD\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) xhci_halt(xhci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) xhci_zero_64b_regs(xhci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) retval = xhci_reset(xhci, XHCI_RESET_LONG_USEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) spin_unlock_irq(&xhci->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) if (retval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) xhci_cleanup_msix(xhci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) xhci_dbg(xhci, "// Disabling event ring interrupts\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) temp = readl(&xhci->op_regs->status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) writel((temp & ~0x1fff) | STS_EINT, &xhci->op_regs->status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) temp = readl(&xhci->ir_set->irq_pending);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) writel(ER_IRQ_DISABLE(temp), &xhci->ir_set->irq_pending);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) xhci_dbg(xhci, "cleaning up memory\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) xhci_mem_cleanup(xhci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) xhci_debugfs_exit(xhci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) xhci_dbg(xhci, "xhci_stop completed - status = %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) readl(&xhci->op_regs->status));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) /* USB core calls the PCI reinit and start functions twice:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) * first with the primary HCD, and then with the secondary HCD.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) * If we don't do the same, the host will never be started.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) if (!usb_hcd_is_primary_hcd(hcd))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) secondary_hcd = hcd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) secondary_hcd = xhci->shared_hcd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) xhci_dbg(xhci, "Initialize the xhci_hcd\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) retval = xhci_init(hcd->primary_hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) if (retval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) comp_timer_running = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) xhci_dbg(xhci, "Start the primary HCD\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) retval = xhci_run(hcd->primary_hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) if (!retval) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) xhci_dbg(xhci, "Start the secondary HCD\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) retval = xhci_run(secondary_hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) hcd->state = HC_STATE_SUSPENDED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) xhci->shared_hcd->state = HC_STATE_SUSPENDED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) /* step 4: set Run/Stop bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) command = readl(&xhci->op_regs->command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) command |= CMD_RUN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) writel(command, &xhci->op_regs->command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) xhci_handshake(&xhci->op_regs->status, STS_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) 0, 250 * 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) /* step 5: walk topology and initialize portsc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) * portpmsc and portli
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) /* this is done in bus_resume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) /* step 6: restart each of the previously
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) * Running endpoints by ringing their doorbells
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) spin_unlock_irq(&xhci->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) xhci_dbc_resume(xhci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) if (retval == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) * Resume roothubs only if there are pending events.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) * USB 3 devices resend U3 LFPS wake after a 100ms delay if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) * the first wake signalling failed, give it that chance.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) pending_portevent = xhci_pending_portevent(xhci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) if (!pending_portevent) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) msleep(120);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) pending_portevent = xhci_pending_portevent(xhci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) if (pending_portevent) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) usb_hcd_resume_root_hub(xhci->shared_hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) usb_hcd_resume_root_hub(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) * If system is subject to the Quirk, Compliance Mode Timer needs to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) * be re-initialized Always after a system resume. Ports are subject
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) * to suffer the Compliance Mode issue again. It doesn't matter if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) * ports have entered previously to U0 before system's suspension.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) && !comp_timer_running)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) compliance_mode_recovery_timer_init(xhci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) if (xhci->quirks & XHCI_ASMEDIA_MODIFY_FLOWCONTROL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) usb_asmedia_modifyflowcontrol(to_pci_dev(hcd->self.controller));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) /* Re-enable port polling. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) xhci_dbg(xhci, "%s: starting usb%d port polling.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) __func__, hcd->self.busnum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) set_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) usb_hcd_poll_rh_status(xhci->shared_hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) usb_hcd_poll_rh_status(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) EXPORT_SYMBOL_GPL(xhci_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) #endif /* CONFIG_PM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) /*-------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) * Bypass the DMA mapping if URB is suitable for Immediate Transfer (IDT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) * we'll copy the actual data into the TRB address register. This is limited to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) * transfers up to 8 bytes on output endpoints of any kind with wMaxPacketSize
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) * >= 8 bytes. If suitable for IDT only one Transfer TRB per TD is allowed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) static int xhci_map_urb_for_dma(struct usb_hcd *hcd, struct urb *urb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) gfp_t mem_flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) if (xhci_urb_suitable_for_idt(urb))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) return usb_hcd_map_urb_for_dma(hcd, urb, mem_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) * xhci_get_endpoint_index - Used for passing endpoint bitmasks between the core and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) * HCDs. Find the index for an endpoint given its descriptor. Use the return
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) * value to right shift 1 for the bitmask.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) * Index = (epnum * 2) + direction - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) * where direction = 0 for OUT, 1 for IN.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) * For control endpoints, the IN index is used (OUT index is unused), so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) * index = (epnum * 2) + direction - 1 = (epnum * 2) + 1 - 1 = (epnum * 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) unsigned int index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) if (usb_endpoint_xfer_control(desc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) index = (unsigned int) (usb_endpoint_num(desc)*2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) index = (unsigned int) (usb_endpoint_num(desc)*2) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) (usb_endpoint_dir_in(desc) ? 1 : 0) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) return index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) EXPORT_SYMBOL_GPL(xhci_get_endpoint_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) /* The reverse operation to xhci_get_endpoint_index. Calculate the USB endpoint
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) * address from the XHCI endpoint index.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) unsigned int xhci_get_endpoint_address(unsigned int ep_index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) unsigned int number = DIV_ROUND_UP(ep_index, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) unsigned int direction = ep_index % 2 ? USB_DIR_OUT : USB_DIR_IN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) return direction | number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) EXPORT_SYMBOL_GPL(xhci_get_endpoint_address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) /* Find the flag for this endpoint (for use in the control context). Use the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) * endpoint index to create a bitmask. The slot context is bit 0, endpoint 0 is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) * bit 1, etc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) static unsigned int xhci_get_endpoint_flag(struct usb_endpoint_descriptor *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) return 1 << (xhci_get_endpoint_index(desc) + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) /* Compute the last valid endpoint context index. Basically, this is the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) * endpoint index plus one. For slot contexts with more than valid endpoint,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) * we find the most significant bit set in the added contexts flags.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) * e.g. ep 1 IN (with epnum 0x81) => added_ctxs = 0b1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) * fls(0b1000) = 4, but the endpoint context index is 3, so subtract one.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) unsigned int xhci_last_valid_endpoint(u32 added_ctxs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) return fls(added_ctxs) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) /* Returns 1 if the arguments are OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) * returns 0 this is a root hub; returns -EINVAL for NULL pointers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) static int xhci_check_args(struct usb_hcd *hcd, struct usb_device *udev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) struct usb_host_endpoint *ep, int check_ep, bool check_virt_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) const char *func) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) struct xhci_hcd *xhci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) struct xhci_virt_device *virt_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) if (!hcd || (check_ep && !ep) || !udev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) pr_debug("xHCI %s called with invalid args\n", func);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) if (!udev->parent) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) pr_debug("xHCI %s called for root hub\n", func);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) xhci = hcd_to_xhci(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) if (check_virt_dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) if (!udev->slot_id || !xhci->devs[udev->slot_id]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) xhci_dbg(xhci, "xHCI %s called with unaddressed device\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) func);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) virt_dev = xhci->devs[udev->slot_id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) if (virt_dev->udev != udev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) xhci_dbg(xhci, "xHCI %s called with udev and "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) "virt_dev does not match\n", func);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) if (xhci->xhc_state & XHCI_STATE_HALTED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) static int xhci_configure_endpoint(struct xhci_hcd *xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) struct usb_device *udev, struct xhci_command *command,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) bool ctx_change, bool must_succeed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) * Full speed devices may have a max packet size greater than 8 bytes, but the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) * USB core doesn't know that until it reads the first 8 bytes of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) * descriptor. If the usb_device's max packet size changes after that point,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) * we need to issue an evaluate context command and wait on it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) static int xhci_check_maxpacket(struct xhci_hcd *xhci, unsigned int slot_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) unsigned int ep_index, struct urb *urb, gfp_t mem_flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) struct xhci_container_ctx *out_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) struct xhci_input_control_ctx *ctrl_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) struct xhci_ep_ctx *ep_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) struct xhci_command *command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) int max_packet_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) int hw_max_packet_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) out_ctx = xhci->devs[slot_id]->out_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) hw_max_packet_size = MAX_PACKET_DECODED(le32_to_cpu(ep_ctx->ep_info2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) max_packet_size = usb_endpoint_maxp(&urb->dev->ep0.desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) if (hw_max_packet_size != max_packet_size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) "Max Packet Size for ep 0 changed.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) "Max packet size in usb_device = %d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) max_packet_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) "Max packet size in xHCI HW = %d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) hw_max_packet_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) "Issuing evaluate context command.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) /* Set up the input context flags for the command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) /* FIXME: This won't work if a non-default control endpoint
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) * changes max packet sizes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) command = xhci_alloc_command(xhci, true, mem_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) if (!command)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) command->in_ctx = xhci->devs[slot_id]->in_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) if (!ctrl_ctx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) goto command_cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) /* Set up the modified control endpoint 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) xhci_endpoint_copy(xhci, xhci->devs[slot_id]->in_ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) xhci->devs[slot_id]->out_ctx, ep_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) ep_ctx = xhci_get_ep_ctx(xhci, command->in_ctx, ep_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) ep_ctx->ep_info &= cpu_to_le32(~EP_STATE_MASK);/* must clear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) ep_ctx->ep_info2 &= cpu_to_le32(~MAX_PACKET_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) ep_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(max_packet_size));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) ctrl_ctx->add_flags = cpu_to_le32(EP0_FLAG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) ctrl_ctx->drop_flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) ret = xhci_configure_endpoint(xhci, urb->dev, command,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) true, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) /* Clean up the input context for later use by bandwidth
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) * functions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) command_cleanup:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) kfree(command->completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) kfree(command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) * non-error returns are a promise to giveback() the urb later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) * we drop ownership so next owner (or urb unlink) can get it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) static int xhci_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) struct xhci_hcd *xhci = hcd_to_xhci(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) unsigned int slot_id, ep_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) unsigned int *ep_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) struct urb_priv *urb_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) int num_tds;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) if (!urb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) ret = xhci_check_args(hcd, urb->dev, urb->ep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) true, true, __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) if (ret <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) return ret ? ret : -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) slot_id = urb->dev->slot_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) ep_index = xhci_get_endpoint_index(&urb->ep->desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) ep_state = &xhci->devs[slot_id]->eps[ep_index].ep_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) if (!HCD_HW_ACCESSIBLE(hcd)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) if (!in_interrupt())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) xhci_dbg(xhci, "urb submitted during PCI suspend\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) return -ESHUTDOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) if (xhci->devs[slot_id]->flags & VDEV_PORT_ERROR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) xhci_dbg(xhci, "Can't queue urb, port error, link inactive\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) if (xhci_vendor_usb_offload_skip_urb(xhci, urb)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) xhci_dbg(xhci, "skip urb for usb offload\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) if (usb_endpoint_xfer_isoc(&urb->ep->desc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) num_tds = urb->number_of_packets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) else if (usb_endpoint_is_bulk_out(&urb->ep->desc) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) urb->transfer_buffer_length > 0 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) urb->transfer_flags & URB_ZERO_PACKET &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) !(urb->transfer_buffer_length % usb_endpoint_maxp(&urb->ep->desc)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) num_tds = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) num_tds = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) urb_priv = kzalloc(struct_size(urb_priv, td, num_tds), mem_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) if (!urb_priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) urb_priv->num_tds = num_tds;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) urb_priv->num_tds_done = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) urb->hcpriv = urb_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) trace_xhci_urb_enqueue(urb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) if (usb_endpoint_xfer_control(&urb->ep->desc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) /* Check to see if the max packet size for the default control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) * endpoint changed during FS device enumeration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) if (urb->dev->speed == USB_SPEED_FULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) ret = xhci_check_maxpacket(xhci, slot_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) ep_index, urb, mem_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) xhci_urb_free_priv(urb_priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) urb->hcpriv = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) spin_lock_irqsave(&xhci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) if (xhci->xhc_state & XHCI_STATE_DYING) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) xhci_dbg(xhci, "Ep 0x%x: URB %p submitted for non-responsive xHCI host.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) urb->ep->desc.bEndpointAddress, urb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) ret = -ESHUTDOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) goto free_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) if (*ep_state & (EP_GETTING_STREAMS | EP_GETTING_NO_STREAMS)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) xhci_warn(xhci, "WARN: Can't enqueue URB, ep in streams transition state %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) *ep_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) goto free_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) if (*ep_state & EP_SOFT_CLEAR_TOGGLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) xhci_warn(xhci, "Can't enqueue URB while manually clearing toggle\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) goto free_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) switch (usb_endpoint_type(&urb->ep->desc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) case USB_ENDPOINT_XFER_CONTROL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) ret = xhci_queue_ctrl_tx(xhci, GFP_ATOMIC, urb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) slot_id, ep_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) case USB_ENDPOINT_XFER_BULK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) ret = xhci_queue_bulk_tx(xhci, GFP_ATOMIC, urb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) slot_id, ep_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) case USB_ENDPOINT_XFER_INT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) ret = xhci_queue_intr_tx(xhci, GFP_ATOMIC, urb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) slot_id, ep_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) case USB_ENDPOINT_XFER_ISOC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) ret = xhci_queue_isoc_tx_prepare(xhci, GFP_ATOMIC, urb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) slot_id, ep_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) free_priv:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) xhci_urb_free_priv(urb_priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) urb->hcpriv = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) spin_unlock_irqrestore(&xhci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) * Remove the URB's TD from the endpoint ring. This may cause the HC to stop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) * USB transfers, potentially stopping in the middle of a TRB buffer. The HC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) * should pick up where it left off in the TD, unless a Set Transfer Ring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) * Dequeue Pointer is issued.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) * The TRBs that make up the buffers for the canceled URB will be "removed" from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) * the ring. Since the ring is a contiguous structure, they can't be physically
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) * removed. Instead, there are two options:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) * 1) If the HC is in the middle of processing the URB to be canceled, we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) * simply move the ring's dequeue pointer past those TRBs using the Set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) * Transfer Ring Dequeue Pointer command. This will be the common case,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) * when drivers timeout on the last submitted URB and attempt to cancel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) * 2) If the HC is in the middle of a different TD, we turn the TRBs into a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) * series of 1-TRB transfer no-op TDs. (No-ops shouldn't be chained.) The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) * HC will need to invalidate the any TRBs it has cached after the stop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) * endpoint command, as noted in the xHCI 0.95 errata.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) * 3) The TD may have completed by the time the Stop Endpoint Command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) * completes, so software needs to handle that case too.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) * This function should protect against the TD enqueueing code ringing the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) * doorbell while this code is waiting for a Stop Endpoint command to complete.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) * It also needs to account for multiple cancellations on happening at the same
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) * time for the same endpoint.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) * Note that this function can be called in any context, or so says
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) * usb_hcd_unlink_urb()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) static int xhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) u32 temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) struct xhci_hcd *xhci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) struct urb_priv *urb_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) struct xhci_td *td;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) unsigned int ep_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) struct xhci_ring *ep_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) struct xhci_virt_ep *ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) struct xhci_command *command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) struct xhci_virt_device *vdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) xhci = hcd_to_xhci(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) spin_lock_irqsave(&xhci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) trace_xhci_urb_dequeue(urb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) /* Make sure the URB hasn't completed or been unlinked already */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) ret = usb_hcd_check_unlink_urb(hcd, urb, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) /* give back URB now if we can't queue it for cancel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) vdev = xhci->devs[urb->dev->slot_id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) urb_priv = urb->hcpriv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) if (!vdev || !urb_priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) goto err_giveback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) ep_index = xhci_get_endpoint_index(&urb->ep->desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) ep = &vdev->eps[ep_index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) if (!ep || !ep_ring)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) goto err_giveback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) /* If xHC is dead take it down and return ALL URBs in xhci_hc_died() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) temp = readl(&xhci->op_regs->status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) if (temp == ~(u32)0 || xhci->xhc_state & XHCI_STATE_DYING) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) xhci_hc_died(xhci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) * check ring is not re-allocated since URB was enqueued. If it is, then
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) * make sure none of the ring related pointers in this URB private data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) * are touched, such as td_list, otherwise we overwrite freed data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) if (!td_on_ring(&urb_priv->td[0], ep_ring)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) xhci_err(xhci, "Canceled URB td not found on endpoint ring");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) for (i = urb_priv->num_tds_done; i < urb_priv->num_tds; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) td = &urb_priv->td[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) if (!list_empty(&td->cancelled_td_list))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) list_del_init(&td->cancelled_td_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) goto err_giveback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) if (xhci->xhc_state & XHCI_STATE_HALTED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) "HC halted, freeing TD manually.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) for (i = urb_priv->num_tds_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) i < urb_priv->num_tds;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) td = &urb_priv->td[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) if (!list_empty(&td->td_list))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) list_del_init(&td->td_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) if (!list_empty(&td->cancelled_td_list))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) list_del_init(&td->cancelled_td_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) goto err_giveback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) i = urb_priv->num_tds_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) if (i < urb_priv->num_tds)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) "Cancel URB %p, dev %s, ep 0x%x, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) "starting at offset 0x%llx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) urb, urb->dev->devpath,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) urb->ep->desc.bEndpointAddress,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) (unsigned long long) xhci_trb_virt_to_dma(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) urb_priv->td[i].start_seg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) urb_priv->td[i].first_trb));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) for (; i < urb_priv->num_tds; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) td = &urb_priv->td[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) /* TD can already be on cancelled list if ep halted on it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) if (list_empty(&td->cancelled_td_list)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) td->cancel_status = TD_DIRTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) list_add_tail(&td->cancelled_td_list,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) &ep->cancelled_td_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) /* Queue a stop endpoint command, but only if this is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) * the first cancellation to be handled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) if (!(ep->ep_state & EP_STOP_CMD_PENDING)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) command = xhci_alloc_command(xhci, false, GFP_ATOMIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) if (!command) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) ep->ep_state |= EP_STOP_CMD_PENDING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) ep->stop_cmd_timer.expires = jiffies +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) XHCI_STOP_EP_CMD_TIMEOUT * HZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) add_timer(&ep->stop_cmd_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) xhci_queue_stop_endpoint(xhci, command, urb->dev->slot_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) ep_index, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) xhci_ring_cmd_db(xhci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) spin_unlock_irqrestore(&xhci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) err_giveback:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) if (urb_priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) xhci_urb_free_priv(urb_priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) usb_hcd_unlink_urb_from_ep(hcd, urb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) spin_unlock_irqrestore(&xhci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) usb_hcd_giveback_urb(hcd, urb, -ESHUTDOWN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) /* Drop an endpoint from a new bandwidth configuration for this device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) * Only one call to this function is allowed per endpoint before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) * check_bandwidth() or reset_bandwidth() must be called.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) * add the endpoint to the schedule with possibly new parameters denoted by a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) * different endpoint descriptor in usb_host_endpoint.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) * not allowed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) * The USB core will not allow URBs to be queued to an endpoint that is being
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) * disabled, so there's no need for mutual exclusion to protect
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) * the xhci->devs[slot_id] structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) struct usb_host_endpoint *ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) struct xhci_hcd *xhci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) struct xhci_container_ctx *in_ctx, *out_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) struct xhci_input_control_ctx *ctrl_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) unsigned int ep_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) struct xhci_ep_ctx *ep_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) u32 drop_flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) u32 new_add_flags, new_drop_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) ret = xhci_check_args(hcd, udev, ep, 1, true, __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) if (ret <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) xhci = hcd_to_xhci(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) if (xhci->xhc_state & XHCI_STATE_DYING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) drop_flag = xhci_get_endpoint_flag(&ep->desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) if (drop_flag == SLOT_FLAG || drop_flag == EP0_FLAG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) xhci_dbg(xhci, "xHCI %s - can't drop slot or ep 0 %#x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) __func__, drop_flag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) in_ctx = xhci->devs[udev->slot_id]->in_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) out_ctx = xhci->devs[udev->slot_id]->out_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) if (!ctrl_ctx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) ep_index = xhci_get_endpoint_index(&ep->desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) /* If the HC already knows the endpoint is disabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) * or the HCD has noted it is disabled, ignore this request
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) if ((GET_EP_CTX_STATE(ep_ctx) == EP_STATE_DISABLED) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) le32_to_cpu(ctrl_ctx->drop_flags) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) xhci_get_endpoint_flag(&ep->desc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) /* Do not warn when called after a usb_device_reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) if (xhci->devs[udev->slot_id]->eps[ep_index].ring != NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) xhci_warn(xhci, "xHCI %s called with disabled ep %p\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) __func__, ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) ctrl_ctx->drop_flags |= cpu_to_le32(drop_flag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) new_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) ctrl_ctx->add_flags &= cpu_to_le32(~drop_flag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) new_add_flags = le32_to_cpu(ctrl_ctx->add_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) xhci_debugfs_remove_endpoint(xhci, xhci->devs[udev->slot_id], ep_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) xhci_endpoint_zero(xhci, xhci->devs[udev->slot_id], ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) xhci_dbg(xhci, "drop ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) (unsigned int) ep->desc.bEndpointAddress,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) udev->slot_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) (unsigned int) new_drop_flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) (unsigned int) new_add_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) EXPORT_SYMBOL_GPL(xhci_drop_endpoint);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) /* Add an endpoint to a new possible bandwidth configuration for this device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) * Only one call to this function is allowed per endpoint before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) * check_bandwidth() or reset_bandwidth() must be called.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) * add the endpoint to the schedule with possibly new parameters denoted by a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) * different endpoint descriptor in usb_host_endpoint.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) * not allowed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) * The USB core will not allow URBs to be queued to an endpoint until the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) * configuration or alt setting is installed in the device, so there's no need
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) * for mutual exclusion to protect the xhci->devs[slot_id] structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) struct usb_host_endpoint *ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) struct xhci_hcd *xhci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) struct xhci_container_ctx *in_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) unsigned int ep_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) struct xhci_input_control_ctx *ctrl_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) struct xhci_ep_ctx *ep_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) u32 added_ctxs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) u32 new_add_flags, new_drop_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) struct xhci_virt_device *virt_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) ret = xhci_check_args(hcd, udev, ep, 1, true, __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) if (ret <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) /* So we won't queue a reset ep command for a root hub */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) ep->hcpriv = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) xhci = hcd_to_xhci(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) if (xhci->xhc_state & XHCI_STATE_DYING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) added_ctxs = xhci_get_endpoint_flag(&ep->desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) if (added_ctxs == SLOT_FLAG || added_ctxs == EP0_FLAG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) /* FIXME when we have to issue an evaluate endpoint command to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) * deal with ep0 max packet size changing once we get the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) * descriptors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) xhci_dbg(xhci, "xHCI %s - can't add slot or ep 0 %#x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) __func__, added_ctxs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) virt_dev = xhci->devs[udev->slot_id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) in_ctx = virt_dev->in_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) if (!ctrl_ctx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) ep_index = xhci_get_endpoint_index(&ep->desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) /* If this endpoint is already in use, and the upper layers are trying
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) * to add it again without dropping it, reject the addition.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) if (virt_dev->eps[ep_index].ring &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) !(le32_to_cpu(ctrl_ctx->drop_flags) & added_ctxs)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) xhci_warn(xhci, "Trying to add endpoint 0x%x "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) "without dropping it.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) (unsigned int) ep->desc.bEndpointAddress);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) /* If the HCD has already noted the endpoint is enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) * ignore this request.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) if (le32_to_cpu(ctrl_ctx->add_flags) & added_ctxs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) xhci_warn(xhci, "xHCI %s called with enabled ep %p\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) __func__, ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) * Configuration and alternate setting changes must be done in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) * process context, not interrupt context (or so documenation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) * for usb_set_interface() and usb_set_configuration() claim).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) if (xhci_endpoint_init(xhci, virt_dev, udev, ep, GFP_NOIO) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) dev_dbg(&udev->dev, "%s - could not initialize ep %#x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) __func__, ep->desc.bEndpointAddress);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) ctrl_ctx->add_flags |= cpu_to_le32(added_ctxs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) new_add_flags = le32_to_cpu(ctrl_ctx->add_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) /* If xhci_endpoint_disable() was called for this endpoint, but the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) * xHC hasn't been notified yet through the check_bandwidth() call,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) * this re-adds a new state for the endpoint from the new endpoint
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) * descriptors. We must drop and re-add this endpoint, so we leave the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) * drop flags alone.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) new_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) /* Store the usb_device pointer for later use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) ep->hcpriv = udev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, ep_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) trace_xhci_add_endpoint(ep_ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) xhci_dbg(xhci, "add ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) (unsigned int) ep->desc.bEndpointAddress,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) udev->slot_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) (unsigned int) new_drop_flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) (unsigned int) new_add_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) EXPORT_SYMBOL_GPL(xhci_add_endpoint);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) static void xhci_zero_in_ctx(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) struct xhci_input_control_ctx *ctrl_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) struct xhci_ep_ctx *ep_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) struct xhci_slot_ctx *slot_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) if (!ctrl_ctx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) /* When a device's add flag and drop flag are zero, any subsequent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) * configure endpoint command will leave that endpoint's state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) * untouched. Make sure we don't leave any old state in the input
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) * endpoint contexts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) ctrl_ctx->drop_flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) ctrl_ctx->add_flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) /* Endpoint 0 is always valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) for (i = 1; i < 31; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) ep_ctx->ep_info = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) ep_ctx->ep_info2 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) ep_ctx->deq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) ep_ctx->tx_info = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) static int xhci_configure_endpoint_result(struct xhci_hcd *xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) struct usb_device *udev, u32 *cmd_status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) switch (*cmd_status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) case COMP_COMMAND_ABORTED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) case COMP_COMMAND_RING_STOPPED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) xhci_warn(xhci, "Timeout while waiting for configure endpoint command\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) ret = -ETIME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) case COMP_RESOURCE_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) dev_warn(&udev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) "Not enough host controller resources for new device state.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) /* FIXME: can we allocate more resources for the HC? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) case COMP_BANDWIDTH_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) case COMP_SECONDARY_BANDWIDTH_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) dev_warn(&udev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) "Not enough bandwidth for new device state.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) ret = -ENOSPC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) /* FIXME: can we go back to the old state? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) case COMP_TRB_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) /* the HCD set up something wrong */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) dev_warn(&udev->dev, "ERROR: Endpoint drop flag = 0, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) "add flag = 1, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) "and endpoint is not disabled.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) case COMP_INCOMPATIBLE_DEVICE_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) dev_warn(&udev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) "ERROR: Incompatible device for endpoint configure command.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) case COMP_SUCCESS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) "Successful Endpoint Configure command");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) xhci_err(xhci, "ERROR: unexpected command completion code 0x%x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) *cmd_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) static int xhci_evaluate_context_result(struct xhci_hcd *xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) struct usb_device *udev, u32 *cmd_status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) switch (*cmd_status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) case COMP_COMMAND_ABORTED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) case COMP_COMMAND_RING_STOPPED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) xhci_warn(xhci, "Timeout while waiting for evaluate context command\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) ret = -ETIME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) case COMP_PARAMETER_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) dev_warn(&udev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) "WARN: xHCI driver setup invalid evaluate context command.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) case COMP_SLOT_NOT_ENABLED_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) dev_warn(&udev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) "WARN: slot not enabled for evaluate context command.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) case COMP_CONTEXT_STATE_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) dev_warn(&udev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) "WARN: invalid context state for evaluate context command.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) case COMP_INCOMPATIBLE_DEVICE_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) dev_warn(&udev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) "ERROR: Incompatible device for evaluate context command.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) case COMP_MAX_EXIT_LATENCY_TOO_LARGE_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) /* Max Exit Latency too large error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) dev_warn(&udev->dev, "WARN: Max Exit Latency too large\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) case COMP_SUCCESS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) "Successful evaluate context command");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) xhci_err(xhci, "ERROR: unexpected command completion code 0x%x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) *cmd_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) static u32 xhci_count_num_new_endpoints(struct xhci_hcd *xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) struct xhci_input_control_ctx *ctrl_ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) u32 valid_add_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) u32 valid_drop_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) /* Ignore the slot flag (bit 0), and the default control endpoint flag
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) * (bit 1). The default control endpoint is added during the Address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) * Device command and is never removed until the slot is disabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) valid_add_flags = le32_to_cpu(ctrl_ctx->add_flags) >> 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) valid_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags) >> 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) /* Use hweight32 to count the number of ones in the add flags, or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) * number of endpoints added. Don't count endpoints that are changed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) * (both added and dropped).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) return hweight32(valid_add_flags) -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) hweight32(valid_add_flags & valid_drop_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) static unsigned int xhci_count_num_dropped_endpoints(struct xhci_hcd *xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) struct xhci_input_control_ctx *ctrl_ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) u32 valid_add_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) u32 valid_drop_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) valid_add_flags = le32_to_cpu(ctrl_ctx->add_flags) >> 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) valid_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags) >> 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) return hweight32(valid_drop_flags) -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) hweight32(valid_add_flags & valid_drop_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) * We need to reserve the new number of endpoints before the configure endpoint
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) * command completes. We can't subtract the dropped endpoints from the number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) * of active endpoints until the command completes because we can oversubscribe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) * the host in this case:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) * - the first configure endpoint command drops more endpoints than it adds
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) * - a second configure endpoint command that adds more endpoints is queued
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) * - the first configure endpoint command fails, so the config is unchanged
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) * - the second command may succeed, even though there isn't enough resources
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) * Must be called with xhci->lock held.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) static int xhci_reserve_host_resources(struct xhci_hcd *xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) struct xhci_input_control_ctx *ctrl_ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) u32 added_eps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) added_eps = xhci_count_num_new_endpoints(xhci, ctrl_ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) if (xhci->num_active_eps + added_eps > xhci->limit_active_eps) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) "Not enough ep ctxs: "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) "%u active, need to add %u, limit is %u.",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) xhci->num_active_eps, added_eps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) xhci->limit_active_eps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) xhci->num_active_eps += added_eps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) "Adding %u ep ctxs, %u now active.", added_eps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) xhci->num_active_eps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) * The configure endpoint was failed by the xHC for some other reason, so we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) * need to revert the resources that failed configuration would have used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) * Must be called with xhci->lock held.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) static void xhci_free_host_resources(struct xhci_hcd *xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) struct xhci_input_control_ctx *ctrl_ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) u32 num_failed_eps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) num_failed_eps = xhci_count_num_new_endpoints(xhci, ctrl_ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) xhci->num_active_eps -= num_failed_eps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) "Removing %u failed ep ctxs, %u now active.",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) num_failed_eps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) xhci->num_active_eps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) * Now that the command has completed, clean up the active endpoint count by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) * subtracting out the endpoints that were dropped (but not changed).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) * Must be called with xhci->lock held.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) static void xhci_finish_resource_reservation(struct xhci_hcd *xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) struct xhci_input_control_ctx *ctrl_ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) u32 num_dropped_eps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) num_dropped_eps = xhci_count_num_dropped_endpoints(xhci, ctrl_ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) xhci->num_active_eps -= num_dropped_eps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) if (num_dropped_eps)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) "Removing %u dropped ep ctxs, %u now active.",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) num_dropped_eps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) xhci->num_active_eps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) static unsigned int xhci_get_block_size(struct usb_device *udev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) switch (udev->speed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) case USB_SPEED_LOW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) case USB_SPEED_FULL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) return FS_BLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) case USB_SPEED_HIGH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) return HS_BLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) case USB_SPEED_SUPER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) case USB_SPEED_SUPER_PLUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) return SS_BLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) case USB_SPEED_UNKNOWN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) case USB_SPEED_WIRELESS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) /* Should never happen */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) static unsigned int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) xhci_get_largest_overhead(struct xhci_interval_bw *interval_bw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) if (interval_bw->overhead[LS_OVERHEAD_TYPE])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) return LS_OVERHEAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) if (interval_bw->overhead[FS_OVERHEAD_TYPE])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) return FS_OVERHEAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) return HS_OVERHEAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) /* If we are changing a LS/FS device under a HS hub,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) * make sure (if we are activating a new TT) that the HS bus has enough
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) * bandwidth for this new TT.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) static int xhci_check_tt_bw_table(struct xhci_hcd *xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) struct xhci_virt_device *virt_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) int old_active_eps)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) struct xhci_interval_bw_table *bw_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) struct xhci_tt_bw_info *tt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) /* Find the bandwidth table for the root port this TT is attached to. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) bw_table = &xhci->rh_bw[virt_dev->real_port - 1].bw_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) tt_info = virt_dev->tt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) /* If this TT already had active endpoints, the bandwidth for this TT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) * has already been added. Removing all periodic endpoints (and thus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) * making the TT enactive) will only decrease the bandwidth used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) if (old_active_eps)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) if (old_active_eps == 0 && tt_info->active_eps != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) if (bw_table->bw_used + TT_HS_OVERHEAD > HS_BW_LIMIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) /* Not sure why we would have no new active endpoints...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) * Maybe because of an Evaluate Context change for a hub update or a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) * control endpoint 0 max packet size change?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) * FIXME: skip the bandwidth calculation in that case.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) static int xhci_check_ss_bw(struct xhci_hcd *xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) struct xhci_virt_device *virt_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) unsigned int bw_reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) bw_reserved = DIV_ROUND_UP(SS_BW_RESERVED*SS_BW_LIMIT_IN, 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) if (virt_dev->bw_table->ss_bw_in > (SS_BW_LIMIT_IN - bw_reserved))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) bw_reserved = DIV_ROUND_UP(SS_BW_RESERVED*SS_BW_LIMIT_OUT, 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) if (virt_dev->bw_table->ss_bw_out > (SS_BW_LIMIT_OUT - bw_reserved))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) * This algorithm is a very conservative estimate of the worst-case scheduling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) * scenario for any one interval. The hardware dynamically schedules the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) * packets, so we can't tell which microframe could be the limiting factor in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) * the bandwidth scheduling. This only takes into account periodic endpoints.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) * Obviously, we can't solve an NP complete problem to find the minimum worst
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) * case scenario. Instead, we come up with an estimate that is no less than
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) * the worst case bandwidth used for any one microframe, but may be an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) * over-estimate.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) * We walk the requirements for each endpoint by interval, starting with the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) * smallest interval, and place packets in the schedule where there is only one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) * possible way to schedule packets for that interval. In order to simplify
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) * this algorithm, we record the largest max packet size for each interval, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) * assume all packets will be that size.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) * For interval 0, we obviously must schedule all packets for each interval.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) * The bandwidth for interval 0 is just the amount of data to be transmitted
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) * (the sum of all max ESIT payload sizes, plus any overhead per packet times
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) * the number of packets).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) * For interval 1, we have two possible microframes to schedule those packets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) * in. For this algorithm, if we can schedule the same number of packets for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) * each possible scheduling opportunity (each microframe), we will do so. The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) * remaining number of packets will be saved to be transmitted in the gaps in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) * the next interval's scheduling sequence.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) * As we move those remaining packets to be scheduled with interval 2 packets,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) * we have to double the number of remaining packets to transmit. This is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) * because the intervals are actually powers of 2, and we would be transmitting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) * the previous interval's packets twice in this interval. We also have to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) * sure that when we look at the largest max packet size for this interval, we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) * also look at the largest max packet size for the remaining packets and take
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) * the greater of the two.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) * The algorithm continues to evenly distribute packets in each scheduling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) * opportunity, and push the remaining packets out, until we get to the last
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) * interval. Then those packets and their associated overhead are just added
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) * to the bandwidth used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) static int xhci_check_bw_table(struct xhci_hcd *xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) struct xhci_virt_device *virt_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) int old_active_eps)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) unsigned int bw_reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) unsigned int max_bandwidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) unsigned int bw_used;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) unsigned int block_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) struct xhci_interval_bw_table *bw_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) unsigned int packet_size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) unsigned int overhead = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) unsigned int packets_transmitted = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) unsigned int packets_remaining = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) if (virt_dev->udev->speed >= USB_SPEED_SUPER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) return xhci_check_ss_bw(xhci, virt_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) if (virt_dev->udev->speed == USB_SPEED_HIGH) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) max_bandwidth = HS_BW_LIMIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) /* Convert percent of bus BW reserved to blocks reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) bw_reserved = DIV_ROUND_UP(HS_BW_RESERVED * max_bandwidth, 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) max_bandwidth = FS_BW_LIMIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) bw_reserved = DIV_ROUND_UP(FS_BW_RESERVED * max_bandwidth, 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) bw_table = virt_dev->bw_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) /* We need to translate the max packet size and max ESIT payloads into
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) * the units the hardware uses.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) block_size = xhci_get_block_size(virt_dev->udev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) /* If we are manipulating a LS/FS device under a HS hub, double check
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) * that the HS bus has enough bandwidth if we are activing a new TT.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) if (virt_dev->tt_info) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) "Recalculating BW for rootport %u",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) virt_dev->real_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) if (xhci_check_tt_bw_table(xhci, virt_dev, old_active_eps)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) xhci_warn(xhci, "Not enough bandwidth on HS bus for "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) "newly activated TT.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) "Recalculating BW for TT slot %u port %u",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) virt_dev->tt_info->slot_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) virt_dev->tt_info->ttport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) "Recalculating BW for rootport %u",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) virt_dev->real_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) /* Add in how much bandwidth will be used for interval zero, or the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) * rounded max ESIT payload + number of packets * largest overhead.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) bw_used = DIV_ROUND_UP(bw_table->interval0_esit_payload, block_size) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) bw_table->interval_bw[0].num_packets *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) xhci_get_largest_overhead(&bw_table->interval_bw[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) for (i = 1; i < XHCI_MAX_INTERVAL; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) unsigned int bw_added;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) unsigned int largest_mps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) unsigned int interval_overhead;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) * How many packets could we transmit in this interval?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) * If packets didn't fit in the previous interval, we will need
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) * to transmit that many packets twice within this interval.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) packets_remaining = 2 * packets_remaining +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) bw_table->interval_bw[i].num_packets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) /* Find the largest max packet size of this or the previous
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) * interval.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) if (list_empty(&bw_table->interval_bw[i].endpoints))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) largest_mps = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) struct xhci_virt_ep *virt_ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) struct list_head *ep_entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) ep_entry = bw_table->interval_bw[i].endpoints.next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) virt_ep = list_entry(ep_entry,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) struct xhci_virt_ep, bw_endpoint_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) /* Convert to blocks, rounding up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) largest_mps = DIV_ROUND_UP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) virt_ep->bw_info.max_packet_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) block_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) if (largest_mps > packet_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) packet_size = largest_mps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) /* Use the larger overhead of this or the previous interval. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) interval_overhead = xhci_get_largest_overhead(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) &bw_table->interval_bw[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) if (interval_overhead > overhead)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) overhead = interval_overhead;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) /* How many packets can we evenly distribute across
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) * (1 << (i + 1)) possible scheduling opportunities?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) packets_transmitted = packets_remaining >> (i + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) /* Add in the bandwidth used for those scheduled packets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) bw_added = packets_transmitted * (overhead + packet_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) /* How many packets do we have remaining to transmit? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) packets_remaining = packets_remaining % (1 << (i + 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) /* What largest max packet size should those packets have? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) /* If we've transmitted all packets, don't carry over the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) * largest packet size.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) if (packets_remaining == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) packet_size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) overhead = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) } else if (packets_transmitted > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) /* Otherwise if we do have remaining packets, and we've
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) * scheduled some packets in this interval, take the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) * largest max packet size from endpoints with this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) * interval.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) packet_size = largest_mps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) overhead = interval_overhead;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) /* Otherwise carry over packet_size and overhead from the last
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) * time we had a remainder.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) bw_used += bw_added;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) if (bw_used > max_bandwidth) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) xhci_warn(xhci, "Not enough bandwidth. "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) "Proposed: %u, Max: %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) bw_used, max_bandwidth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) * Ok, we know we have some packets left over after even-handedly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) * scheduling interval 15. We don't know which microframes they will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) * fit into, so we over-schedule and say they will be scheduled every
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) * microframe.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) if (packets_remaining > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) bw_used += overhead + packet_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) if (!virt_dev->tt_info && virt_dev->udev->speed == USB_SPEED_HIGH) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) unsigned int port_index = virt_dev->real_port - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) /* OK, we're manipulating a HS device attached to a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) * root port bandwidth domain. Include the number of active TTs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) * in the bandwidth used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) bw_used += TT_HS_OVERHEAD *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) xhci->rh_bw[port_index].num_active_tts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) "Final bandwidth: %u, Limit: %u, Reserved: %u, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) "Available: %u " "percent",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) bw_used, max_bandwidth, bw_reserved,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) (max_bandwidth - bw_used - bw_reserved) * 100 /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) max_bandwidth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) bw_used += bw_reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) if (bw_used > max_bandwidth) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) xhci_warn(xhci, "Not enough bandwidth. Proposed: %u, Max: %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) bw_used, max_bandwidth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) bw_table->bw_used = bw_used;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) static bool xhci_is_async_ep(unsigned int ep_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483) return (ep_type != ISOC_OUT_EP && ep_type != INT_OUT_EP &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) ep_type != ISOC_IN_EP &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) ep_type != INT_IN_EP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) static bool xhci_is_sync_in_ep(unsigned int ep_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490) return (ep_type == ISOC_IN_EP || ep_type == INT_IN_EP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) static unsigned int xhci_get_ss_bw_consumed(struct xhci_bw_info *ep_bw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) unsigned int mps = DIV_ROUND_UP(ep_bw->max_packet_size, SS_BLOCK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497) if (ep_bw->ep_interval == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) return SS_OVERHEAD_BURST +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) (ep_bw->mult * ep_bw->num_packets *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) (SS_OVERHEAD + mps));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501) return DIV_ROUND_UP(ep_bw->mult * ep_bw->num_packets *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) (SS_OVERHEAD + mps + SS_OVERHEAD_BURST),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) 1 << ep_bw->ep_interval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507) static void xhci_drop_ep_from_interval_table(struct xhci_hcd *xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) struct xhci_bw_info *ep_bw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) struct xhci_interval_bw_table *bw_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) struct usb_device *udev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) struct xhci_virt_ep *virt_ep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) struct xhci_tt_bw_info *tt_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514) struct xhci_interval_bw *interval_bw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) int normalized_interval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517) if (xhci_is_async_ep(ep_bw->type))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520) if (udev->speed >= USB_SPEED_SUPER) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) if (xhci_is_sync_in_ep(ep_bw->type))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) xhci->devs[udev->slot_id]->bw_table->ss_bw_in -=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) xhci_get_ss_bw_consumed(ep_bw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) xhci->devs[udev->slot_id]->bw_table->ss_bw_out -=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526) xhci_get_ss_bw_consumed(ep_bw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530) /* SuperSpeed endpoints never get added to intervals in the table, so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531) * this check is only valid for HS/FS/LS devices.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) if (list_empty(&virt_ep->bw_endpoint_list))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535) /* For LS/FS devices, we need to translate the interval expressed in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) * microframes to frames.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538) if (udev->speed == USB_SPEED_HIGH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539) normalized_interval = ep_bw->ep_interval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) normalized_interval = ep_bw->ep_interval - 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543) if (normalized_interval == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) bw_table->interval0_esit_payload -= ep_bw->max_esit_payload;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545) interval_bw = &bw_table->interval_bw[normalized_interval];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546) interval_bw->num_packets -= ep_bw->num_packets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547) switch (udev->speed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) case USB_SPEED_LOW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549) interval_bw->overhead[LS_OVERHEAD_TYPE] -= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551) case USB_SPEED_FULL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552) interval_bw->overhead[FS_OVERHEAD_TYPE] -= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554) case USB_SPEED_HIGH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555) interval_bw->overhead[HS_OVERHEAD_TYPE] -= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557) case USB_SPEED_SUPER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558) case USB_SPEED_SUPER_PLUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559) case USB_SPEED_UNKNOWN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560) case USB_SPEED_WIRELESS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561) /* Should never happen because only LS/FS/HS endpoints will get
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562) * added to the endpoint list.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566) if (tt_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567) tt_info->active_eps -= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568) list_del_init(&virt_ep->bw_endpoint_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571) static void xhci_add_ep_to_interval_table(struct xhci_hcd *xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572) struct xhci_bw_info *ep_bw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) struct xhci_interval_bw_table *bw_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574) struct usb_device *udev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575) struct xhci_virt_ep *virt_ep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576) struct xhci_tt_bw_info *tt_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578) struct xhci_interval_bw *interval_bw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579) struct xhci_virt_ep *smaller_ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580) int normalized_interval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582) if (xhci_is_async_ep(ep_bw->type))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) if (udev->speed == USB_SPEED_SUPER) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586) if (xhci_is_sync_in_ep(ep_bw->type))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587) xhci->devs[udev->slot_id]->bw_table->ss_bw_in +=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588) xhci_get_ss_bw_consumed(ep_bw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590) xhci->devs[udev->slot_id]->bw_table->ss_bw_out +=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591) xhci_get_ss_bw_consumed(ep_bw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595) /* For LS/FS devices, we need to translate the interval expressed in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596) * microframes to frames.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598) if (udev->speed == USB_SPEED_HIGH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599) normalized_interval = ep_bw->ep_interval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601) normalized_interval = ep_bw->ep_interval - 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603) if (normalized_interval == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604) bw_table->interval0_esit_payload += ep_bw->max_esit_payload;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605) interval_bw = &bw_table->interval_bw[normalized_interval];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606) interval_bw->num_packets += ep_bw->num_packets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607) switch (udev->speed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608) case USB_SPEED_LOW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609) interval_bw->overhead[LS_OVERHEAD_TYPE] += 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611) case USB_SPEED_FULL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612) interval_bw->overhead[FS_OVERHEAD_TYPE] += 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614) case USB_SPEED_HIGH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615) interval_bw->overhead[HS_OVERHEAD_TYPE] += 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617) case USB_SPEED_SUPER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618) case USB_SPEED_SUPER_PLUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619) case USB_SPEED_UNKNOWN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620) case USB_SPEED_WIRELESS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621) /* Should never happen because only LS/FS/HS endpoints will get
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622) * added to the endpoint list.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627) if (tt_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628) tt_info->active_eps += 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629) /* Insert the endpoint into the list, largest max packet size first. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630) list_for_each_entry(smaller_ep, &interval_bw->endpoints,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631) bw_endpoint_list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632) if (ep_bw->max_packet_size >=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633) smaller_ep->bw_info.max_packet_size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634) /* Add the new ep before the smaller endpoint */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635) list_add_tail(&virt_ep->bw_endpoint_list,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636) &smaller_ep->bw_endpoint_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640) /* Add the new endpoint at the end of the list. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641) list_add_tail(&virt_ep->bw_endpoint_list,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642) &interval_bw->endpoints);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645) void xhci_update_tt_active_eps(struct xhci_hcd *xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646) struct xhci_virt_device *virt_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647) int old_active_eps)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649) struct xhci_root_port_bw_info *rh_bw_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650) if (!virt_dev->tt_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653) rh_bw_info = &xhci->rh_bw[virt_dev->real_port - 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654) if (old_active_eps == 0 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655) virt_dev->tt_info->active_eps != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656) rh_bw_info->num_active_tts += 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657) rh_bw_info->bw_table.bw_used += TT_HS_OVERHEAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658) } else if (old_active_eps != 0 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659) virt_dev->tt_info->active_eps == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660) rh_bw_info->num_active_tts -= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661) rh_bw_info->bw_table.bw_used -= TT_HS_OVERHEAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665) static int xhci_reserve_bandwidth(struct xhci_hcd *xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666) struct xhci_virt_device *virt_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667) struct xhci_container_ctx *in_ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669) struct xhci_bw_info ep_bw_info[31];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671) struct xhci_input_control_ctx *ctrl_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672) int old_active_eps = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674) if (virt_dev->tt_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675) old_active_eps = virt_dev->tt_info->active_eps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2677) ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2678) if (!ctrl_ctx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2679) xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2680) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2681) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2682) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2684) for (i = 0; i < 31; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2685) if (!EP_IS_ADDED(ctrl_ctx, i) && !EP_IS_DROPPED(ctrl_ctx, i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2686) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2688) /* Make a copy of the BW info in case we need to revert this */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2689) memcpy(&ep_bw_info[i], &virt_dev->eps[i].bw_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2690) sizeof(ep_bw_info[i]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2691) /* Drop the endpoint from the interval table if the endpoint is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2692) * being dropped or changed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2693) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2694) if (EP_IS_DROPPED(ctrl_ctx, i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2695) xhci_drop_ep_from_interval_table(xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2696) &virt_dev->eps[i].bw_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2697) virt_dev->bw_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2698) virt_dev->udev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2699) &virt_dev->eps[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2700) virt_dev->tt_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2701) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2702) /* Overwrite the information stored in the endpoints' bw_info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2703) xhci_update_bw_info(xhci, virt_dev->in_ctx, ctrl_ctx, virt_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2704) for (i = 0; i < 31; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2705) /* Add any changed or added endpoints to the interval table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2706) if (EP_IS_ADDED(ctrl_ctx, i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2707) xhci_add_ep_to_interval_table(xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2708) &virt_dev->eps[i].bw_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2709) virt_dev->bw_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2710) virt_dev->udev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2711) &virt_dev->eps[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2712) virt_dev->tt_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2713) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2715) if (!xhci_check_bw_table(xhci, virt_dev, old_active_eps)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2716) /* Ok, this fits in the bandwidth we have.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2717) * Update the number of active TTs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2718) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2719) xhci_update_tt_active_eps(xhci, virt_dev, old_active_eps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2720) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2721) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2723) /* We don't have enough bandwidth for this, revert the stored info. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2724) for (i = 0; i < 31; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2725) if (!EP_IS_ADDED(ctrl_ctx, i) && !EP_IS_DROPPED(ctrl_ctx, i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2726) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2728) /* Drop the new copies of any added or changed endpoints from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2729) * the interval table.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2730) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2731) if (EP_IS_ADDED(ctrl_ctx, i)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2732) xhci_drop_ep_from_interval_table(xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2733) &virt_dev->eps[i].bw_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2734) virt_dev->bw_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2735) virt_dev->udev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2736) &virt_dev->eps[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2737) virt_dev->tt_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2738) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2739) /* Revert the endpoint back to its old information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2740) memcpy(&virt_dev->eps[i].bw_info, &ep_bw_info[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2741) sizeof(ep_bw_info[i]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2742) /* Add any changed or dropped endpoints back into the table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2743) if (EP_IS_DROPPED(ctrl_ctx, i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2744) xhci_add_ep_to_interval_table(xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2745) &virt_dev->eps[i].bw_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2746) virt_dev->bw_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2747) virt_dev->udev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2748) &virt_dev->eps[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2749) virt_dev->tt_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2750) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2751) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2752) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2755) /* Issue a configure endpoint command or evaluate context command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2756) * and wait for it to finish.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2757) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2758) static int xhci_configure_endpoint(struct xhci_hcd *xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2759) struct usb_device *udev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2760) struct xhci_command *command,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2761) bool ctx_change, bool must_succeed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2762) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2763) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2764) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2765) struct xhci_input_control_ctx *ctrl_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2766) struct xhci_virt_device *virt_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2767) struct xhci_slot_ctx *slot_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2769) if (!command)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2770) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2772) spin_lock_irqsave(&xhci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2774) if (xhci->xhc_state & XHCI_STATE_DYING) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2775) spin_unlock_irqrestore(&xhci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2776) return -ESHUTDOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2777) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2779) virt_dev = xhci->devs[udev->slot_id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2781) ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2782) if (!ctrl_ctx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2783) spin_unlock_irqrestore(&xhci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2784) xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2785) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2786) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2787) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2789) if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2790) xhci_reserve_host_resources(xhci, ctrl_ctx)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2791) spin_unlock_irqrestore(&xhci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2792) xhci_warn(xhci, "Not enough host resources, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2793) "active endpoint contexts = %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2794) xhci->num_active_eps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2795) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2796) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2797) if ((xhci->quirks & XHCI_SW_BW_CHECKING) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2798) xhci_reserve_bandwidth(xhci, virt_dev, command->in_ctx)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2799) if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2800) xhci_free_host_resources(xhci, ctrl_ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2801) spin_unlock_irqrestore(&xhci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2802) xhci_warn(xhci, "Not enough bandwidth\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2803) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2804) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2806) slot_ctx = xhci_get_slot_ctx(xhci, command->in_ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2808) trace_xhci_configure_endpoint_ctrl_ctx(ctrl_ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2809) trace_xhci_configure_endpoint(slot_ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2811) if (!ctx_change)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2812) ret = xhci_queue_configure_endpoint(xhci, command,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2813) command->in_ctx->dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2814) udev->slot_id, must_succeed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2815) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2816) ret = xhci_queue_evaluate_context(xhci, command,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2817) command->in_ctx->dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2818) udev->slot_id, must_succeed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2819) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2820) if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2821) xhci_free_host_resources(xhci, ctrl_ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2822) spin_unlock_irqrestore(&xhci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2823) xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2824) "FIXME allocate a new ring segment");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2825) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2826) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2827) xhci_ring_cmd_db(xhci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2828) spin_unlock_irqrestore(&xhci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2830) /* Wait for the configure endpoint command to complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2831) wait_for_completion(command->completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2833) if (!ctx_change)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2834) ret = xhci_configure_endpoint_result(xhci, udev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2835) &command->status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2836) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2837) ret = xhci_evaluate_context_result(xhci, udev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2838) &command->status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2840) if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2841) spin_lock_irqsave(&xhci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2842) /* If the command failed, remove the reserved resources.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2843) * Otherwise, clean up the estimate to include dropped eps.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2844) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2845) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2846) xhci_free_host_resources(xhci, ctrl_ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2847) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2848) xhci_finish_resource_reservation(xhci, ctrl_ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2849) spin_unlock_irqrestore(&xhci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2850) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2851) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2852) goto failed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2854) ret = xhci_vendor_sync_dev_ctx(xhci, udev->slot_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2855) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2856) xhci_warn(xhci, "sync device context failed, ret=%d", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2858) failed:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2859) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2860) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2862) static void xhci_check_bw_drop_ep_streams(struct xhci_hcd *xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2863) struct xhci_virt_device *vdev, int i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2864) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2865) struct xhci_virt_ep *ep = &vdev->eps[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2867) if (ep->ep_state & EP_HAS_STREAMS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2868) xhci_warn(xhci, "WARN: endpoint 0x%02x has streams on set_interface, freeing streams.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2869) xhci_get_endpoint_address(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2870) xhci_free_stream_info(xhci, ep->stream_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2871) ep->stream_info = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2872) ep->ep_state &= ~EP_HAS_STREAMS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2873) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2874) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2876) /* Called after one or more calls to xhci_add_endpoint() or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2877) * xhci_drop_endpoint(). If this call fails, the USB core is expected
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2878) * to call xhci_reset_bandwidth().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2879) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2880) * Since we are in the middle of changing either configuration or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2881) * installing a new alt setting, the USB core won't allow URBs to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2882) * enqueued for any endpoint on the old config or interface. Nothing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2883) * else should be touching the xhci->devs[slot_id] structure, so we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2884) * don't need to take the xhci->lock for manipulating that.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2885) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2886) int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2887) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2888) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2889) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2890) struct xhci_hcd *xhci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2891) struct xhci_virt_device *virt_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2892) struct xhci_input_control_ctx *ctrl_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2893) struct xhci_slot_ctx *slot_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2894) struct xhci_command *command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2896) ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2897) if (ret <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2898) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2899) xhci = hcd_to_xhci(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2900) if ((xhci->xhc_state & XHCI_STATE_DYING) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2901) (xhci->xhc_state & XHCI_STATE_REMOVING))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2902) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2904) xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2905) virt_dev = xhci->devs[udev->slot_id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2907) command = xhci_alloc_command(xhci, true, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2908) if (!command)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2909) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2911) command->in_ctx = virt_dev->in_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2913) /* See section 4.6.6 - A0 = 1; A1 = D0 = D1 = 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2914) ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2915) if (!ctrl_ctx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2916) xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2917) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2918) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2919) goto command_cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2920) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2921) ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2922) ctrl_ctx->add_flags &= cpu_to_le32(~EP0_FLAG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2923) ctrl_ctx->drop_flags &= cpu_to_le32(~(SLOT_FLAG | EP0_FLAG));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2925) /* Don't issue the command if there's no endpoints to update. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2926) if (ctrl_ctx->add_flags == cpu_to_le32(SLOT_FLAG) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2927) ctrl_ctx->drop_flags == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2928) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2929) goto command_cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2930) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2931) /* Fix up Context Entries field. Minimum value is EP0 == BIT(1). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2932) slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2933) for (i = 31; i >= 1; i--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2934) __le32 le32 = cpu_to_le32(BIT(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2936) if ((virt_dev->eps[i-1].ring && !(ctrl_ctx->drop_flags & le32))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2937) || (ctrl_ctx->add_flags & le32) || i == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2938) slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2939) slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2940) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2941) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2942) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2944) ret = xhci_configure_endpoint(xhci, udev, command,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2945) false, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2946) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2947) /* Callee should call reset_bandwidth() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2948) goto command_cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2950) /* Free any rings that were dropped, but not changed. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2951) for (i = 1; i < 31; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2952) if ((le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1))) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2953) !(le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1)))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2954) xhci_free_endpoint_ring(xhci, virt_dev, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2955) xhci_check_bw_drop_ep_streams(xhci, virt_dev, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2956) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2957) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2958) xhci_zero_in_ctx(xhci, virt_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2959) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2960) * Install any rings for completely new endpoints or changed endpoints,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2961) * and free any old rings from changed endpoints.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2962) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2963) for (i = 1; i < 31; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2964) if (!virt_dev->eps[i].new_ring)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2965) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2966) /* Only free the old ring if it exists.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2967) * It may not if this is the first add of an endpoint.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2968) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2969) if (virt_dev->eps[i].ring) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2970) xhci_free_endpoint_ring(xhci, virt_dev, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2971) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2972) xhci_check_bw_drop_ep_streams(xhci, virt_dev, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2973) virt_dev->eps[i].ring = virt_dev->eps[i].new_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2974) virt_dev->eps[i].new_ring = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2975) xhci_debugfs_create_endpoint(xhci, virt_dev, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2976) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2977) command_cleanup:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2978) kfree(command->completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2979) kfree(command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2981) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2982) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2983) EXPORT_SYMBOL_GPL(xhci_check_bandwidth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2985) void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2986) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2987) struct xhci_hcd *xhci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2988) struct xhci_virt_device *virt_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2989) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2991) ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2992) if (ret <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2993) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2994) xhci = hcd_to_xhci(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2996) xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2997) virt_dev = xhci->devs[udev->slot_id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2998) /* Free any rings allocated for added endpoints */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2999) for (i = 0; i < 31; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3000) if (virt_dev->eps[i].new_ring) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3001) xhci_debugfs_remove_endpoint(xhci, virt_dev, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3002) if (xhci_vendor_is_usb_offload_enabled(xhci, virt_dev, i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3003) xhci_vendor_free_transfer_ring(xhci, virt_dev, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3004) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3005) xhci_ring_free(xhci, virt_dev->eps[i].new_ring);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3007) virt_dev->eps[i].new_ring = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3008) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3009) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3010) xhci_zero_in_ctx(xhci, virt_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3011) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3012) EXPORT_SYMBOL_GPL(xhci_reset_bandwidth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3014) static void xhci_setup_input_ctx_for_config_ep(struct xhci_hcd *xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3015) struct xhci_container_ctx *in_ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3016) struct xhci_container_ctx *out_ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3017) struct xhci_input_control_ctx *ctrl_ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3018) u32 add_flags, u32 drop_flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3019) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3020) ctrl_ctx->add_flags = cpu_to_le32(add_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3021) ctrl_ctx->drop_flags = cpu_to_le32(drop_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3022) xhci_slot_copy(xhci, in_ctx, out_ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3023) ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3024) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3026) static void xhci_endpoint_disable(struct usb_hcd *hcd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3027) struct usb_host_endpoint *host_ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3028) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3029) struct xhci_hcd *xhci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3030) struct xhci_virt_device *vdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3031) struct xhci_virt_ep *ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3032) struct usb_device *udev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3033) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3034) unsigned int ep_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3036) xhci = hcd_to_xhci(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3037) rescan:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3038) spin_lock_irqsave(&xhci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3040) udev = (struct usb_device *)host_ep->hcpriv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3041) if (!udev || !udev->slot_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3042) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3044) vdev = xhci->devs[udev->slot_id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3045) if (!vdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3046) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3048) ep_index = xhci_get_endpoint_index(&host_ep->desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3049) ep = &vdev->eps[ep_index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3050) if (!ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3051) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3053) /* wait for hub_tt_work to finish clearing hub TT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3054) if (ep->ep_state & EP_CLEARING_TT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3055) spin_unlock_irqrestore(&xhci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3056) schedule_timeout_uninterruptible(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3057) goto rescan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3058) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3060) if (ep->ep_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3061) xhci_dbg(xhci, "endpoint disable with ep_state 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3062) ep->ep_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3063) done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3064) host_ep->hcpriv = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3065) spin_unlock_irqrestore(&xhci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3066) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3068) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3069) * Called after usb core issues a clear halt control message.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3070) * The host side of the halt should already be cleared by a reset endpoint
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3071) * command issued when the STALL event was received.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3072) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3073) * The reset endpoint command may only be issued to endpoints in the halted
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3074) * state. For software that wishes to reset the data toggle or sequence number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3075) * of an endpoint that isn't in the halted state this function will issue a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3076) * configure endpoint command with the Drop and Add bits set for the target
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3077) * endpoint. Refer to the additional note in xhci spcification section 4.6.8.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3078) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3080) static void xhci_endpoint_reset(struct usb_hcd *hcd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3081) struct usb_host_endpoint *host_ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3082) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3083) struct xhci_hcd *xhci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3084) struct usb_device *udev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3085) struct xhci_virt_device *vdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3086) struct xhci_virt_ep *ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3087) struct xhci_input_control_ctx *ctrl_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3088) struct xhci_command *stop_cmd, *cfg_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3089) unsigned int ep_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3090) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3091) u32 ep_flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3092) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3094) xhci = hcd_to_xhci(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3095) if (!host_ep->hcpriv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3096) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3097) udev = (struct usb_device *) host_ep->hcpriv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3098) vdev = xhci->devs[udev->slot_id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3100) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3101) * vdev may be lost due to xHC restore error and re-initialization
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3102) * during S3/S4 resume. A new vdev will be allocated later by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3103) * xhci_discover_or_reset_device()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3104) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3105) if (!udev->slot_id || !vdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3106) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3107) ep_index = xhci_get_endpoint_index(&host_ep->desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3108) ep = &vdev->eps[ep_index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3109) if (!ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3110) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3112) /* Bail out if toggle is already being cleared by a endpoint reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3113) spin_lock_irqsave(&xhci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3114) if (ep->ep_state & EP_HARD_CLEAR_TOGGLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3115) ep->ep_state &= ~EP_HARD_CLEAR_TOGGLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3116) spin_unlock_irqrestore(&xhci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3117) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3119) spin_unlock_irqrestore(&xhci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3120) /* Only interrupt and bulk ep's use data toggle, USB2 spec 5.5.4-> */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3121) if (usb_endpoint_xfer_control(&host_ep->desc) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3122) usb_endpoint_xfer_isoc(&host_ep->desc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3123) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3125) ep_flag = xhci_get_endpoint_flag(&host_ep->desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3127) if (ep_flag == SLOT_FLAG || ep_flag == EP0_FLAG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3128) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3130) stop_cmd = xhci_alloc_command(xhci, true, GFP_NOWAIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3131) if (!stop_cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3132) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3134) cfg_cmd = xhci_alloc_command_with_ctx(xhci, true, GFP_NOWAIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3135) if (!cfg_cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3136) goto cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3138) spin_lock_irqsave(&xhci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3140) /* block queuing new trbs and ringing ep doorbell */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3141) ep->ep_state |= EP_SOFT_CLEAR_TOGGLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3143) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3144) * Make sure endpoint ring is empty before resetting the toggle/seq.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3145) * Driver is required to synchronously cancel all transfer request.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3146) * Stop the endpoint to force xHC to update the output context
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3147) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3149) if (!list_empty(&ep->ring->td_list)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3150) dev_err(&udev->dev, "EP not empty, refuse reset\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3151) spin_unlock_irqrestore(&xhci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3152) xhci_free_command(xhci, cfg_cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3153) goto cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3156) err = xhci_queue_stop_endpoint(xhci, stop_cmd, udev->slot_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3157) ep_index, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3158) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3159) spin_unlock_irqrestore(&xhci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3160) xhci_free_command(xhci, cfg_cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3161) xhci_dbg(xhci, "%s: Failed to queue stop ep command, %d ",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3162) __func__, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3163) goto cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3166) xhci_ring_cmd_db(xhci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3167) spin_unlock_irqrestore(&xhci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3169) wait_for_completion(stop_cmd->completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3171) err = xhci_vendor_sync_dev_ctx(xhci, udev->slot_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3172) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3173) xhci_warn(xhci, "%s: Failed to sync device context failed, err=%d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3174) __func__, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3175) goto cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3178) spin_lock_irqsave(&xhci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3180) /* config ep command clears toggle if add and drop ep flags are set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3181) ctrl_ctx = xhci_get_input_control_ctx(cfg_cmd->in_ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3182) if (!ctrl_ctx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3183) spin_unlock_irqrestore(&xhci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3184) xhci_free_command(xhci, cfg_cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3185) xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3186) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3187) goto cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3190) xhci_setup_input_ctx_for_config_ep(xhci, cfg_cmd->in_ctx, vdev->out_ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3191) ctrl_ctx, ep_flag, ep_flag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3192) xhci_endpoint_copy(xhci, cfg_cmd->in_ctx, vdev->out_ctx, ep_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3194) err = xhci_queue_configure_endpoint(xhci, cfg_cmd, cfg_cmd->in_ctx->dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3195) udev->slot_id, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3196) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3197) spin_unlock_irqrestore(&xhci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3198) xhci_free_command(xhci, cfg_cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3199) xhci_dbg(xhci, "%s: Failed to queue config ep command, %d ",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3200) __func__, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3201) goto cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3204) xhci_ring_cmd_db(xhci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3205) spin_unlock_irqrestore(&xhci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3207) wait_for_completion(cfg_cmd->completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3209) err = xhci_vendor_sync_dev_ctx(xhci, udev->slot_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3210) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3211) xhci_warn(xhci, "%s: Failed to sync device context failed, err=%d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3212) __func__, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3214) xhci_free_command(xhci, cfg_cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3215) cleanup:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3216) xhci_free_command(xhci, stop_cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3217) spin_lock_irqsave(&xhci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3218) if (ep->ep_state & EP_SOFT_CLEAR_TOGGLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3219) ep->ep_state &= ~EP_SOFT_CLEAR_TOGGLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3220) spin_unlock_irqrestore(&xhci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3223) static int xhci_check_streams_endpoint(struct xhci_hcd *xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3224) struct usb_device *udev, struct usb_host_endpoint *ep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3225) unsigned int slot_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3226) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3227) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3228) unsigned int ep_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3229) unsigned int ep_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3231) if (!ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3232) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3233) ret = xhci_check_args(xhci_to_hcd(xhci), udev, ep, 1, true, __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3234) if (ret <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3235) return ret ? ret : -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3236) if (usb_ss_max_streams(&ep->ss_ep_comp) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3237) xhci_warn(xhci, "WARN: SuperSpeed Endpoint Companion"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3238) " descriptor for ep 0x%x does not support streams\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3239) ep->desc.bEndpointAddress);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3240) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3243) ep_index = xhci_get_endpoint_index(&ep->desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3244) ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3245) if (ep_state & EP_HAS_STREAMS ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3246) ep_state & EP_GETTING_STREAMS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3247) xhci_warn(xhci, "WARN: SuperSpeed bulk endpoint 0x%x "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3248) "already has streams set up.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3249) ep->desc.bEndpointAddress);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3250) xhci_warn(xhci, "Send email to xHCI maintainer and ask for "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3251) "dynamic stream context array reallocation.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3252) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3254) if (!list_empty(&xhci->devs[slot_id]->eps[ep_index].ring->td_list)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3255) xhci_warn(xhci, "Cannot setup streams for SuperSpeed bulk "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3256) "endpoint 0x%x; URBs are pending.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3257) ep->desc.bEndpointAddress);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3258) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3260) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3263) static void xhci_calculate_streams_entries(struct xhci_hcd *xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3264) unsigned int *num_streams, unsigned int *num_stream_ctxs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3265) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3266) unsigned int max_streams;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3268) /* The stream context array size must be a power of two */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3269) *num_stream_ctxs = roundup_pow_of_two(*num_streams);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3270) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3271) * Find out how many primary stream array entries the host controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3272) * supports. Later we may use secondary stream arrays (similar to 2nd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3273) * level page entries), but that's an optional feature for xHCI host
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3274) * controllers. xHCs must support at least 4 stream IDs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3275) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3276) max_streams = HCC_MAX_PSA(xhci->hcc_params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3277) if (*num_stream_ctxs > max_streams) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3278) xhci_dbg(xhci, "xHCI HW only supports %u stream ctx entries.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3279) max_streams);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3280) *num_stream_ctxs = max_streams;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3281) *num_streams = max_streams;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3285) /* Returns an error code if one of the endpoint already has streams.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3286) * This does not change any data structures, it only checks and gathers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3287) * information.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3288) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3289) static int xhci_calculate_streams_and_bitmask(struct xhci_hcd *xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3290) struct usb_device *udev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3291) struct usb_host_endpoint **eps, unsigned int num_eps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3292) unsigned int *num_streams, u32 *changed_ep_bitmask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3293) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3294) unsigned int max_streams;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3295) unsigned int endpoint_flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3296) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3297) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3299) for (i = 0; i < num_eps; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3300) ret = xhci_check_streams_endpoint(xhci, udev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3301) eps[i], udev->slot_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3302) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3303) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3305) max_streams = usb_ss_max_streams(&eps[i]->ss_ep_comp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3306) if (max_streams < (*num_streams - 1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3307) xhci_dbg(xhci, "Ep 0x%x only supports %u stream IDs.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3308) eps[i]->desc.bEndpointAddress,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3309) max_streams);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3310) *num_streams = max_streams+1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3313) endpoint_flag = xhci_get_endpoint_flag(&eps[i]->desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3314) if (*changed_ep_bitmask & endpoint_flag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3315) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3316) *changed_ep_bitmask |= endpoint_flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3318) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3321) static u32 xhci_calculate_no_streams_bitmask(struct xhci_hcd *xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3322) struct usb_device *udev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3323) struct usb_host_endpoint **eps, unsigned int num_eps)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3324) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3325) u32 changed_ep_bitmask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3326) unsigned int slot_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3327) unsigned int ep_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3328) unsigned int ep_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3329) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3331) slot_id = udev->slot_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3332) if (!xhci->devs[slot_id])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3333) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3335) for (i = 0; i < num_eps; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3336) ep_index = xhci_get_endpoint_index(&eps[i]->desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3337) ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3338) /* Are streams already being freed for the endpoint? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3339) if (ep_state & EP_GETTING_NO_STREAMS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3340) xhci_warn(xhci, "WARN Can't disable streams for "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3341) "endpoint 0x%x, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3342) "streams are being disabled already\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3343) eps[i]->desc.bEndpointAddress);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3344) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3346) /* Are there actually any streams to free? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3347) if (!(ep_state & EP_HAS_STREAMS) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3348) !(ep_state & EP_GETTING_STREAMS)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3349) xhci_warn(xhci, "WARN Can't disable streams for "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3350) "endpoint 0x%x, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3351) "streams are already disabled!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3352) eps[i]->desc.bEndpointAddress);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3353) xhci_warn(xhci, "WARN xhci_free_streams() called "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3354) "with non-streams endpoint\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3355) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3357) changed_ep_bitmask |= xhci_get_endpoint_flag(&eps[i]->desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3359) return changed_ep_bitmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3362) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3363) * The USB device drivers use this function (through the HCD interface in USB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3364) * core) to prepare a set of bulk endpoints to use streams. Streams are used to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3365) * coordinate mass storage command queueing across multiple endpoints (basically
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3366) * a stream ID == a task ID).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3367) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3368) * Setting up streams involves allocating the same size stream context array
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3369) * for each endpoint and issuing a configure endpoint command for all endpoints.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3370) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3371) * Don't allow the call to succeed if one endpoint only supports one stream
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3372) * (which means it doesn't support streams at all).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3373) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3374) * Drivers may get less stream IDs than they asked for, if the host controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3375) * hardware or endpoints claim they can't support the number of requested
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3376) * stream IDs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3377) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3378) static int xhci_alloc_streams(struct usb_hcd *hcd, struct usb_device *udev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3379) struct usb_host_endpoint **eps, unsigned int num_eps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3380) unsigned int num_streams, gfp_t mem_flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3381) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3382) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3383) struct xhci_hcd *xhci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3384) struct xhci_virt_device *vdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3385) struct xhci_command *config_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3386) struct xhci_input_control_ctx *ctrl_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3387) unsigned int ep_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3388) unsigned int num_stream_ctxs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3389) unsigned int max_packet;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3390) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3391) u32 changed_ep_bitmask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3393) if (!eps)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3394) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3396) /* Add one to the number of streams requested to account for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3397) * stream 0 that is reserved for xHCI usage.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3398) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3399) num_streams += 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3400) xhci = hcd_to_xhci(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3401) xhci_dbg(xhci, "Driver wants %u stream IDs (including stream 0).\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3402) num_streams);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3404) /* MaxPSASize value 0 (2 streams) means streams are not supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3405) if ((xhci->quirks & XHCI_BROKEN_STREAMS) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3406) HCC_MAX_PSA(xhci->hcc_params) < 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3407) xhci_dbg(xhci, "xHCI controller does not support streams.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3408) return -ENOSYS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3409) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3411) config_cmd = xhci_alloc_command_with_ctx(xhci, true, mem_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3412) if (!config_cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3413) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3415) ctrl_ctx = xhci_get_input_control_ctx(config_cmd->in_ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3416) if (!ctrl_ctx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3417) xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3418) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3419) xhci_free_command(xhci, config_cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3420) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3421) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3423) /* Check to make sure all endpoints are not already configured for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3424) * streams. While we're at it, find the maximum number of streams that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3425) * all the endpoints will support and check for duplicate endpoints.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3426) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3427) spin_lock_irqsave(&xhci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3428) ret = xhci_calculate_streams_and_bitmask(xhci, udev, eps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3429) num_eps, &num_streams, &changed_ep_bitmask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3430) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3431) xhci_free_command(xhci, config_cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3432) spin_unlock_irqrestore(&xhci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3433) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3434) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3435) if (num_streams <= 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3436) xhci_warn(xhci, "WARN: endpoints can't handle "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3437) "more than one stream.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3438) xhci_free_command(xhci, config_cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3439) spin_unlock_irqrestore(&xhci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3440) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3441) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3442) vdev = xhci->devs[udev->slot_id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3443) /* Mark each endpoint as being in transition, so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3444) * xhci_urb_enqueue() will reject all URBs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3445) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3446) for (i = 0; i < num_eps; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3447) ep_index = xhci_get_endpoint_index(&eps[i]->desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3448) vdev->eps[ep_index].ep_state |= EP_GETTING_STREAMS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3449) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3450) spin_unlock_irqrestore(&xhci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3452) /* Setup internal data structures and allocate HW data structures for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3453) * streams (but don't install the HW structures in the input context
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3454) * until we're sure all memory allocation succeeded).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3455) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3456) xhci_calculate_streams_entries(xhci, &num_streams, &num_stream_ctxs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3457) xhci_dbg(xhci, "Need %u stream ctx entries for %u stream IDs.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3458) num_stream_ctxs, num_streams);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3460) for (i = 0; i < num_eps; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3461) ep_index = xhci_get_endpoint_index(&eps[i]->desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3462) max_packet = usb_endpoint_maxp(&eps[i]->desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3463) vdev->eps[ep_index].stream_info = xhci_alloc_stream_info(xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3464) num_stream_ctxs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3465) num_streams,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3466) max_packet, mem_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3467) if (!vdev->eps[ep_index].stream_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3468) goto cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3469) /* Set maxPstreams in endpoint context and update deq ptr to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3470) * point to stream context array. FIXME
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3471) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3472) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3474) /* Set up the input context for a configure endpoint command. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3475) for (i = 0; i < num_eps; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3476) struct xhci_ep_ctx *ep_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3478) ep_index = xhci_get_endpoint_index(&eps[i]->desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3479) ep_ctx = xhci_get_ep_ctx(xhci, config_cmd->in_ctx, ep_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3481) xhci_endpoint_copy(xhci, config_cmd->in_ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3482) vdev->out_ctx, ep_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3483) xhci_setup_streams_ep_input_ctx(xhci, ep_ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3484) vdev->eps[ep_index].stream_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3485) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3486) /* Tell the HW to drop its old copy of the endpoint context info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3487) * and add the updated copy from the input context.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3488) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3489) xhci_setup_input_ctx_for_config_ep(xhci, config_cmd->in_ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3490) vdev->out_ctx, ctrl_ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3491) changed_ep_bitmask, changed_ep_bitmask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3493) /* Issue and wait for the configure endpoint command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3494) ret = xhci_configure_endpoint(xhci, udev, config_cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3495) false, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3497) /* xHC rejected the configure endpoint command for some reason, so we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3498) * leave the old ring intact and free our internal streams data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3499) * structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3500) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3501) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3502) goto cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3504) spin_lock_irqsave(&xhci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3505) for (i = 0; i < num_eps; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3506) ep_index = xhci_get_endpoint_index(&eps[i]->desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3507) vdev->eps[ep_index].ep_state &= ~EP_GETTING_STREAMS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3508) xhci_dbg(xhci, "Slot %u ep ctx %u now has streams.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3509) udev->slot_id, ep_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3510) vdev->eps[ep_index].ep_state |= EP_HAS_STREAMS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3511) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3512) xhci_free_command(xhci, config_cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3513) spin_unlock_irqrestore(&xhci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3515) for (i = 0; i < num_eps; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3516) ep_index = xhci_get_endpoint_index(&eps[i]->desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3517) xhci_debugfs_create_stream_files(xhci, vdev, ep_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3518) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3519) /* Subtract 1 for stream 0, which drivers can't use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3520) return num_streams - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3522) cleanup:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3523) /* If it didn't work, free the streams! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3524) for (i = 0; i < num_eps; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3525) ep_index = xhci_get_endpoint_index(&eps[i]->desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3526) xhci_free_stream_info(xhci, vdev->eps[ep_index].stream_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3527) vdev->eps[ep_index].stream_info = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3528) /* FIXME Unset maxPstreams in endpoint context and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3529) * update deq ptr to point to normal string ring.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3530) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3531) vdev->eps[ep_index].ep_state &= ~EP_GETTING_STREAMS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3532) vdev->eps[ep_index].ep_state &= ~EP_HAS_STREAMS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3533) xhci_endpoint_zero(xhci, vdev, eps[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3534) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3535) xhci_free_command(xhci, config_cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3536) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3537) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3539) /* Transition the endpoint from using streams to being a "normal" endpoint
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3540) * without streams.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3541) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3542) * Modify the endpoint context state, submit a configure endpoint command,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3543) * and free all endpoint rings for streams if that completes successfully.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3544) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3545) static int xhci_free_streams(struct usb_hcd *hcd, struct usb_device *udev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3546) struct usb_host_endpoint **eps, unsigned int num_eps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3547) gfp_t mem_flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3548) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3549) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3550) struct xhci_hcd *xhci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3551) struct xhci_virt_device *vdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3552) struct xhci_command *command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3553) struct xhci_input_control_ctx *ctrl_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3554) unsigned int ep_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3555) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3556) u32 changed_ep_bitmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3558) xhci = hcd_to_xhci(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3559) vdev = xhci->devs[udev->slot_id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3561) /* Set up a configure endpoint command to remove the streams rings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3562) spin_lock_irqsave(&xhci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3563) changed_ep_bitmask = xhci_calculate_no_streams_bitmask(xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3564) udev, eps, num_eps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3565) if (changed_ep_bitmask == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3566) spin_unlock_irqrestore(&xhci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3567) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3568) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3570) /* Use the xhci_command structure from the first endpoint. We may have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3571) * allocated too many, but the driver may call xhci_free_streams() for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3572) * each endpoint it grouped into one call to xhci_alloc_streams().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3573) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3574) ep_index = xhci_get_endpoint_index(&eps[0]->desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3575) command = vdev->eps[ep_index].stream_info->free_streams_command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3576) ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3577) if (!ctrl_ctx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3578) spin_unlock_irqrestore(&xhci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3579) xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3580) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3581) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3582) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3584) for (i = 0; i < num_eps; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3585) struct xhci_ep_ctx *ep_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3587) ep_index = xhci_get_endpoint_index(&eps[i]->desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3588) ep_ctx = xhci_get_ep_ctx(xhci, command->in_ctx, ep_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3589) xhci->devs[udev->slot_id]->eps[ep_index].ep_state |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3590) EP_GETTING_NO_STREAMS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3592) xhci_endpoint_copy(xhci, command->in_ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3593) vdev->out_ctx, ep_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3594) xhci_setup_no_streams_ep_input_ctx(ep_ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3595) &vdev->eps[ep_index]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3596) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3597) xhci_setup_input_ctx_for_config_ep(xhci, command->in_ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3598) vdev->out_ctx, ctrl_ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3599) changed_ep_bitmask, changed_ep_bitmask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3600) spin_unlock_irqrestore(&xhci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3602) /* Issue and wait for the configure endpoint command,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3603) * which must succeed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3604) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3605) ret = xhci_configure_endpoint(xhci, udev, command,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3606) false, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3608) /* xHC rejected the configure endpoint command for some reason, so we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3609) * leave the streams rings intact.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3610) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3611) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3612) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3614) spin_lock_irqsave(&xhci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3615) for (i = 0; i < num_eps; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3616) ep_index = xhci_get_endpoint_index(&eps[i]->desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3617) xhci_free_stream_info(xhci, vdev->eps[ep_index].stream_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3618) vdev->eps[ep_index].stream_info = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3619) /* FIXME Unset maxPstreams in endpoint context and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3620) * update deq ptr to point to normal string ring.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3621) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3622) vdev->eps[ep_index].ep_state &= ~EP_GETTING_NO_STREAMS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3623) vdev->eps[ep_index].ep_state &= ~EP_HAS_STREAMS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3624) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3625) spin_unlock_irqrestore(&xhci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3627) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3628) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3630) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3631) * Deletes endpoint resources for endpoints that were active before a Reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3632) * Device command, or a Disable Slot command. The Reset Device command leaves
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3633) * the control endpoint intact, whereas the Disable Slot command deletes it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3634) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3635) * Must be called with xhci->lock held.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3636) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3637) void xhci_free_device_endpoint_resources(struct xhci_hcd *xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3638) struct xhci_virt_device *virt_dev, bool drop_control_ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3639) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3640) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3641) unsigned int num_dropped_eps = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3642) unsigned int drop_flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3644) for (i = (drop_control_ep ? 0 : 1); i < 31; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3645) if (virt_dev->eps[i].ring) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3646) drop_flags |= 1 << i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3647) num_dropped_eps++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3648) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3649) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3650) xhci->num_active_eps -= num_dropped_eps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3651) if (num_dropped_eps)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3652) xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3653) "Dropped %u ep ctxs, flags = 0x%x, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3654) "%u now active.",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3655) num_dropped_eps, drop_flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3656) xhci->num_active_eps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3657) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3659) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3660) * This submits a Reset Device Command, which will set the device state to 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3661) * set the device address to 0, and disable all the endpoints except the default
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3662) * control endpoint. The USB core should come back and call
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3663) * xhci_address_device(), and then re-set up the configuration. If this is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3664) * called because of a usb_reset_and_verify_device(), then the old alternate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3665) * settings will be re-installed through the normal bandwidth allocation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3666) * functions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3667) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3668) * Wait for the Reset Device command to finish. Remove all structures
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3669) * associated with the endpoints that were disabled. Clear the input device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3670) * structure? Reset the control endpoint 0 max packet size?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3671) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3672) * If the virt_dev to be reset does not exist or does not match the udev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3673) * it means the device is lost, possibly due to the xHC restore error and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3674) * re-initialization during S3/S4. In this case, call xhci_alloc_dev() to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3675) * re-allocate the device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3676) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3677) static int xhci_discover_or_reset_device(struct usb_hcd *hcd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3678) struct usb_device *udev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3679) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3680) int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3681) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3682) struct xhci_hcd *xhci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3683) unsigned int slot_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3684) struct xhci_virt_device *virt_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3685) struct xhci_command *reset_device_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3686) struct xhci_slot_ctx *slot_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3687) int old_active_eps = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3689) ret = xhci_check_args(hcd, udev, NULL, 0, false, __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3690) if (ret <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3691) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3692) xhci = hcd_to_xhci(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3693) slot_id = udev->slot_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3694) virt_dev = xhci->devs[slot_id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3695) if (!virt_dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3696) xhci_dbg(xhci, "The device to be reset with slot ID %u does "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3697) "not exist. Re-allocate the device\n", slot_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3698) ret = xhci_alloc_dev(hcd, udev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3699) if (ret == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3700) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3701) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3702) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3703) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3705) if (virt_dev->tt_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3706) old_active_eps = virt_dev->tt_info->active_eps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3708) if (virt_dev->udev != udev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3709) /* If the virt_dev and the udev does not match, this virt_dev
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3710) * may belong to another udev.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3711) * Re-allocate the device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3712) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3713) xhci_dbg(xhci, "The device to be reset with slot ID %u does "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3714) "not match the udev. Re-allocate the device\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3715) slot_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3716) ret = xhci_alloc_dev(hcd, udev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3717) if (ret == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3718) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3719) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3720) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3721) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3723) /* If device is not setup, there is no point in resetting it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3724) slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3725) if (GET_SLOT_STATE(le32_to_cpu(slot_ctx->dev_state)) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3726) SLOT_STATE_DISABLED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3727) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3729) trace_xhci_discover_or_reset_device(slot_ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3731) xhci_dbg(xhci, "Resetting device with slot ID %u\n", slot_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3732) /* Allocate the command structure that holds the struct completion.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3733) * Assume we're in process context, since the normal device reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3734) * process has to wait for the device anyway. Storage devices are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3735) * reset as part of error handling, so use GFP_NOIO instead of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3736) * GFP_KERNEL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3737) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3738) reset_device_cmd = xhci_alloc_command(xhci, true, GFP_NOIO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3739) if (!reset_device_cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3740) xhci_dbg(xhci, "Couldn't allocate command structure.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3741) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3742) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3744) /* Attempt to submit the Reset Device command to the command ring */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3745) spin_lock_irqsave(&xhci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3747) ret = xhci_queue_reset_device(xhci, reset_device_cmd, slot_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3748) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3749) xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3750) spin_unlock_irqrestore(&xhci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3751) goto command_cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3752) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3753) xhci_ring_cmd_db(xhci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3754) spin_unlock_irqrestore(&xhci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3756) /* Wait for the Reset Device command to finish */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3757) wait_for_completion(reset_device_cmd->completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3759) ret = xhci_vendor_sync_dev_ctx(xhci, slot_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3760) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3761) xhci_warn(xhci, "%s: Failed to sync device context failed, err=%d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3762) __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3763) goto command_cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3764) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3766) /* The Reset Device command can't fail, according to the 0.95/0.96 spec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3767) * unless we tried to reset a slot ID that wasn't enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3768) * or the device wasn't in the addressed or configured state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3769) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3770) ret = reset_device_cmd->status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3771) switch (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3772) case COMP_COMMAND_ABORTED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3773) case COMP_COMMAND_RING_STOPPED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3774) xhci_warn(xhci, "Timeout waiting for reset device command\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3775) ret = -ETIME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3776) goto command_cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3777) case COMP_SLOT_NOT_ENABLED_ERROR: /* 0.95 completion for bad slot ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3778) case COMP_CONTEXT_STATE_ERROR: /* 0.96 completion code for same thing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3779) xhci_dbg(xhci, "Can't reset device (slot ID %u) in %s state\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3780) slot_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3781) xhci_get_slot_state(xhci, virt_dev->out_ctx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3782) xhci_dbg(xhci, "Not freeing device rings.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3783) /* Don't treat this as an error. May change my mind later. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3784) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3785) goto command_cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3786) case COMP_SUCCESS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3787) xhci_dbg(xhci, "Successful reset device command.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3788) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3789) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3790) if (xhci_is_vendor_info_code(xhci, ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3791) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3792) xhci_warn(xhci, "Unknown completion code %u for "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3793) "reset device command.\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3794) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3795) goto command_cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3796) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3798) /* Free up host controller endpoint resources */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3799) if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3800) spin_lock_irqsave(&xhci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3801) /* Don't delete the default control endpoint resources */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3802) xhci_free_device_endpoint_resources(xhci, virt_dev, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3803) spin_unlock_irqrestore(&xhci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3804) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3806) /* Everything but endpoint 0 is disabled, so free the rings. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3807) for (i = 1; i < 31; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3808) struct xhci_virt_ep *ep = &virt_dev->eps[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3810) if (ep->ep_state & EP_HAS_STREAMS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3811) xhci_warn(xhci, "WARN: endpoint 0x%02x has streams on device reset, freeing streams.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3812) xhci_get_endpoint_address(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3813) xhci_free_stream_info(xhci, ep->stream_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3814) ep->stream_info = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3815) ep->ep_state &= ~EP_HAS_STREAMS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3816) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3818) if (ep->ring) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3819) xhci_debugfs_remove_endpoint(xhci, virt_dev, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3820) xhci_free_endpoint_ring(xhci, virt_dev, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3821) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3822) if (!list_empty(&virt_dev->eps[i].bw_endpoint_list))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3823) xhci_drop_ep_from_interval_table(xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3824) &virt_dev->eps[i].bw_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3825) virt_dev->bw_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3826) udev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3827) &virt_dev->eps[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3828) virt_dev->tt_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3829) xhci_clear_endpoint_bw_info(&virt_dev->eps[i].bw_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3830) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3831) /* If necessary, update the number of active TTs on this root port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3832) xhci_update_tt_active_eps(xhci, virt_dev, old_active_eps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3833) virt_dev->flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3834) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3836) command_cleanup:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3837) xhci_free_command(xhci, reset_device_cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3838) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3839) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3841) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3842) * At this point, the struct usb_device is about to go away, the device has
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3843) * disconnected, and all traffic has been stopped and the endpoints have been
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3844) * disabled. Free any HC data structures associated with that device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3845) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3846) static void xhci_free_dev(struct usb_hcd *hcd, struct usb_device *udev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3847) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3848) struct xhci_hcd *xhci = hcd_to_xhci(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3849) struct xhci_virt_device *virt_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3850) struct xhci_slot_ctx *slot_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3851) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3853) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3854) * We called pm_runtime_get_noresume when the device was attached.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3855) * Decrement the counter here to allow controller to runtime suspend
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3856) * if no devices remain.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3857) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3858) if (xhci->quirks & XHCI_RESET_ON_RESUME)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3859) pm_runtime_put_noidle(hcd->self.controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3861) ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3862) /* If the host is halted due to driver unload, we still need to free the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3863) * device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3864) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3865) if (ret <= 0 && ret != -ENODEV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3866) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3868) virt_dev = xhci->devs[udev->slot_id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3869) slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3870) trace_xhci_free_dev(slot_ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3872) /* Stop any wayward timer functions (which may grab the lock) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3873) for (i = 0; i < 31; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3874) virt_dev->eps[i].ep_state &= ~EP_STOP_CMD_PENDING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3875) del_timer_sync(&virt_dev->eps[i].stop_cmd_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3876) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3877) virt_dev->udev = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3878) xhci_disable_slot(xhci, udev->slot_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3879) xhci_free_virt_device(xhci, udev->slot_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3880) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3882) int xhci_disable_slot(struct xhci_hcd *xhci, u32 slot_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3883) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3884) struct xhci_command *command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3885) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3886) u32 state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3887) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3889) command = xhci_alloc_command(xhci, true, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3890) if (!command)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3891) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3893) xhci_debugfs_remove_slot(xhci, slot_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3895) spin_lock_irqsave(&xhci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3896) /* Don't disable the slot if the host controller is dead. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3897) state = readl(&xhci->op_regs->status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3898) if (state == 0xffffffff || (xhci->xhc_state & XHCI_STATE_DYING) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3899) (xhci->xhc_state & XHCI_STATE_HALTED)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3900) spin_unlock_irqrestore(&xhci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3901) kfree(command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3902) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3903) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3905) ret = xhci_queue_slot_control(xhci, command, TRB_DISABLE_SLOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3906) slot_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3907) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3908) spin_unlock_irqrestore(&xhci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3909) kfree(command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3910) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3911) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3912) xhci_ring_cmd_db(xhci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3913) spin_unlock_irqrestore(&xhci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3915) wait_for_completion(command->completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3917) if (command->status != COMP_SUCCESS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3918) xhci_warn(xhci, "Unsuccessful disable slot %u command, status %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3919) slot_id, command->status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3921) xhci_free_command(xhci, command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3923) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3924) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3926) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3927) * Checks if we have enough host controller resources for the default control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3928) * endpoint.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3929) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3930) * Must be called with xhci->lock held.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3931) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3932) static int xhci_reserve_host_control_ep_resources(struct xhci_hcd *xhci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3933) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3934) if (xhci->num_active_eps + 1 > xhci->limit_active_eps) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3935) xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3936) "Not enough ep ctxs: "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3937) "%u active, need to add 1, limit is %u.",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3938) xhci->num_active_eps, xhci->limit_active_eps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3939) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3940) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3941) xhci->num_active_eps += 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3942) xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3943) "Adding 1 ep ctx, %u now active.",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3944) xhci->num_active_eps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3945) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3946) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3949) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3950) * Returns 0 if the xHC ran out of device slots, the Enable Slot command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3951) * timed out, or allocating memory failed. Returns 1 on success.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3952) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3953) int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3954) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3955) struct xhci_hcd *xhci = hcd_to_xhci(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3956) struct xhci_virt_device *vdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3957) struct xhci_slot_ctx *slot_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3958) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3959) int ret, slot_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3960) struct xhci_command *command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3962) command = xhci_alloc_command(xhci, true, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3963) if (!command)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3964) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3966) spin_lock_irqsave(&xhci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3967) ret = xhci_queue_slot_control(xhci, command, TRB_ENABLE_SLOT, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3968) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3969) spin_unlock_irqrestore(&xhci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3970) xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3971) xhci_free_command(xhci, command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3972) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3973) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3974) xhci_ring_cmd_db(xhci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3975) spin_unlock_irqrestore(&xhci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3977) wait_for_completion(command->completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3978) slot_id = command->slot_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3980) if (!slot_id || command->status != COMP_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3981) xhci_err(xhci, "Error while assigning device slot ID\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3982) xhci_err(xhci, "Max number of devices this xHCI host supports is %u.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3983) HCS_MAX_SLOTS(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3984) readl(&xhci->cap_regs->hcs_params1)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3985) xhci_free_command(xhci, command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3986) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3987) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3989) xhci_free_command(xhci, command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3991) if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3992) spin_lock_irqsave(&xhci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3993) ret = xhci_reserve_host_control_ep_resources(xhci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3994) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3995) spin_unlock_irqrestore(&xhci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3996) xhci_warn(xhci, "Not enough host resources, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3997) "active endpoint contexts = %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3998) xhci->num_active_eps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3999) goto disable_slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4000) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4001) spin_unlock_irqrestore(&xhci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4002) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4003) /* Use GFP_NOIO, since this function can be called from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4004) * xhci_discover_or_reset_device(), which may be called as part of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4005) * mass storage driver error handling.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4006) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4007) if (!xhci_alloc_virt_device(xhci, slot_id, udev, GFP_NOIO)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4008) xhci_warn(xhci, "Could not allocate xHCI USB device data structures\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4009) goto disable_slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4010) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4012) ret = xhci_vendor_sync_dev_ctx(xhci, slot_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4013) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4014) xhci_warn(xhci, "%s: Failed to sync device context failed, err=%d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4015) __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4016) goto disable_slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4017) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4019) vdev = xhci->devs[slot_id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4020) slot_ctx = xhci_get_slot_ctx(xhci, vdev->out_ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4021) trace_xhci_alloc_dev(slot_ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4023) udev->slot_id = slot_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4025) xhci_debugfs_create_slot(xhci, slot_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4027) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4028) * If resetting upon resume, we can't put the controller into runtime
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4029) * suspend if there is a device attached.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4030) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4031) if (xhci->quirks & XHCI_RESET_ON_RESUME)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4032) pm_runtime_get_noresume(hcd->self.controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4034) /* Is this a LS or FS device under a HS hub? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4035) /* Hub or peripherial? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4036) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4038) disable_slot:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4039) xhci_disable_slot(xhci, udev->slot_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4040) xhci_free_virt_device(xhci, udev->slot_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4042) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4043) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4045) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4046) * Issue an Address Device command and optionally send a corresponding
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4047) * SetAddress request to the device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4048) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4049) static int xhci_setup_device(struct usb_hcd *hcd, struct usb_device *udev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4050) enum xhci_setup_dev setup)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4051) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4052) const char *act = setup == SETUP_CONTEXT_ONLY ? "context" : "address";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4053) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4054) struct xhci_virt_device *virt_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4055) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4056) struct xhci_hcd *xhci = hcd_to_xhci(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4057) struct xhci_slot_ctx *slot_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4058) struct xhci_input_control_ctx *ctrl_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4059) u64 temp_64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4060) struct xhci_command *command = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4062) mutex_lock(&xhci->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4064) if (xhci->xhc_state) { /* dying, removing or halted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4065) ret = -ESHUTDOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4066) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4067) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4069) if (!udev->slot_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4070) xhci_dbg_trace(xhci, trace_xhci_dbg_address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4071) "Bad Slot ID %d", udev->slot_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4072) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4073) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4074) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4076) virt_dev = xhci->devs[udev->slot_id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4078) if (WARN_ON(!virt_dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4079) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4080) * In plug/unplug torture test with an NEC controller,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4081) * a zero-dereference was observed once due to virt_dev = 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4082) * Print useful debug rather than crash if it is observed again!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4083) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4084) xhci_warn(xhci, "Virt dev invalid for slot_id 0x%x!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4085) udev->slot_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4086) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4087) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4088) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4089) slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4090) trace_xhci_setup_device_slot(slot_ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4091)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4092) if (setup == SETUP_CONTEXT_ONLY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4093) if (GET_SLOT_STATE(le32_to_cpu(slot_ctx->dev_state)) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4094) SLOT_STATE_DEFAULT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4095) xhci_dbg(xhci, "Slot already in default state\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4096) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4097) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4098) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4100) command = xhci_alloc_command(xhci, true, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4101) if (!command) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4102) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4103) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4106) command->in_ctx = virt_dev->in_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4108) slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4109) ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4110) if (!ctrl_ctx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4111) xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4112) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4113) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4114) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4116) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4117) * If this is the first Set Address since device plug-in or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4118) * virt_device realloaction after a resume with an xHCI power loss,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4119) * then set up the slot context.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4120) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4121) if (!slot_ctx->dev_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4122) xhci_setup_addressable_virt_dev(xhci, udev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4123) /* Otherwise, update the control endpoint ring enqueue pointer. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4124) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4125) xhci_copy_ep0_dequeue_into_input_ctx(xhci, udev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4126) ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG | EP0_FLAG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4127) ctrl_ctx->drop_flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4129) trace_xhci_address_ctx(xhci, virt_dev->in_ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4130) le32_to_cpu(slot_ctx->dev_info) >> 27);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4132) trace_xhci_address_ctrl_ctx(ctrl_ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4133) spin_lock_irqsave(&xhci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4134) trace_xhci_setup_device(virt_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4135) ret = xhci_queue_address_device(xhci, command, virt_dev->in_ctx->dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4136) udev->slot_id, setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4137) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4138) spin_unlock_irqrestore(&xhci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4139) xhci_dbg_trace(xhci, trace_xhci_dbg_address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4140) "FIXME: allocate a command ring segment");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4141) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4143) xhci_ring_cmd_db(xhci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4144) spin_unlock_irqrestore(&xhci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4146) /* ctrl tx can take up to 5 sec; XXX: need more time for xHC? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4147) wait_for_completion(command->completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4149) ret = xhci_vendor_sync_dev_ctx(xhci, udev->slot_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4150) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4151) xhci_warn(xhci, "%s: Failed to sync device context failed, err=%d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4152) __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4153) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4156) /* FIXME: From section 4.3.4: "Software shall be responsible for timing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4157) * the SetAddress() "recovery interval" required by USB and aborting the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4158) * command on a timeout.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4159) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4160) switch (command->status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4161) case COMP_COMMAND_ABORTED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4162) case COMP_COMMAND_RING_STOPPED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4163) xhci_warn(xhci, "Timeout while waiting for setup device command\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4164) ret = -ETIME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4165) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4166) case COMP_CONTEXT_STATE_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4167) case COMP_SLOT_NOT_ENABLED_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4168) xhci_err(xhci, "Setup ERROR: setup %s command for slot %d.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4169) act, udev->slot_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4170) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4171) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4172) case COMP_USB_TRANSACTION_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4173) dev_warn(&udev->dev, "Device not responding to setup %s.\n", act);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4175) mutex_unlock(&xhci->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4176) ret = xhci_disable_slot(xhci, udev->slot_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4177) xhci_free_virt_device(xhci, udev->slot_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4178) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4179) xhci_alloc_dev(hcd, udev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4180) kfree(command->completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4181) kfree(command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4182) return -EPROTO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4183) case COMP_INCOMPATIBLE_DEVICE_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4184) dev_warn(&udev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4185) "ERROR: Incompatible device for setup %s command\n", act);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4186) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4187) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4188) case COMP_SUCCESS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4189) xhci_dbg_trace(xhci, trace_xhci_dbg_address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4190) "Successful setup %s command", act);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4191) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4192) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4193) xhci_err(xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4194) "ERROR: unexpected setup %s command completion code 0x%x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4195) act, command->status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4196) trace_xhci_address_ctx(xhci, virt_dev->out_ctx, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4197) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4198) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4200) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4201) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4202) temp_64 = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4203) xhci_dbg_trace(xhci, trace_xhci_dbg_address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4204) "Op regs DCBAA ptr = %#016llx", temp_64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4205) xhci_dbg_trace(xhci, trace_xhci_dbg_address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4206) "Slot ID %d dcbaa entry @%p = %#016llx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4207) udev->slot_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4208) &xhci->dcbaa->dev_context_ptrs[udev->slot_id],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4209) (unsigned long long)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4210) le64_to_cpu(xhci->dcbaa->dev_context_ptrs[udev->slot_id]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4211) xhci_dbg_trace(xhci, trace_xhci_dbg_address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4212) "Output Context DMA address = %#08llx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4213) (unsigned long long)virt_dev->out_ctx->dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4214) trace_xhci_address_ctx(xhci, virt_dev->in_ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4215) le32_to_cpu(slot_ctx->dev_info) >> 27);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4216) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4217) * USB core uses address 1 for the roothubs, so we add one to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4218) * address given back to us by the HC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4219) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4220) trace_xhci_address_ctx(xhci, virt_dev->out_ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4221) le32_to_cpu(slot_ctx->dev_info) >> 27);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4222) /* Zero the input context control for later use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4223) ctrl_ctx->add_flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4224) ctrl_ctx->drop_flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4225) slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4226) udev->devaddr = (u8)(le32_to_cpu(slot_ctx->dev_state) & DEV_ADDR_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4228) xhci_dbg_trace(xhci, trace_xhci_dbg_address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4229) "Internal device address = %d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4230) le32_to_cpu(slot_ctx->dev_state) & DEV_ADDR_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4231) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4232) mutex_unlock(&xhci->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4233) if (command) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4234) kfree(command->completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4235) kfree(command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4237) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4240) int xhci_address_device(struct usb_hcd *hcd, struct usb_device *udev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4241) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4242) return xhci_setup_device(hcd, udev, SETUP_CONTEXT_ADDRESS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4244) EXPORT_SYMBOL_GPL(xhci_address_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4246) static int xhci_enable_device(struct usb_hcd *hcd, struct usb_device *udev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4247) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4248) return xhci_setup_device(hcd, udev, SETUP_CONTEXT_ONLY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4251) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4252) * Transfer the port index into real index in the HW port status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4253) * registers. Caculate offset between the port's PORTSC register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4254) * and port status base. Divide the number of per port register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4255) * to get the real index. The raw port number bases 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4256) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4257) int xhci_find_raw_port_number(struct usb_hcd *hcd, int port1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4258) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4259) struct xhci_hub *rhub;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4261) rhub = xhci_get_rhub(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4262) return rhub->ports[port1 - 1]->hw_portnum + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4265) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4266) * Issue an Evaluate Context command to change the Maximum Exit Latency in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4267) * slot context. If that succeeds, store the new MEL in the xhci_virt_device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4268) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4269) static int __maybe_unused xhci_change_max_exit_latency(struct xhci_hcd *xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4270) struct usb_device *udev, u16 max_exit_latency)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4271) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4272) struct xhci_virt_device *virt_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4273) struct xhci_command *command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4274) struct xhci_input_control_ctx *ctrl_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4275) struct xhci_slot_ctx *slot_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4276) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4277) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4279) spin_lock_irqsave(&xhci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4281) virt_dev = xhci->devs[udev->slot_id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4283) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4284) * virt_dev might not exists yet if xHC resumed from hibernate (S4) and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4285) * xHC was re-initialized. Exit latency will be set later after
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4286) * hub_port_finish_reset() is done and xhci->devs[] are re-allocated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4287) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4289) if (!virt_dev || max_exit_latency == virt_dev->current_mel) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4290) spin_unlock_irqrestore(&xhci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4291) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4294) /* Attempt to issue an Evaluate Context command to change the MEL. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4295) command = xhci->lpm_command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4296) ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4297) if (!ctrl_ctx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4298) spin_unlock_irqrestore(&xhci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4299) xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4300) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4301) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4304) ret = xhci_vendor_sync_dev_ctx(xhci, udev->slot_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4305) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4306) spin_unlock_irqrestore(&xhci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4307) xhci_warn(xhci, "%s: Failed to sync device context failed, err=%d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4308) __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4309) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4312) xhci_slot_copy(xhci, command->in_ctx, virt_dev->out_ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4313) spin_unlock_irqrestore(&xhci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4315) ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4316) slot_ctx = xhci_get_slot_ctx(xhci, command->in_ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4317) slot_ctx->dev_info2 &= cpu_to_le32(~((u32) MAX_EXIT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4318) slot_ctx->dev_info2 |= cpu_to_le32(max_exit_latency);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4319) slot_ctx->dev_state = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4321) xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4322) "Set up evaluate context for LPM MEL change.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4324) /* Issue and wait for the evaluate context command. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4325) ret = xhci_configure_endpoint(xhci, udev, command,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4326) true, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4328) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4329) spin_lock_irqsave(&xhci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4330) virt_dev->current_mel = max_exit_latency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4331) spin_unlock_irqrestore(&xhci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4333) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4336) struct xhci_vendor_ops *xhci_vendor_get_ops(struct xhci_hcd *xhci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4337) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4338) return xhci->vendor_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4340) EXPORT_SYMBOL_GPL(xhci_vendor_get_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4342) int xhci_vendor_sync_dev_ctx(struct xhci_hcd *xhci, unsigned int slot_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4343) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4344) struct xhci_vendor_ops *ops = xhci_vendor_get_ops(xhci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4346) if (ops && ops->sync_dev_ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4347) return ops->sync_dev_ctx(xhci, slot_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4348) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4351) bool xhci_vendor_usb_offload_skip_urb(struct xhci_hcd *xhci, struct urb *urb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4352) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4353) struct xhci_vendor_ops *ops = xhci_vendor_get_ops(xhci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4355) if (ops && ops->usb_offload_skip_urb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4356) return ops->usb_offload_skip_urb(xhci, urb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4357) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4360) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4362) /* BESL to HIRD Encoding array for USB2 LPM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4363) static int xhci_besl_encoding[16] = {125, 150, 200, 300, 400, 500, 1000, 2000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4364) 3000, 4000, 5000, 6000, 7000, 8000, 9000, 10000};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4366) /* Calculate HIRD/BESL for USB2 PORTPMSC*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4367) static int xhci_calculate_hird_besl(struct xhci_hcd *xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4368) struct usb_device *udev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4369) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4370) int u2del, besl, besl_host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4371) int besl_device = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4372) u32 field;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4374) u2del = HCS_U2_LATENCY(xhci->hcs_params3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4375) field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4377) if (field & USB_BESL_SUPPORT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4378) for (besl_host = 0; besl_host < 16; besl_host++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4379) if (xhci_besl_encoding[besl_host] >= u2del)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4380) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4381) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4382) /* Use baseline BESL value as default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4383) if (field & USB_BESL_BASELINE_VALID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4384) besl_device = USB_GET_BESL_BASELINE(field);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4385) else if (field & USB_BESL_DEEP_VALID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4386) besl_device = USB_GET_BESL_DEEP(field);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4387) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4388) if (u2del <= 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4389) besl_host = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4390) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4391) besl_host = (u2del - 51) / 75 + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4392) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4394) besl = besl_host + besl_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4395) if (besl > 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4396) besl = 15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4398) return besl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4401) /* Calculate BESLD, L1 timeout and HIRDM for USB2 PORTHLPMC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4402) static int xhci_calculate_usb2_hw_lpm_params(struct usb_device *udev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4403) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4404) u32 field;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4405) int l1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4406) int besld = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4407) int hirdm = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4409) field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4411) /* xHCI l1 is set in steps of 256us, xHCI 1.0 section 5.4.11.2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4412) l1 = udev->l1_params.timeout / 256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4414) /* device has preferred BESLD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4415) if (field & USB_BESL_DEEP_VALID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4416) besld = USB_GET_BESL_DEEP(field);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4417) hirdm = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4418) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4420) return PORT_BESLD(besld) | PORT_L1_TIMEOUT(l1) | PORT_HIRDM(hirdm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4421) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4423) static int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4424) struct usb_device *udev, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4425) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4426) struct xhci_hcd *xhci = hcd_to_xhci(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4427) struct xhci_port **ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4428) __le32 __iomem *pm_addr, *hlpm_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4429) u32 pm_val, hlpm_val, field;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4430) unsigned int port_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4431) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4432) int hird, exit_latency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4433) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4435) if (xhci->quirks & XHCI_HW_LPM_DISABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4436) return -EPERM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4438) if (hcd->speed >= HCD_USB3 || !xhci->hw_lpm_support ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4439) !udev->lpm_capable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4440) return -EPERM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4442) if (!udev->parent || udev->parent->parent ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4443) udev->descriptor.bDeviceClass == USB_CLASS_HUB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4444) return -EPERM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4446) if (udev->usb2_hw_lpm_capable != 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4447) return -EPERM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4449) spin_lock_irqsave(&xhci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4451) ports = xhci->usb2_rhub.ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4452) port_num = udev->portnum - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4453) pm_addr = ports[port_num]->addr + PORTPMSC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4454) pm_val = readl(pm_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4455) hlpm_addr = ports[port_num]->addr + PORTHLPMC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4457) xhci_dbg(xhci, "%s port %d USB2 hardware LPM\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4458) enable ? "enable" : "disable", port_num + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4460) if (enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4461) /* Host supports BESL timeout instead of HIRD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4462) if (udev->usb2_hw_lpm_besl_capable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4463) /* if device doesn't have a preferred BESL value use a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4464) * default one which works with mixed HIRD and BESL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4465) * systems. See XHCI_DEFAULT_BESL definition in xhci.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4466) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4467) field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4468) if ((field & USB_BESL_SUPPORT) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4469) (field & USB_BESL_BASELINE_VALID))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4470) hird = USB_GET_BESL_BASELINE(field);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4471) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4472) hird = udev->l1_params.besl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4474) exit_latency = xhci_besl_encoding[hird];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4475) spin_unlock_irqrestore(&xhci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4477) /* USB 3.0 code dedicate one xhci->lpm_command->in_ctx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4478) * input context for link powermanagement evaluate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4479) * context commands. It is protected by hcd->bandwidth
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4480) * mutex and is shared by all devices. We need to set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4481) * the max ext latency in USB 2 BESL LPM as well, so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4482) * use the same mutex and xhci_change_max_exit_latency()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4483) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4484) mutex_lock(hcd->bandwidth_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4485) ret = xhci_change_max_exit_latency(xhci, udev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4486) exit_latency);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4487) mutex_unlock(hcd->bandwidth_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4489) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4490) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4491) spin_lock_irqsave(&xhci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4493) hlpm_val = xhci_calculate_usb2_hw_lpm_params(udev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4494) writel(hlpm_val, hlpm_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4495) /* flush write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4496) readl(hlpm_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4497) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4498) hird = xhci_calculate_hird_besl(xhci, udev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4499) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4501) pm_val &= ~PORT_HIRD_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4502) pm_val |= PORT_HIRD(hird) | PORT_RWE | PORT_L1DS(udev->slot_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4503) writel(pm_val, pm_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4504) pm_val = readl(pm_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4505) pm_val |= PORT_HLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4506) writel(pm_val, pm_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4507) /* flush write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4508) readl(pm_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4509) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4510) pm_val &= ~(PORT_HLE | PORT_RWE | PORT_HIRD_MASK | PORT_L1DS_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4511) writel(pm_val, pm_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4512) /* flush write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4513) readl(pm_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4514) if (udev->usb2_hw_lpm_besl_capable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4515) spin_unlock_irqrestore(&xhci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4516) mutex_lock(hcd->bandwidth_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4517) xhci_change_max_exit_latency(xhci, udev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4518) mutex_unlock(hcd->bandwidth_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4519) readl_poll_timeout(ports[port_num]->addr, pm_val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4520) (pm_val & PORT_PLS_MASK) == XDEV_U0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4521) 100, 10000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4522) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4523) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4524) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4526) spin_unlock_irqrestore(&xhci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4527) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4528) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4530) /* check if a usb2 port supports a given extened capability protocol
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4531) * only USB2 ports extended protocol capability values are cached.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4532) * Return 1 if capability is supported
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4533) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4534) static int xhci_check_usb2_port_capability(struct xhci_hcd *xhci, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4535) unsigned capability)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4536) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4537) u32 port_offset, port_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4538) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4540) for (i = 0; i < xhci->num_ext_caps; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4541) if (xhci->ext_caps[i] & capability) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4542) /* port offsets starts at 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4543) port_offset = XHCI_EXT_PORT_OFF(xhci->ext_caps[i]) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4544) port_count = XHCI_EXT_PORT_COUNT(xhci->ext_caps[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4545) if (port >= port_offset &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4546) port < port_offset + port_count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4547) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4548) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4549) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4550) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4551) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4553) static int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4554) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4555) struct xhci_hcd *xhci = hcd_to_xhci(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4556) int portnum = udev->portnum - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4558) if (hcd->speed >= HCD_USB3 || !udev->lpm_capable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4559) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4561) /* we only support lpm for non-hub device connected to root hub yet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4562) if (!udev->parent || udev->parent->parent ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4563) udev->descriptor.bDeviceClass == USB_CLASS_HUB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4564) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4566) if (xhci->hw_lpm_support == 1 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4567) xhci_check_usb2_port_capability(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4568) xhci, portnum, XHCI_HLC)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4569) udev->usb2_hw_lpm_capable = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4570) udev->l1_params.timeout = XHCI_L1_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4571) udev->l1_params.besl = XHCI_DEFAULT_BESL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4572) if (xhci_check_usb2_port_capability(xhci, portnum,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4573) XHCI_BLC))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4574) udev->usb2_hw_lpm_besl_capable = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4575) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4577) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4578) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4580) /*---------------------- USB 3.0 Link PM functions ------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4582) /* Service interval in nanoseconds = 2^(bInterval - 1) * 125us * 1000ns / 1us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4583) static unsigned long long xhci_service_interval_to_ns(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4584) struct usb_endpoint_descriptor *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4585) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4586) return (1ULL << (desc->bInterval - 1)) * 125 * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4587) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4589) static u16 xhci_get_timeout_no_hub_lpm(struct usb_device *udev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4590) enum usb3_link_state state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4591) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4592) unsigned long long sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4593) unsigned long long pel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4594) unsigned int max_sel_pel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4595) char *state_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4597) switch (state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4598) case USB3_LPM_U1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4599) /* Convert SEL and PEL stored in nanoseconds to microseconds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4600) sel = DIV_ROUND_UP(udev->u1_params.sel, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4601) pel = DIV_ROUND_UP(udev->u1_params.pel, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4602) max_sel_pel = USB3_LPM_MAX_U1_SEL_PEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4603) state_name = "U1";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4604) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4605) case USB3_LPM_U2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4606) sel = DIV_ROUND_UP(udev->u2_params.sel, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4607) pel = DIV_ROUND_UP(udev->u2_params.pel, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4608) max_sel_pel = USB3_LPM_MAX_U2_SEL_PEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4609) state_name = "U2";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4610) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4611) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4612) dev_warn(&udev->dev, "%s: Can't get timeout for non-U1 or U2 state.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4613) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4614) return USB3_LPM_DISABLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4615) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4617) if (sel <= max_sel_pel && pel <= max_sel_pel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4618) return USB3_LPM_DEVICE_INITIATED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4620) if (sel > max_sel_pel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4621) dev_dbg(&udev->dev, "Device-initiated %s disabled "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4622) "due to long SEL %llu ms\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4623) state_name, sel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4624) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4625) dev_dbg(&udev->dev, "Device-initiated %s disabled "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4626) "due to long PEL %llu ms\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4627) state_name, pel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4628) return USB3_LPM_DISABLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4629) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4631) /* The U1 timeout should be the maximum of the following values:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4632) * - For control endpoints, U1 system exit latency (SEL) * 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4633) * - For bulk endpoints, U1 SEL * 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4634) * - For interrupt endpoints:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4635) * - Notification EPs, U1 SEL * 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4636) * - Periodic EPs, max(105% of bInterval, U1 SEL * 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4637) * - For isochronous endpoints, max(105% of bInterval, U1 SEL * 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4638) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4639) static unsigned long long xhci_calculate_intel_u1_timeout(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4640) struct usb_device *udev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4641) struct usb_endpoint_descriptor *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4642) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4643) unsigned long long timeout_ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4644) int ep_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4645) int intr_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4647) ep_type = usb_endpoint_type(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4648) switch (ep_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4649) case USB_ENDPOINT_XFER_CONTROL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4650) timeout_ns = udev->u1_params.sel * 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4651) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4652) case USB_ENDPOINT_XFER_BULK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4653) timeout_ns = udev->u1_params.sel * 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4654) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4655) case USB_ENDPOINT_XFER_INT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4656) intr_type = usb_endpoint_interrupt_type(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4657) if (intr_type == USB_ENDPOINT_INTR_NOTIFICATION) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4658) timeout_ns = udev->u1_params.sel * 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4659) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4660) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4661) /* Otherwise the calculation is the same as isoc eps */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4662) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4663) case USB_ENDPOINT_XFER_ISOC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4664) timeout_ns = xhci_service_interval_to_ns(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4665) timeout_ns = DIV_ROUND_UP_ULL(timeout_ns * 105, 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4666) if (timeout_ns < udev->u1_params.sel * 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4667) timeout_ns = udev->u1_params.sel * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4668) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4669) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4670) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4671) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4673) return timeout_ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4674) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4676) /* Returns the hub-encoded U1 timeout value. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4677) static u16 xhci_calculate_u1_timeout(struct xhci_hcd *xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4678) struct usb_device *udev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4679) struct usb_endpoint_descriptor *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4680) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4681) unsigned long long timeout_ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4683) /* Prevent U1 if service interval is shorter than U1 exit latency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4684) if (usb_endpoint_xfer_int(desc) || usb_endpoint_xfer_isoc(desc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4685) if (xhci_service_interval_to_ns(desc) <= udev->u1_params.mel) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4686) dev_dbg(&udev->dev, "Disable U1, ESIT shorter than exit latency\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4687) return USB3_LPM_DISABLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4688) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4689) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4691) if (xhci->quirks & XHCI_INTEL_HOST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4692) timeout_ns = xhci_calculate_intel_u1_timeout(udev, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4693) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4694) timeout_ns = udev->u1_params.sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4696) /* The U1 timeout is encoded in 1us intervals.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4697) * Don't return a timeout of zero, because that's USB3_LPM_DISABLED.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4698) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4699) if (timeout_ns == USB3_LPM_DISABLED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4700) timeout_ns = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4701) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4702) timeout_ns = DIV_ROUND_UP_ULL(timeout_ns, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4704) /* If the necessary timeout value is bigger than what we can set in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4705) * USB 3.0 hub, we have to disable hub-initiated U1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4706) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4707) if (timeout_ns <= USB3_LPM_U1_MAX_TIMEOUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4708) return timeout_ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4709) dev_dbg(&udev->dev, "Hub-initiated U1 disabled "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4710) "due to long timeout %llu ms\n", timeout_ns);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4711) return xhci_get_timeout_no_hub_lpm(udev, USB3_LPM_U1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4712) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4714) /* The U2 timeout should be the maximum of:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4715) * - 10 ms (to avoid the bandwidth impact on the scheduler)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4716) * - largest bInterval of any active periodic endpoint (to avoid going
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4717) * into lower power link states between intervals).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4718) * - the U2 Exit Latency of the device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4719) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4720) static unsigned long long xhci_calculate_intel_u2_timeout(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4721) struct usb_device *udev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4722) struct usb_endpoint_descriptor *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4723) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4724) unsigned long long timeout_ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4725) unsigned long long u2_del_ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4727) timeout_ns = 10 * 1000 * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4729) if ((usb_endpoint_xfer_int(desc) || usb_endpoint_xfer_isoc(desc)) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4730) (xhci_service_interval_to_ns(desc) > timeout_ns))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4731) timeout_ns = xhci_service_interval_to_ns(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4733) u2_del_ns = le16_to_cpu(udev->bos->ss_cap->bU2DevExitLat) * 1000ULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4734) if (u2_del_ns > timeout_ns)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4735) timeout_ns = u2_del_ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4737) return timeout_ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4738) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4740) /* Returns the hub-encoded U2 timeout value. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4741) static u16 xhci_calculate_u2_timeout(struct xhci_hcd *xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4742) struct usb_device *udev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4743) struct usb_endpoint_descriptor *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4744) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4745) unsigned long long timeout_ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4747) /* Prevent U2 if service interval is shorter than U2 exit latency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4748) if (usb_endpoint_xfer_int(desc) || usb_endpoint_xfer_isoc(desc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4749) if (xhci_service_interval_to_ns(desc) <= udev->u2_params.mel) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4750) dev_dbg(&udev->dev, "Disable U2, ESIT shorter than exit latency\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4751) return USB3_LPM_DISABLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4752) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4753) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4755) if (xhci->quirks & XHCI_INTEL_HOST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4756) timeout_ns = xhci_calculate_intel_u2_timeout(udev, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4757) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4758) timeout_ns = udev->u2_params.sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4760) /* The U2 timeout is encoded in 256us intervals */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4761) timeout_ns = DIV_ROUND_UP_ULL(timeout_ns, 256 * 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4762) /* If the necessary timeout value is bigger than what we can set in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4763) * USB 3.0 hub, we have to disable hub-initiated U2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4764) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4765) if (timeout_ns <= USB3_LPM_U2_MAX_TIMEOUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4766) return timeout_ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4767) dev_dbg(&udev->dev, "Hub-initiated U2 disabled "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4768) "due to long timeout %llu ms\n", timeout_ns);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4769) return xhci_get_timeout_no_hub_lpm(udev, USB3_LPM_U2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4770) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4772) static u16 xhci_call_host_update_timeout_for_endpoint(struct xhci_hcd *xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4773) struct usb_device *udev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4774) struct usb_endpoint_descriptor *desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4775) enum usb3_link_state state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4776) u16 *timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4777) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4778) if (state == USB3_LPM_U1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4779) return xhci_calculate_u1_timeout(xhci, udev, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4780) else if (state == USB3_LPM_U2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4781) return xhci_calculate_u2_timeout(xhci, udev, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4783) return USB3_LPM_DISABLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4784) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4786) static int xhci_update_timeout_for_endpoint(struct xhci_hcd *xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4787) struct usb_device *udev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4788) struct usb_endpoint_descriptor *desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4789) enum usb3_link_state state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4790) u16 *timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4791) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4792) u16 alt_timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4794) alt_timeout = xhci_call_host_update_timeout_for_endpoint(xhci, udev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4795) desc, state, timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4797) /* If we found we can't enable hub-initiated LPM, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4798) * the U1 or U2 exit latency was too high to allow
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4799) * device-initiated LPM as well, then we will disable LPM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4800) * for this device, so stop searching any further.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4801) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4802) if (alt_timeout == USB3_LPM_DISABLED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4803) *timeout = alt_timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4804) return -E2BIG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4805) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4806) if (alt_timeout > *timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4807) *timeout = alt_timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4808) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4809) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4811) static int xhci_update_timeout_for_interface(struct xhci_hcd *xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4812) struct usb_device *udev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4813) struct usb_host_interface *alt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4814) enum usb3_link_state state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4815) u16 *timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4816) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4817) int j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4819) for (j = 0; j < alt->desc.bNumEndpoints; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4820) if (xhci_update_timeout_for_endpoint(xhci, udev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4821) &alt->endpoint[j].desc, state, timeout))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4822) return -E2BIG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4823) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4824) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4825) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4826) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4828) static int xhci_check_intel_tier_policy(struct usb_device *udev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4829) enum usb3_link_state state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4830) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4831) struct usb_device *parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4832) unsigned int num_hubs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4834) if (state == USB3_LPM_U2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4835) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4837) /* Don't enable U1 if the device is on a 2nd tier hub or lower. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4838) for (parent = udev->parent, num_hubs = 0; parent->parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4839) parent = parent->parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4840) num_hubs++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4842) if (num_hubs < 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4843) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4845) dev_dbg(&udev->dev, "Disabling U1 link state for device"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4846) " below second-tier hub.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4847) dev_dbg(&udev->dev, "Plug device into first-tier hub "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4848) "to decrease power consumption.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4849) return -E2BIG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4850) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4852) static int xhci_check_tier_policy(struct xhci_hcd *xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4853) struct usb_device *udev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4854) enum usb3_link_state state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4855) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4856) if (xhci->quirks & XHCI_INTEL_HOST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4857) return xhci_check_intel_tier_policy(udev, state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4858) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4859) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4860) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4862) /* Returns the U1 or U2 timeout that should be enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4863) * If the tier check or timeout setting functions return with a non-zero exit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4864) * code, that means the timeout value has been finalized and we shouldn't look
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4865) * at any more endpoints.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4866) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4867) static u16 xhci_calculate_lpm_timeout(struct usb_hcd *hcd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4868) struct usb_device *udev, enum usb3_link_state state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4869) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4870) struct xhci_hcd *xhci = hcd_to_xhci(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4871) struct usb_host_config *config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4872) char *state_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4873) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4874) u16 timeout = USB3_LPM_DISABLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4876) if (state == USB3_LPM_U1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4877) state_name = "U1";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4878) else if (state == USB3_LPM_U2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4879) state_name = "U2";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4880) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4881) dev_warn(&udev->dev, "Can't enable unknown link state %i\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4882) state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4883) return timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4884) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4886) if (xhci_check_tier_policy(xhci, udev, state) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4887) return timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4889) /* Gather some information about the currently installed configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4890) * and alternate interface settings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4891) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4892) if (xhci_update_timeout_for_endpoint(xhci, udev, &udev->ep0.desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4893) state, &timeout))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4894) return timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4896) config = udev->actconfig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4897) if (!config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4898) return timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4900) for (i = 0; i < config->desc.bNumInterfaces; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4901) struct usb_driver *driver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4902) struct usb_interface *intf = config->interface[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4904) if (!intf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4905) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4907) /* Check if any currently bound drivers want hub-initiated LPM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4908) * disabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4909) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4910) if (intf->dev.driver) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4911) driver = to_usb_driver(intf->dev.driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4912) if (driver && driver->disable_hub_initiated_lpm) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4913) dev_dbg(&udev->dev, "Hub-initiated %s disabled at request of driver %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4914) state_name, driver->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4915) timeout = xhci_get_timeout_no_hub_lpm(udev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4916) state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4917) if (timeout == USB3_LPM_DISABLED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4918) return timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4919) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4920) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4922) /* Not sure how this could happen... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4923) if (!intf->cur_altsetting)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4924) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4926) if (xhci_update_timeout_for_interface(xhci, udev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4927) intf->cur_altsetting,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4928) state, &timeout))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4929) return timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4930) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4931) return timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4932) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4934) static int calculate_max_exit_latency(struct usb_device *udev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4935) enum usb3_link_state state_changed,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4936) u16 hub_encoded_timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4937) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4938) unsigned long long u1_mel_us = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4939) unsigned long long u2_mel_us = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4940) unsigned long long mel_us = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4941) bool disabling_u1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4942) bool disabling_u2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4943) bool enabling_u1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4944) bool enabling_u2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4946) disabling_u1 = (state_changed == USB3_LPM_U1 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4947) hub_encoded_timeout == USB3_LPM_DISABLED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4948) disabling_u2 = (state_changed == USB3_LPM_U2 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4949) hub_encoded_timeout == USB3_LPM_DISABLED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4951) enabling_u1 = (state_changed == USB3_LPM_U1 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4952) hub_encoded_timeout != USB3_LPM_DISABLED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4953) enabling_u2 = (state_changed == USB3_LPM_U2 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4954) hub_encoded_timeout != USB3_LPM_DISABLED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4956) /* If U1 was already enabled and we're not disabling it,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4957) * or we're going to enable U1, account for the U1 max exit latency.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4958) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4959) if ((udev->u1_params.timeout != USB3_LPM_DISABLED && !disabling_u1) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4960) enabling_u1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4961) u1_mel_us = DIV_ROUND_UP(udev->u1_params.mel, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4962) if ((udev->u2_params.timeout != USB3_LPM_DISABLED && !disabling_u2) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4963) enabling_u2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4964) u2_mel_us = DIV_ROUND_UP(udev->u2_params.mel, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4966) if (u1_mel_us > u2_mel_us)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4967) mel_us = u1_mel_us;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4968) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4969) mel_us = u2_mel_us;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4970) /* xHCI host controller max exit latency field is only 16 bits wide. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4971) if (mel_us > MAX_EXIT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4972) dev_warn(&udev->dev, "Link PM max exit latency of %lluus "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4973) "is too big.\n", mel_us);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4974) return -E2BIG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4975) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4976) return mel_us;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4977) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4979) /* Returns the USB3 hub-encoded value for the U1/U2 timeout. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4980) static int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4981) struct usb_device *udev, enum usb3_link_state state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4982) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4983) struct xhci_hcd *xhci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4984) u16 hub_encoded_timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4985) int mel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4986) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4988) xhci = hcd_to_xhci(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4989) /* The LPM timeout values are pretty host-controller specific, so don't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4990) * enable hub-initiated timeouts unless the vendor has provided
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4991) * information about their timeout algorithm.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4992) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4993) if (!xhci || !(xhci->quirks & XHCI_LPM_SUPPORT) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4994) !xhci->devs[udev->slot_id])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4995) return USB3_LPM_DISABLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4997) hub_encoded_timeout = xhci_calculate_lpm_timeout(hcd, udev, state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4998) mel = calculate_max_exit_latency(udev, state, hub_encoded_timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4999) if (mel < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5000) /* Max Exit Latency is too big, disable LPM. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5001) hub_encoded_timeout = USB3_LPM_DISABLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5002) mel = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5003) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5005) ret = xhci_change_max_exit_latency(xhci, udev, mel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5006) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5007) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5008) return hub_encoded_timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5009) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5011) static int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5012) struct usb_device *udev, enum usb3_link_state state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5013) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5014) struct xhci_hcd *xhci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5015) u16 mel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5017) xhci = hcd_to_xhci(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5018) if (!xhci || !(xhci->quirks & XHCI_LPM_SUPPORT) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5019) !xhci->devs[udev->slot_id])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5020) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5022) mel = calculate_max_exit_latency(udev, state, USB3_LPM_DISABLED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5023) return xhci_change_max_exit_latency(xhci, udev, mel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5024) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5025) #else /* CONFIG_PM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5027) static int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5028) struct usb_device *udev, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5029) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5030) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5031) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5033) static int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5034) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5035) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5036) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5038) static int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5039) struct usb_device *udev, enum usb3_link_state state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5040) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5041) return USB3_LPM_DISABLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5042) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5044) static int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5045) struct usb_device *udev, enum usb3_link_state state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5046) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5047) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5048) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5049) #endif /* CONFIG_PM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5051) /*-------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5053) /* Once a hub descriptor is fetched for a device, we need to update the xHC's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5054) * internal data structures for the device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5055) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5056) static int xhci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5057) struct usb_tt *tt, gfp_t mem_flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5058) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5059) struct xhci_hcd *xhci = hcd_to_xhci(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5060) struct xhci_virt_device *vdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5061) struct xhci_command *config_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5062) struct xhci_input_control_ctx *ctrl_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5063) struct xhci_slot_ctx *slot_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5064) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5065) unsigned think_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5066) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5068) /* Ignore root hubs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5069) if (!hdev->parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5070) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5072) vdev = xhci->devs[hdev->slot_id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5073) if (!vdev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5074) xhci_warn(xhci, "Cannot update hub desc for unknown device.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5075) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5076) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5078) config_cmd = xhci_alloc_command_with_ctx(xhci, true, mem_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5079) if (!config_cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5080) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5082) ctrl_ctx = xhci_get_input_control_ctx(config_cmd->in_ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5083) if (!ctrl_ctx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5084) xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5085) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5086) xhci_free_command(xhci, config_cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5087) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5088) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5090) spin_lock_irqsave(&xhci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5091) if (hdev->speed == USB_SPEED_HIGH &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5092) xhci_alloc_tt_info(xhci, vdev, hdev, tt, GFP_ATOMIC)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5093) xhci_dbg(xhci, "Could not allocate xHCI TT structure.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5094) xhci_free_command(xhci, config_cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5095) spin_unlock_irqrestore(&xhci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5096) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5097) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5099) ret = xhci_vendor_sync_dev_ctx(xhci, hdev->slot_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5100) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5101) xhci_warn(xhci, "%s: Failed to sync device context failed, err=%d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5102) __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5103) xhci_free_command(xhci, config_cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5104) spin_unlock_irqrestore(&xhci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5105) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5108) xhci_slot_copy(xhci, config_cmd->in_ctx, vdev->out_ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5109) ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5110) slot_ctx = xhci_get_slot_ctx(xhci, config_cmd->in_ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5111) slot_ctx->dev_info |= cpu_to_le32(DEV_HUB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5112) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5113) * refer to section 6.2.2: MTT should be 0 for full speed hub,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5114) * but it may be already set to 1 when setup an xHCI virtual
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5115) * device, so clear it anyway.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5116) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5117) if (tt->multi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5118) slot_ctx->dev_info |= cpu_to_le32(DEV_MTT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5119) else if (hdev->speed == USB_SPEED_FULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5120) slot_ctx->dev_info &= cpu_to_le32(~DEV_MTT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5122) if (xhci->hci_version > 0x95) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5123) xhci_dbg(xhci, "xHCI version %x needs hub "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5124) "TT think time and number of ports\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5125) (unsigned int) xhci->hci_version);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5126) slot_ctx->dev_info2 |= cpu_to_le32(XHCI_MAX_PORTS(hdev->maxchild));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5127) /* Set TT think time - convert from ns to FS bit times.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5128) * 0 = 8 FS bit times, 1 = 16 FS bit times,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5129) * 2 = 24 FS bit times, 3 = 32 FS bit times.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5130) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5131) * xHCI 1.0: this field shall be 0 if the device is not a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5132) * High-spped hub.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5133) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5134) think_time = tt->think_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5135) if (think_time != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5136) think_time = (think_time / 666) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5137) if (xhci->hci_version < 0x100 || hdev->speed == USB_SPEED_HIGH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5138) slot_ctx->tt_info |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5139) cpu_to_le32(TT_THINK_TIME(think_time));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5140) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5141) xhci_dbg(xhci, "xHCI version %x doesn't need hub "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5142) "TT think time or number of ports\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5143) (unsigned int) xhci->hci_version);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5145) slot_ctx->dev_state = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5146) spin_unlock_irqrestore(&xhci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5148) xhci_dbg(xhci, "Set up %s for hub device.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5149) (xhci->hci_version > 0x95) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5150) "configure endpoint" : "evaluate context");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5152) /* Issue and wait for the configure endpoint or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5153) * evaluate context command.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5154) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5155) if (xhci->hci_version > 0x95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5156) ret = xhci_configure_endpoint(xhci, hdev, config_cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5157) false, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5158) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5159) ret = xhci_configure_endpoint(xhci, hdev, config_cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5160) true, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5162) xhci_free_command(xhci, config_cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5163) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5166) static int xhci_get_frame(struct usb_hcd *hcd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5167) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5168) struct xhci_hcd *xhci = hcd_to_xhci(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5169) /* EHCI mods by the periodic size. Why? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5170) return readl(&xhci->run_regs->microframe_index) >> 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5173) int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5174) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5175) struct xhci_hcd *xhci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5176) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5177) * TODO: Check with DWC3 clients for sysdev according to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5178) * quirks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5179) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5180) struct device *dev = hcd->self.sysdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5181) unsigned int minor_rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5182) int retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5184) /* Accept arbitrarily long scatter-gather lists */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5185) hcd->self.sg_tablesize = ~0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5187) /* support to build packet from discontinuous buffers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5188) hcd->self.no_sg_constraint = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5190) /* XHCI controllers don't stop the ep queue on short packets :| */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5191) hcd->self.no_stop_on_short = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5193) xhci = hcd_to_xhci(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5195) if (usb_hcd_is_primary_hcd(hcd)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5196) xhci->main_hcd = hcd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5197) xhci->usb2_rhub.hcd = hcd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5198) /* Mark the first roothub as being USB 2.0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5199) * The xHCI driver will register the USB 3.0 roothub.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5200) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5201) hcd->speed = HCD_USB2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5202) hcd->self.root_hub->speed = USB_SPEED_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5203) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5204) * USB 2.0 roothub under xHCI has an integrated TT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5205) * (rate matching hub) as opposed to having an OHCI/UHCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5206) * companion controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5207) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5208) hcd->has_tt = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5209) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5210) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5211) * Early xHCI 1.1 spec did not mention USB 3.1 capable hosts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5212) * should return 0x31 for sbrn, or that the minor revision
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5213) * is a two digit BCD containig minor and sub-minor numbers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5214) * This was later clarified in xHCI 1.2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5215) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5216) * Some USB 3.1 capable hosts therefore have sbrn 0x30, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5217) * minor revision set to 0x1 instead of 0x10.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5218) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5219) if (xhci->usb3_rhub.min_rev == 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5220) minor_rev = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5221) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5222) minor_rev = xhci->usb3_rhub.min_rev / 0x10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5224) switch (minor_rev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5225) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5226) hcd->speed = HCD_USB32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5227) hcd->self.root_hub->speed = USB_SPEED_SUPER_PLUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5228) hcd->self.root_hub->rx_lanes = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5229) hcd->self.root_hub->tx_lanes = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5230) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5231) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5232) hcd->speed = HCD_USB31;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5233) hcd->self.root_hub->speed = USB_SPEED_SUPER_PLUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5234) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5236) xhci_info(xhci, "Host supports USB 3.%x %sSuperSpeed\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5237) minor_rev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5238) minor_rev ? "Enhanced " : "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5240) xhci->usb3_rhub.hcd = hcd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5241) /* xHCI private pointer was set in xhci_pci_probe for the second
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5242) * registered roothub.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5243) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5244) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5247) mutex_init(&xhci->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5248) xhci->cap_regs = hcd->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5249) xhci->op_regs = hcd->regs +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5250) HC_LENGTH(readl(&xhci->cap_regs->hc_capbase));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5251) xhci->run_regs = hcd->regs +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5252) (readl(&xhci->cap_regs->run_regs_off) & RTSOFF_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5253) /* Cache read-only capability registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5254) xhci->hcs_params1 = readl(&xhci->cap_regs->hcs_params1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5255) xhci->hcs_params2 = readl(&xhci->cap_regs->hcs_params2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5256) xhci->hcs_params3 = readl(&xhci->cap_regs->hcs_params3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5257) xhci->hcc_params = readl(&xhci->cap_regs->hc_capbase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5258) xhci->hci_version = HC_VERSION(xhci->hcc_params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5259) xhci->hcc_params = readl(&xhci->cap_regs->hcc_params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5260) if (xhci->hci_version > 0x100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5261) xhci->hcc_params2 = readl(&xhci->cap_regs->hcc_params2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5263) xhci->quirks |= quirks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5265) get_quirks(dev, xhci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5267) /* In xhci controllers which follow xhci 1.0 spec gives a spurious
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5268) * success event after a short transfer. This quirk will ignore such
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5269) * spurious event.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5270) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5271) if (xhci->hci_version > 0x96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5272) xhci->quirks |= XHCI_SPURIOUS_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5274) /* Make sure the HC is halted. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5275) retval = xhci_halt(xhci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5276) if (retval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5277) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5279) xhci_zero_64b_regs(xhci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5281) xhci_dbg(xhci, "Resetting HCD\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5282) /* Reset the internal HC memory state and registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5283) retval = xhci_reset(xhci, XHCI_RESET_LONG_USEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5284) if (retval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5285) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5286) xhci_dbg(xhci, "Reset complete\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5288) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5289) * On some xHCI controllers (e.g. R-Car SoCs), the AC64 bit (bit 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5290) * of HCCPARAMS1 is set to 1. However, the xHCs don't support 64-bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5291) * address memory pointers actually. So, this driver clears the AC64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5292) * bit of xhci->hcc_params to call dma_set_coherent_mask(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5293) * DMA_BIT_MASK(32)) in this xhci_gen_setup().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5294) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5295) if (xhci->quirks & XHCI_NO_64BIT_SUPPORT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5296) xhci->hcc_params &= ~BIT(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5298) /* Set dma_mask and coherent_dma_mask to 64-bits,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5299) * if xHC supports 64-bit addressing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5300) if (HCC_64BIT_ADDR(xhci->hcc_params) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5301) !dma_set_mask(dev, DMA_BIT_MASK(64))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5302) xhci_dbg(xhci, "Enabling 64-bit DMA addresses.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5303) dma_set_coherent_mask(dev, DMA_BIT_MASK(64));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5304) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5305) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5306) * This is to avoid error in cases where a 32-bit USB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5307) * controller is used on a 64-bit capable system.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5308) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5309) retval = dma_set_mask(dev, DMA_BIT_MASK(32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5310) if (retval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5311) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5312) xhci_dbg(xhci, "Enabling 32-bit DMA addresses.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5313) dma_set_coherent_mask(dev, DMA_BIT_MASK(32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5316) xhci_dbg(xhci, "Calling HCD init\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5317) /* Initialize HCD and host controller data structures. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5318) retval = xhci_init(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5319) if (retval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5320) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5321) xhci_dbg(xhci, "Called HCD init\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5323) xhci_info(xhci, "hcc params 0x%08x hci version 0x%x quirks 0x%016llx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5324) xhci->hcc_params, xhci->hci_version, xhci->quirks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5326) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5328) EXPORT_SYMBOL_GPL(xhci_gen_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5330) static void xhci_clear_tt_buffer_complete(struct usb_hcd *hcd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5331) struct usb_host_endpoint *ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5332) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5333) struct xhci_hcd *xhci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5334) struct usb_device *udev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5335) unsigned int slot_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5336) unsigned int ep_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5337) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5339) xhci = hcd_to_xhci(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5341) spin_lock_irqsave(&xhci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5342) udev = (struct usb_device *)ep->hcpriv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5343) slot_id = udev->slot_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5344) ep_index = xhci_get_endpoint_index(&ep->desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5346) xhci->devs[slot_id]->eps[ep_index].ep_state &= ~EP_CLEARING_TT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5347) xhci_ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5348) spin_unlock_irqrestore(&xhci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5351) static const struct hc_driver xhci_hc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5352) .description = "xhci-hcd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5353) .product_desc = "xHCI Host Controller",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5354) .hcd_priv_size = sizeof(struct xhci_hcd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5356) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5357) * generic hardware linkage
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5358) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5359) .irq = xhci_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5360) .flags = HCD_MEMORY | HCD_DMA | HCD_USB3 | HCD_SHARED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5361) HCD_BH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5363) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5364) * basic lifecycle operations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5365) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5366) .reset = NULL, /* set in xhci_init_driver() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5367) .start = xhci_run,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5368) .stop = xhci_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5369) .shutdown = xhci_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5371) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5372) * managing i/o requests and associated device resources
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5373) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5374) .map_urb_for_dma = xhci_map_urb_for_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5375) .urb_enqueue = xhci_urb_enqueue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5376) .urb_dequeue = xhci_urb_dequeue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5377) .alloc_dev = xhci_alloc_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5378) .free_dev = xhci_free_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5379) .alloc_streams = xhci_alloc_streams,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5380) .free_streams = xhci_free_streams,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5381) .add_endpoint = xhci_add_endpoint,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5382) .drop_endpoint = xhci_drop_endpoint,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5383) .endpoint_disable = xhci_endpoint_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5384) .endpoint_reset = xhci_endpoint_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5385) .check_bandwidth = xhci_check_bandwidth,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5386) .reset_bandwidth = xhci_reset_bandwidth,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5387) .address_device = xhci_address_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5388) .enable_device = xhci_enable_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5389) .update_hub_device = xhci_update_hub_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5390) .reset_device = xhci_discover_or_reset_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5392) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5393) * scheduling support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5394) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5395) .get_frame_number = xhci_get_frame,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5397) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5398) * root hub support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5399) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5400) .hub_control = xhci_hub_control,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5401) .hub_status_data = xhci_hub_status_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5402) .bus_suspend = xhci_bus_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5403) .bus_resume = xhci_bus_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5404) .get_resuming_ports = xhci_get_resuming_ports,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5406) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5407) * call back when device connected and addressed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5408) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5409) .update_device = xhci_update_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5410) .set_usb2_hw_lpm = xhci_set_usb2_hardware_lpm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5411) .enable_usb3_lpm_timeout = xhci_enable_usb3_lpm_timeout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5412) .disable_usb3_lpm_timeout = xhci_disable_usb3_lpm_timeout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5413) .find_raw_port_number = xhci_find_raw_port_number,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5414) .clear_tt_buffer_complete = xhci_clear_tt_buffer_complete,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5415) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5417) void xhci_init_driver(struct hc_driver *drv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5418) const struct xhci_driver_overrides *over)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5419) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5420) BUG_ON(!over);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5422) /* Copy the generic table to drv then apply the overrides */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5423) *drv = xhci_hc_driver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5425) if (over) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5426) drv->hcd_priv_size += over->extra_priv_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5427) if (over->reset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5428) drv->reset = over->reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5429) if (over->start)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5430) drv->start = over->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5431) if (over->add_endpoint)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5432) drv->add_endpoint = over->add_endpoint;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5433) if (over->drop_endpoint)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5434) drv->drop_endpoint = over->drop_endpoint;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5435) if (over->check_bandwidth)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5436) drv->check_bandwidth = over->check_bandwidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5437) if (over->reset_bandwidth)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5438) drv->reset_bandwidth = over->reset_bandwidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5439) if (over->address_device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5440) drv->address_device = over->address_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5441) if (over->bus_suspend)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5442) drv->bus_suspend = over->bus_suspend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5443) if (over->bus_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5444) drv->bus_resume = over->bus_resume;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5445) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5446) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5447) EXPORT_SYMBOL_GPL(xhci_init_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5449) MODULE_DESCRIPTION(DRIVER_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5450) MODULE_AUTHOR(DRIVER_AUTHOR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5451) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5453) static int __init xhci_hcd_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5454) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5455) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5456) * Check the compiler generated sizes of structures that must be laid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5457) * out in specific ways for hardware access.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5458) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5459) BUILD_BUG_ON(sizeof(struct xhci_doorbell_array) != 256*32/8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5460) BUILD_BUG_ON(sizeof(struct xhci_slot_ctx) != 8*32/8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5461) BUILD_BUG_ON(sizeof(struct xhci_ep_ctx) != 8*32/8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5462) /* xhci_device_control has eight fields, and also
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5463) * embeds one xhci_slot_ctx and 31 xhci_ep_ctx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5464) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5465) BUILD_BUG_ON(sizeof(struct xhci_stream_ctx) != 4*32/8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5466) BUILD_BUG_ON(sizeof(union xhci_trb) != 4*32/8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5467) BUILD_BUG_ON(sizeof(struct xhci_erst_entry) != 4*32/8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5468) BUILD_BUG_ON(sizeof(struct xhci_cap_regs) != 8*32/8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5469) BUILD_BUG_ON(sizeof(struct xhci_intr_reg) != 8*32/8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5470) /* xhci_run_regs has eight fields and embeds 128 xhci_intr_regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5471) BUILD_BUG_ON(sizeof(struct xhci_run_regs) != (8+8*128)*32/8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5473) if (usb_disabled())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5474) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5476) xhci_debugfs_create_root();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5478) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5481) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5482) * If an init function is provided, an exit function must also be provided
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5483) * to allow module unload.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5484) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5485) static void __exit xhci_hcd_fini(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5486) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5487) xhci_debugfs_remove_root();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5488) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5490) module_init(xhci_hcd_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5491) module_exit(xhci_hcd_fini);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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