^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * NVIDIA Tegra xHCI host controller driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2014 NVIDIA Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2014 Google, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/firmware.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/iopoll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/phy/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/phy/tegra/xusb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/pm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/pm_domain.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/usb/otg.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/usb/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/usb/role.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <soc/tegra/pmc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include "xhci.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define TEGRA_XHCI_SS_HIGH_SPEED 120000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define TEGRA_XHCI_SS_LOW_SPEED 12000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /* FPCI CFG registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define XUSB_CFG_1 0x004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define XUSB_IO_SPACE_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define XUSB_MEM_SPACE_EN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define XUSB_BUS_MASTER_EN BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define XUSB_CFG_4 0x010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define XUSB_BASE_ADDR_SHIFT 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define XUSB_BASE_ADDR_MASK 0x1ffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define XUSB_CFG_16 0x040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define XUSB_CFG_24 0x060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define XUSB_CFG_AXI_CFG 0x0f8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define XUSB_CFG_ARU_C11_CSBRANGE 0x41c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define XUSB_CFG_ARU_CONTEXT 0x43c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define XUSB_CFG_ARU_CONTEXT_HS_PLS 0x478
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define XUSB_CFG_ARU_CONTEXT_FS_PLS 0x47c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define XUSB_CFG_ARU_CONTEXT_HSFS_SPEED 0x480
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define XUSB_CFG_ARU_CONTEXT_HSFS_PP 0x484
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define XUSB_CFG_CSB_BASE_ADDR 0x800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /* FPCI mailbox registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* XUSB_CFG_ARU_MBOX_CMD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define MBOX_DEST_FALC BIT(27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define MBOX_DEST_PME BIT(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define MBOX_DEST_SMI BIT(29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define MBOX_DEST_XHCI BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define MBOX_INT_EN BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /* XUSB_CFG_ARU_MBOX_DATA_IN and XUSB_CFG_ARU_MBOX_DATA_OUT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define CMD_DATA_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define CMD_DATA_MASK 0xffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define CMD_TYPE_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define CMD_TYPE_MASK 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /* XUSB_CFG_ARU_MBOX_OWNER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define MBOX_OWNER_NONE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define MBOX_OWNER_FW 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define MBOX_OWNER_SW 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define XUSB_CFG_ARU_SMI_INTR 0x428
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define MBOX_SMI_INTR_FW_HANG BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define MBOX_SMI_INTR_EN BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /* IPFS registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define IPFS_XUSB_HOST_MSI_BAR_SZ_0 0x0c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define IPFS_XUSB_HOST_MSI_AXI_BAR_ST_0 0x0c4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define IPFS_XUSB_HOST_MSI_FPCI_BAR_ST_0 0x0c8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define IPFS_XUSB_HOST_MSI_VEC0_0 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define IPFS_XUSB_HOST_MSI_EN_VEC0_0 0x140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define IPFS_XUSB_HOST_CONFIGURATION_0 0x180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define IPFS_EN_FPCI BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define IPFS_XUSB_HOST_FPCI_ERROR_MASKS_0 0x184
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define IPFS_XUSB_HOST_INTR_MASK_0 0x188
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define IPFS_IP_INT_MASK BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define IPFS_XUSB_HOST_INTR_ENABLE_0 0x198
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define IPFS_XUSB_HOST_UFPCI_CONFIG_0 0x19c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define IPFS_XUSB_HOST_CLKGATE_HYSTERESIS_0 0x1bc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define IPFS_XUSB_HOST_MCCIF_FIFOCTRL_0 0x1dc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define CSB_PAGE_SELECT_MASK 0x7fffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define CSB_PAGE_SELECT_SHIFT 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define CSB_PAGE_OFFSET_MASK 0x1ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define CSB_PAGE_SELECT(addr) ((addr) >> (CSB_PAGE_SELECT_SHIFT) & \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) CSB_PAGE_SELECT_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define CSB_PAGE_OFFSET(addr) ((addr) & CSB_PAGE_OFFSET_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /* Falcon CSB registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define XUSB_FALC_CPUCTL 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define CPUCTL_STARTCPU BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define CPUCTL_STATE_HALTED BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define CPUCTL_STATE_STOPPED BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define XUSB_FALC_BOOTVEC 0x104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define XUSB_FALC_DMACTL 0x10c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define XUSB_FALC_IMFILLRNG1 0x154
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define IMFILLRNG1_TAG_MASK 0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define IMFILLRNG1_TAG_LO_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define IMFILLRNG1_TAG_HI_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define XUSB_FALC_IMFILLCTL 0x158
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /* MP CSB registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define XUSB_CSB_MP_ILOAD_ATTR 0x101a00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define XUSB_CSB_MP_ILOAD_BASE_LO 0x101a04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define XUSB_CSB_MP_ILOAD_BASE_HI 0x101a08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define XUSB_CSB_MP_L2IMEMOP_SIZE 0x101a10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define L2IMEMOP_SIZE_SRC_OFFSET_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define L2IMEMOP_SIZE_SRC_OFFSET_MASK 0x3ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define L2IMEMOP_SIZE_SRC_COUNT_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define L2IMEMOP_SIZE_SRC_COUNT_MASK 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define XUSB_CSB_MP_L2IMEMOP_TRIG 0x101a14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define L2IMEMOP_ACTION_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define L2IMEMOP_INVALIDATE_ALL (0x40 << L2IMEMOP_ACTION_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define L2IMEMOP_LOAD_LOCKED_RESULT (0x11 << L2IMEMOP_ACTION_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define XUSB_CSB_MEMPOOL_L2IMEMOP_RESULT 0x101a18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define L2IMEMOP_RESULT_VLD BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define XUSB_CSB_MP_APMAP 0x10181c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define APMAP_BOOTPATH BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define IMEM_BLOCK_SIZE 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) struct tegra_xusb_fw_header {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) __le32 boot_loadaddr_in_imem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) __le32 boot_codedfi_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) __le32 boot_codetag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) __le32 boot_codesize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) __le32 phys_memaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) __le16 reqphys_memsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) __le16 alloc_phys_memsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) __le32 rodata_img_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) __le32 rodata_section_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) __le32 rodata_section_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) __le32 main_fnaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) __le32 fwimg_cksum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) __le32 fwimg_created_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) __le32 imem_resident_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) __le32 imem_resident_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) __le32 idirect_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) __le32 idirect_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) __le32 l2_imem_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) __le32 l2_imem_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) __le32 version_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) u8 init_ddirect;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) u8 reserved[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) __le32 phys_addr_log_buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) __le32 total_log_entries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) __le32 dequeue_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) __le32 dummy_var[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) __le32 fwimg_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) u8 magic[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) __le32 ss_low_power_entry_timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) u8 num_hsic_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) u8 padding[139]; /* Pad to 256 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) struct tegra_xusb_phy_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) unsigned int num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) struct tegra_xusb_mbox_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) u16 cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) u16 data_in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) u16 data_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) u16 owner;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) struct tegra_xusb_context_soc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) const unsigned int *offsets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) unsigned int num_offsets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) } ipfs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) const unsigned int *offsets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) unsigned int num_offsets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) } fpci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) struct tegra_xusb_soc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) const char *firmware;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) const char * const *supply_names;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) unsigned int num_supplies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) const struct tegra_xusb_phy_type *phy_types;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) unsigned int num_types;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) const struct tegra_xusb_context_soc *context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) unsigned int offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) unsigned int count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) } usb2, ulpi, hsic, usb3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) } ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) struct tegra_xusb_mbox_regs mbox;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) bool scale_ss_clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) bool has_ipfs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) bool lpm_support;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) bool otg_reset_sspi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) struct tegra_xusb_context {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) u32 *ipfs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) u32 *fpci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) struct tegra_xusb {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) struct usb_hcd *hcd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) int xhci_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) int mbox_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) void __iomem *ipfs_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) void __iomem *fpci_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) const struct tegra_xusb_soc *soc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) struct regulator_bulk_data *supplies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) struct tegra_xusb_padctl *padctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) struct clk *host_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) struct clk *falcon_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) struct clk *ss_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) struct clk *ss_src_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) struct clk *hs_src_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) struct clk *fs_src_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) struct clk *pll_u_480m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) struct clk *clk_m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) struct clk *pll_e;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) struct reset_control *host_rst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) struct reset_control *ss_rst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) struct device *genpd_dev_host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) struct device *genpd_dev_ss;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) struct device_link *genpd_dl_host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) struct device_link *genpd_dl_ss;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) struct phy **phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) unsigned int num_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) struct usb_phy **usbphy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) unsigned int num_usb_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) int otg_usb2_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) int otg_usb3_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) bool host_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) struct notifier_block id_nb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) struct work_struct id_work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) /* Firmware loading related */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) size_t size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) void *virt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) dma_addr_t phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) } fw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) struct tegra_xusb_context context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) static struct hc_driver __read_mostly tegra_xhci_hc_driver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) static inline u32 fpci_readl(struct tegra_xusb *tegra, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) return readl(tegra->fpci_base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) static inline void fpci_writel(struct tegra_xusb *tegra, u32 value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) writel(value, tegra->fpci_base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) static inline u32 ipfs_readl(struct tegra_xusb *tegra, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) return readl(tegra->ipfs_base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) static inline void ipfs_writel(struct tegra_xusb *tegra, u32 value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) writel(value, tegra->ipfs_base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) static u32 csb_readl(struct tegra_xusb *tegra, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) u32 page = CSB_PAGE_SELECT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) u32 ofs = CSB_PAGE_OFFSET(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) fpci_writel(tegra, page, XUSB_CFG_ARU_C11_CSBRANGE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) return fpci_readl(tegra, XUSB_CFG_CSB_BASE_ADDR + ofs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) static void csb_writel(struct tegra_xusb *tegra, u32 value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) u32 page = CSB_PAGE_SELECT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) u32 ofs = CSB_PAGE_OFFSET(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) fpci_writel(tegra, page, XUSB_CFG_ARU_C11_CSBRANGE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) fpci_writel(tegra, value, XUSB_CFG_CSB_BASE_ADDR + ofs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) static int tegra_xusb_set_ss_clk(struct tegra_xusb *tegra,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) unsigned long rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) unsigned long new_parent_rate, old_parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) struct clk *clk = tegra->ss_src_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) unsigned int div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) if (clk_get_rate(clk) == rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) switch (rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) case TEGRA_XHCI_SS_HIGH_SPEED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) * Reparent to PLLU_480M. Set divider first to avoid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) * overclocking.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) old_parent_rate = clk_get_rate(clk_get_parent(clk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) new_parent_rate = clk_get_rate(tegra->pll_u_480m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) div = new_parent_rate / rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) err = clk_set_rate(clk, old_parent_rate / div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) err = clk_set_parent(clk, tegra->pll_u_480m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) * The rate should already be correct, but set it again just
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) * to be sure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) err = clk_set_rate(clk, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) case TEGRA_XHCI_SS_LOW_SPEED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) /* Reparent to CLK_M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) err = clk_set_parent(clk, tegra->clk_m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) err = clk_set_rate(clk, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) dev_err(tegra->dev, "Invalid SS rate: %lu Hz\n", rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) if (clk_get_rate(clk) != rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) dev_err(tegra->dev, "SS clock doesn't match requested rate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) static unsigned long extract_field(u32 value, unsigned int start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) unsigned int count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) return (value >> start) & ((1 << count) - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) /* Command requests from the firmware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) enum tegra_xusb_mbox_cmd {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) MBOX_CMD_MSG_ENABLED = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) MBOX_CMD_INC_FALC_CLOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) MBOX_CMD_DEC_FALC_CLOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) MBOX_CMD_INC_SSPI_CLOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) MBOX_CMD_DEC_SSPI_CLOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) MBOX_CMD_SET_BW, /* no ACK/NAK required */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) MBOX_CMD_SET_SS_PWR_GATING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) MBOX_CMD_SET_SS_PWR_UNGATING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) MBOX_CMD_SAVE_DFE_CTLE_CTX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) MBOX_CMD_AIRPLANE_MODE_ENABLED, /* unused */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) MBOX_CMD_AIRPLANE_MODE_DISABLED, /* unused */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) MBOX_CMD_START_HSIC_IDLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) MBOX_CMD_STOP_HSIC_IDLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) MBOX_CMD_DBC_WAKE_STACK, /* unused */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) MBOX_CMD_HSIC_PRETEND_CONNECT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) MBOX_CMD_RESET_SSPI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) MBOX_CMD_DISABLE_SS_LFPS_DETECTION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) MBOX_CMD_ENABLE_SS_LFPS_DETECTION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) MBOX_CMD_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) /* Response message to above commands */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) MBOX_CMD_ACK = 128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) MBOX_CMD_NAK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) struct tegra_xusb_mbox_msg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) u32 cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) u32 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) static inline u32 tegra_xusb_mbox_pack(const struct tegra_xusb_mbox_msg *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) return (msg->cmd & CMD_TYPE_MASK) << CMD_TYPE_SHIFT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) (msg->data & CMD_DATA_MASK) << CMD_DATA_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) static inline void tegra_xusb_mbox_unpack(struct tegra_xusb_mbox_msg *msg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) msg->cmd = (value >> CMD_TYPE_SHIFT) & CMD_TYPE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) msg->data = (value >> CMD_DATA_SHIFT) & CMD_DATA_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) static bool tegra_xusb_mbox_cmd_requires_ack(enum tegra_xusb_mbox_cmd cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) case MBOX_CMD_SET_BW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) case MBOX_CMD_ACK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) case MBOX_CMD_NAK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) static int tegra_xusb_mbox_send(struct tegra_xusb *tegra,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) const struct tegra_xusb_mbox_msg *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) bool wait_for_idle = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) * Acquire the mailbox. The firmware still owns the mailbox for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) * ACK/NAK messages.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) if (!(msg->cmd == MBOX_CMD_ACK || msg->cmd == MBOX_CMD_NAK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) value = fpci_readl(tegra, tegra->soc->mbox.owner);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) if (value != MBOX_OWNER_NONE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) dev_err(tegra->dev, "mailbox is busy\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) fpci_writel(tegra, MBOX_OWNER_SW, tegra->soc->mbox.owner);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) value = fpci_readl(tegra, tegra->soc->mbox.owner);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) if (value != MBOX_OWNER_SW) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) dev_err(tegra->dev, "failed to acquire mailbox\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) wait_for_idle = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) value = tegra_xusb_mbox_pack(msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) fpci_writel(tegra, value, tegra->soc->mbox.data_in);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) value = fpci_readl(tegra, tegra->soc->mbox.cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) value |= MBOX_INT_EN | MBOX_DEST_FALC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) fpci_writel(tegra, value, tegra->soc->mbox.cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) if (wait_for_idle) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) unsigned long timeout = jiffies + msecs_to_jiffies(250);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) while (time_before(jiffies, timeout)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) value = fpci_readl(tegra, tegra->soc->mbox.owner);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) if (value == MBOX_OWNER_NONE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) usleep_range(10, 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) if (time_after(jiffies, timeout))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) value = fpci_readl(tegra, tegra->soc->mbox.owner);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) if (value != MBOX_OWNER_NONE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) static irqreturn_t tegra_xusb_mbox_irq(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) struct tegra_xusb *tegra = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) /* clear mailbox interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) value = fpci_readl(tegra, XUSB_CFG_ARU_SMI_INTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) fpci_writel(tegra, value, XUSB_CFG_ARU_SMI_INTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) if (value & MBOX_SMI_INTR_FW_HANG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) dev_err(tegra->dev, "controller firmware hang\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) return IRQ_WAKE_THREAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) static void tegra_xusb_mbox_handle(struct tegra_xusb *tegra,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) const struct tegra_xusb_mbox_msg *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) struct tegra_xusb_padctl *padctl = tegra->padctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) const struct tegra_xusb_soc *soc = tegra->soc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) struct device *dev = tegra->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) struct tegra_xusb_mbox_msg rsp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) unsigned long mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) unsigned int port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) bool idle, enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) memset(&rsp, 0, sizeof(rsp));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) switch (msg->cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) case MBOX_CMD_INC_FALC_CLOCK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) case MBOX_CMD_DEC_FALC_CLOCK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) rsp.data = clk_get_rate(tegra->falcon_clk) / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) if (rsp.data != msg->data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) rsp.cmd = MBOX_CMD_NAK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) rsp.cmd = MBOX_CMD_ACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) case MBOX_CMD_INC_SSPI_CLOCK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) case MBOX_CMD_DEC_SSPI_CLOCK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) if (tegra->soc->scale_ss_clock) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) err = tegra_xusb_set_ss_clk(tegra, msg->data * 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) rsp.cmd = MBOX_CMD_NAK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) rsp.cmd = MBOX_CMD_ACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) rsp.data = clk_get_rate(tegra->ss_src_clk) / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) rsp.cmd = MBOX_CMD_ACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) rsp.data = msg->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) case MBOX_CMD_SET_BW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) * TODO: Request bandwidth once EMC scaling is supported.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) * Ignore for now since ACK/NAK is not required for SET_BW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) * messages.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) case MBOX_CMD_SAVE_DFE_CTLE_CTX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) err = tegra_xusb_padctl_usb3_save_context(padctl, msg->data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) dev_err(dev, "failed to save context for USB3#%u: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) msg->data, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) rsp.cmd = MBOX_CMD_NAK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) rsp.cmd = MBOX_CMD_ACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) rsp.data = msg->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) case MBOX_CMD_START_HSIC_IDLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) case MBOX_CMD_STOP_HSIC_IDLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) if (msg->cmd == MBOX_CMD_STOP_HSIC_IDLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) idle = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) idle = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) mask = extract_field(msg->data, 1 + soc->ports.hsic.offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) soc->ports.hsic.count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) for_each_set_bit(port, &mask, 32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) err = tegra_xusb_padctl_hsic_set_idle(padctl, port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) idle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) dev_err(dev, "failed to set HSIC#%u %s: %d\n", port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) idle ? "idle" : "busy", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) rsp.cmd = MBOX_CMD_NAK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) rsp.cmd = MBOX_CMD_ACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) rsp.data = msg->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) case MBOX_CMD_DISABLE_SS_LFPS_DETECTION:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) case MBOX_CMD_ENABLE_SS_LFPS_DETECTION:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) if (msg->cmd == MBOX_CMD_DISABLE_SS_LFPS_DETECTION)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) enable = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) enable = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) mask = extract_field(msg->data, 1 + soc->ports.usb3.offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) soc->ports.usb3.count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) for_each_set_bit(port, &mask, soc->ports.usb3.count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) err = tegra_xusb_padctl_usb3_set_lfps_detect(padctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) * wait 500us for LFPS detector to be disabled before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) * sending ACK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) if (!enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) usleep_range(500, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) dev_err(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) "failed to %s LFPS detection on USB3#%u: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) enable ? "enable" : "disable", port, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) rsp.cmd = MBOX_CMD_NAK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) rsp.cmd = MBOX_CMD_ACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) rsp.data = msg->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) dev_warn(dev, "unknown message: %#x\n", msg->cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) if (rsp.cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) const char *cmd = (rsp.cmd == MBOX_CMD_ACK) ? "ACK" : "NAK";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) err = tegra_xusb_mbox_send(tegra, &rsp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) dev_err(dev, "failed to send %s: %d\n", cmd, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) static irqreturn_t tegra_xusb_mbox_thread(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) struct tegra_xusb *tegra = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) struct tegra_xusb_mbox_msg msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) mutex_lock(&tegra->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) value = fpci_readl(tegra, tegra->soc->mbox.data_out);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) tegra_xusb_mbox_unpack(&msg, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) value = fpci_readl(tegra, tegra->soc->mbox.cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) value &= ~MBOX_DEST_SMI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) fpci_writel(tegra, value, tegra->soc->mbox.cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) /* clear mailbox owner if no ACK/NAK is required */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) if (!tegra_xusb_mbox_cmd_requires_ack(msg.cmd))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) fpci_writel(tegra, MBOX_OWNER_NONE, tegra->soc->mbox.owner);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) tegra_xusb_mbox_handle(tegra, &msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) mutex_unlock(&tegra->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) static void tegra_xusb_config(struct tegra_xusb *tegra)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) u32 regs = tegra->hcd->rsrc_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) if (tegra->soc->has_ipfs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) value = ipfs_readl(tegra, IPFS_XUSB_HOST_CONFIGURATION_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) value |= IPFS_EN_FPCI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) ipfs_writel(tegra, value, IPFS_XUSB_HOST_CONFIGURATION_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) usleep_range(10, 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) /* Program BAR0 space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) value = fpci_readl(tegra, XUSB_CFG_4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) value &= ~(XUSB_BASE_ADDR_MASK << XUSB_BASE_ADDR_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) value |= regs & (XUSB_BASE_ADDR_MASK << XUSB_BASE_ADDR_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) fpci_writel(tegra, value, XUSB_CFG_4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) usleep_range(100, 200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) /* Enable bus master */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) value = fpci_readl(tegra, XUSB_CFG_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) value |= XUSB_IO_SPACE_EN | XUSB_MEM_SPACE_EN | XUSB_BUS_MASTER_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) fpci_writel(tegra, value, XUSB_CFG_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) if (tegra->soc->has_ipfs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) /* Enable interrupt assertion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) value = ipfs_readl(tegra, IPFS_XUSB_HOST_INTR_MASK_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) value |= IPFS_IP_INT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) ipfs_writel(tegra, value, IPFS_XUSB_HOST_INTR_MASK_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) /* Set hysteresis */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) ipfs_writel(tegra, 0x80, IPFS_XUSB_HOST_CLKGATE_HYSTERESIS_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) static int tegra_xusb_clk_enable(struct tegra_xusb *tegra)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) err = clk_prepare_enable(tegra->pll_e);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) err = clk_prepare_enable(tegra->host_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) goto disable_plle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) err = clk_prepare_enable(tegra->ss_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) goto disable_host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) err = clk_prepare_enable(tegra->falcon_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) goto disable_ss;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) err = clk_prepare_enable(tegra->fs_src_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) goto disable_falc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) err = clk_prepare_enable(tegra->hs_src_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) goto disable_fs_src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) if (tegra->soc->scale_ss_clock) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) err = tegra_xusb_set_ss_clk(tegra, TEGRA_XHCI_SS_HIGH_SPEED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) goto disable_hs_src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) disable_hs_src:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) clk_disable_unprepare(tegra->hs_src_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) disable_fs_src:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) clk_disable_unprepare(tegra->fs_src_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) disable_falc:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) clk_disable_unprepare(tegra->falcon_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) disable_ss:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) clk_disable_unprepare(tegra->ss_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) disable_host:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) clk_disable_unprepare(tegra->host_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) disable_plle:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) clk_disable_unprepare(tegra->pll_e);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) static void tegra_xusb_clk_disable(struct tegra_xusb *tegra)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) clk_disable_unprepare(tegra->pll_e);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) clk_disable_unprepare(tegra->host_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) clk_disable_unprepare(tegra->ss_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) clk_disable_unprepare(tegra->falcon_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) clk_disable_unprepare(tegra->fs_src_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) clk_disable_unprepare(tegra->hs_src_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) static int tegra_xusb_phy_enable(struct tegra_xusb *tegra)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) for (i = 0; i < tegra->num_phys; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) err = phy_init(tegra->phys[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) goto disable_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) err = phy_power_on(tegra->phys[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) phy_exit(tegra->phys[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) goto disable_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) disable_phy:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) while (i--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) phy_power_off(tegra->phys[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) phy_exit(tegra->phys[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) static void tegra_xusb_phy_disable(struct tegra_xusb *tegra)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) for (i = 0; i < tegra->num_phys; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) phy_power_off(tegra->phys[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) phy_exit(tegra->phys[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) static int tegra_xusb_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) struct tegra_xusb *tegra = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) regulator_bulk_disable(tegra->soc->num_supplies, tegra->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) tegra_xusb_clk_disable(tegra);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) static int tegra_xusb_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) struct tegra_xusb *tegra = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) err = tegra_xusb_clk_enable(tegra);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) dev_err(dev, "failed to enable clocks: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) err = regulator_bulk_enable(tegra->soc->num_supplies, tegra->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) dev_err(dev, "failed to enable regulators: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) goto disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) disable_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) tegra_xusb_clk_disable(tegra);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) static int tegra_xusb_init_context(struct tegra_xusb *tegra)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) const struct tegra_xusb_context_soc *soc = tegra->soc->context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) tegra->context.ipfs = devm_kcalloc(tegra->dev, soc->ipfs.num_offsets,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) sizeof(u32), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) if (!tegra->context.ipfs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) tegra->context.fpci = devm_kcalloc(tegra->dev, soc->fpci.num_offsets,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) sizeof(u32), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) if (!tegra->context.fpci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) static inline int tegra_xusb_init_context(struct tegra_xusb *tegra)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) static int tegra_xusb_request_firmware(struct tegra_xusb *tegra)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) struct tegra_xusb_fw_header *header;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) const struct firmware *fw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) err = request_firmware(&fw, tegra->soc->firmware, tegra->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) dev_err(tegra->dev, "failed to request firmware: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) /* Load Falcon controller with its firmware. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) header = (struct tegra_xusb_fw_header *)fw->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) tegra->fw.size = le32_to_cpu(header->fwimg_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) tegra->fw.virt = dma_alloc_coherent(tegra->dev, tegra->fw.size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) &tegra->fw.phys, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) if (!tegra->fw.virt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) dev_err(tegra->dev, "failed to allocate memory for firmware\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) release_firmware(fw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) header = (struct tegra_xusb_fw_header *)tegra->fw.virt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) memcpy(tegra->fw.virt, fw->data, tegra->fw.size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) release_firmware(fw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) static int tegra_xusb_load_firmware(struct tegra_xusb *tegra)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) unsigned int code_tag_blocks, code_size_blocks, code_blocks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) struct xhci_cap_regs __iomem *cap = tegra->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) struct tegra_xusb_fw_header *header;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) struct device *dev = tegra->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) struct xhci_op_regs __iomem *op;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) unsigned long timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) time64_t timestamp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) struct tm time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) u64 address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) header = (struct tegra_xusb_fw_header *)tegra->fw.virt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) op = tegra->regs + HC_LENGTH(readl(&cap->hc_capbase));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) if (csb_readl(tegra, XUSB_CSB_MP_ILOAD_BASE_LO) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) dev_info(dev, "Firmware already loaded, Falcon state %#x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) csb_readl(tegra, XUSB_FALC_CPUCTL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) /* Program the size of DFI into ILOAD_ATTR. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) csb_writel(tegra, tegra->fw.size, XUSB_CSB_MP_ILOAD_ATTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) * Boot code of the firmware reads the ILOAD_BASE registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) * to get to the start of the DFI in system memory.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) address = tegra->fw.phys + sizeof(*header);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) csb_writel(tegra, address >> 32, XUSB_CSB_MP_ILOAD_BASE_HI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) csb_writel(tegra, address, XUSB_CSB_MP_ILOAD_BASE_LO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) /* Set BOOTPATH to 1 in APMAP. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) csb_writel(tegra, APMAP_BOOTPATH, XUSB_CSB_MP_APMAP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) /* Invalidate L2IMEM. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) csb_writel(tegra, L2IMEMOP_INVALIDATE_ALL, XUSB_CSB_MP_L2IMEMOP_TRIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) * Initiate fetch of bootcode from system memory into L2IMEM.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) * Program bootcode location and size in system memory.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) code_tag_blocks = DIV_ROUND_UP(le32_to_cpu(header->boot_codetag),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) IMEM_BLOCK_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) code_size_blocks = DIV_ROUND_UP(le32_to_cpu(header->boot_codesize),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) IMEM_BLOCK_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) code_blocks = code_tag_blocks + code_size_blocks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) value = ((code_tag_blocks & L2IMEMOP_SIZE_SRC_OFFSET_MASK) <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) L2IMEMOP_SIZE_SRC_OFFSET_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) ((code_size_blocks & L2IMEMOP_SIZE_SRC_COUNT_MASK) <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) L2IMEMOP_SIZE_SRC_COUNT_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) csb_writel(tegra, value, XUSB_CSB_MP_L2IMEMOP_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) /* Trigger L2IMEM load operation. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) csb_writel(tegra, L2IMEMOP_LOAD_LOCKED_RESULT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) XUSB_CSB_MP_L2IMEMOP_TRIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) /* Setup Falcon auto-fill. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) csb_writel(tegra, code_size_blocks, XUSB_FALC_IMFILLCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) value = ((code_tag_blocks & IMFILLRNG1_TAG_MASK) <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) IMFILLRNG1_TAG_LO_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) ((code_blocks & IMFILLRNG1_TAG_MASK) <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) IMFILLRNG1_TAG_HI_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) csb_writel(tegra, value, XUSB_FALC_IMFILLRNG1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) csb_writel(tegra, 0, XUSB_FALC_DMACTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) /* wait for RESULT_VLD to get set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) #define tegra_csb_readl(offset) csb_readl(tegra, offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) err = readx_poll_timeout(tegra_csb_readl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) XUSB_CSB_MEMPOOL_L2IMEMOP_RESULT, value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) value & L2IMEMOP_RESULT_VLD, 100, 10000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) dev_err(dev, "DMA controller not ready %#010x\n", value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) #undef tegra_csb_readl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) csb_writel(tegra, le32_to_cpu(header->boot_codetag),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) XUSB_FALC_BOOTVEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) /* Boot Falcon CPU and wait for USBSTS_CNR to get cleared. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) csb_writel(tegra, CPUCTL_STARTCPU, XUSB_FALC_CPUCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) timeout = jiffies + msecs_to_jiffies(200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) value = readl(&op->status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) if ((value & STS_CNR) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) usleep_range(1000, 2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) } while (time_is_after_jiffies(timeout));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) value = readl(&op->status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) if (value & STS_CNR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) value = csb_readl(tegra, XUSB_FALC_CPUCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) dev_err(dev, "XHCI controller not read: %#010x\n", value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) timestamp = le32_to_cpu(header->fwimg_created_time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) time64_to_tm(timestamp, 0, &time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) dev_info(dev, "Firmware timestamp: %ld-%02d-%02d %02d:%02d:%02d UTC\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) time.tm_year + 1900, time.tm_mon + 1, time.tm_mday,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) time.tm_hour, time.tm_min, time.tm_sec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) static void tegra_xusb_powerdomain_remove(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) struct tegra_xusb *tegra)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) if (tegra->genpd_dl_ss)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) device_link_del(tegra->genpd_dl_ss);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) if (tegra->genpd_dl_host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) device_link_del(tegra->genpd_dl_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) if (!IS_ERR_OR_NULL(tegra->genpd_dev_ss))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) dev_pm_domain_detach(tegra->genpd_dev_ss, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) if (!IS_ERR_OR_NULL(tegra->genpd_dev_host))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) dev_pm_domain_detach(tegra->genpd_dev_host, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) static int tegra_xusb_powerdomain_init(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) struct tegra_xusb *tegra)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) tegra->genpd_dev_host = dev_pm_domain_attach_by_name(dev, "xusb_host");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) if (IS_ERR(tegra->genpd_dev_host)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) err = PTR_ERR(tegra->genpd_dev_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) dev_err(dev, "failed to get host pm-domain: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) tegra->genpd_dev_ss = dev_pm_domain_attach_by_name(dev, "xusb_ss");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) if (IS_ERR(tegra->genpd_dev_ss)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) err = PTR_ERR(tegra->genpd_dev_ss);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) dev_err(dev, "failed to get superspeed pm-domain: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) tegra->genpd_dl_host = device_link_add(dev, tegra->genpd_dev_host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) DL_FLAG_PM_RUNTIME |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) DL_FLAG_STATELESS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) if (!tegra->genpd_dl_host) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) dev_err(dev, "adding host device link failed!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) tegra->genpd_dl_ss = device_link_add(dev, tegra->genpd_dev_ss,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) DL_FLAG_PM_RUNTIME |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) DL_FLAG_STATELESS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) if (!tegra->genpd_dl_ss) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) dev_err(dev, "adding superspeed device link failed!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) static int __tegra_xusb_enable_firmware_messages(struct tegra_xusb *tegra)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) struct tegra_xusb_mbox_msg msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) /* Enable firmware messages from controller. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) msg.cmd = MBOX_CMD_MSG_ENABLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) msg.data = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) err = tegra_xusb_mbox_send(tegra, &msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) dev_err(tegra->dev, "failed to enable messages: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) static int tegra_xusb_enable_firmware_messages(struct tegra_xusb *tegra)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) mutex_lock(&tegra->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) err = __tegra_xusb_enable_firmware_messages(tegra);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) mutex_unlock(&tegra->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) static void tegra_xhci_set_port_power(struct tegra_xusb *tegra, bool main,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) bool set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) struct xhci_hcd *xhci = hcd_to_xhci(tegra->hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) struct usb_hcd *hcd = main ? xhci->main_hcd : xhci->shared_hcd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) unsigned int wait = (!main && !set) ? 1000 : 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) u16 typeReq = set ? SetPortFeature : ClearPortFeature;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) u16 wIndex = main ? tegra->otg_usb2_port + 1 : tegra->otg_usb3_port + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) u32 stat_power = main ? USB_PORT_STAT_POWER : USB_SS_PORT_STAT_POWER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) u32 status_val = set ? stat_power : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) dev_dbg(tegra->dev, "%s():%s %s port power\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) set ? "set" : "clear", main ? "HS" : "SS");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) hcd->driver->hub_control(hcd, typeReq, USB_PORT_FEAT_POWER, wIndex,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) tegra_xhci_hc_driver.hub_control(hcd, GetPortStatus, 0, wIndex,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) (char *) &status, sizeof(status));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) if (status_val == (status & stat_power))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) if (!main && !set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) usleep_range(600, 700);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) usleep_range(10, 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) } while (--wait > 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) if (status_val != (status & stat_power))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) dev_info(tegra->dev, "failed to %s %s PP %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) set ? "set" : "clear",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) main ? "HS" : "SS", status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) static struct phy *tegra_xusb_get_phy(struct tegra_xusb *tegra, char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) int port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) unsigned int i, phy_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) for (i = 0; i < tegra->soc->num_types; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) if (!strncmp(tegra->soc->phy_types[i].name, name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) strlen(name)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) return tegra->phys[phy_count+port];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) phy_count += tegra->soc->phy_types[i].num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) static void tegra_xhci_id_work(struct work_struct *work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) struct tegra_xusb *tegra = container_of(work, struct tegra_xusb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) id_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) struct xhci_hcd *xhci = hcd_to_xhci(tegra->hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) struct tegra_xusb_mbox_msg msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) struct phy *phy = tegra_xusb_get_phy(tegra, "usb2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) tegra->otg_usb2_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) dev_dbg(tegra->dev, "host mode %s\n", tegra->host_mode ? "on" : "off");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) mutex_lock(&tegra->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) if (tegra->host_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) phy_set_mode_ext(phy, PHY_MODE_USB_OTG, USB_ROLE_HOST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) phy_set_mode_ext(phy, PHY_MODE_USB_OTG, USB_ROLE_NONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) mutex_unlock(&tegra->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) if (tegra->host_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) /* switch to host mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) if (tegra->otg_usb3_port >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) if (tegra->soc->otg_reset_sspi) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) /* set PP=0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) tegra_xhci_hc_driver.hub_control(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) xhci->shared_hcd, GetPortStatus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) 0, tegra->otg_usb3_port+1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) (char *) &status, sizeof(status));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) if (status & USB_SS_PORT_STAT_POWER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) tegra_xhci_set_port_power(tegra, false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) /* reset OTG port SSPI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) msg.cmd = MBOX_CMD_RESET_SSPI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) msg.data = tegra->otg_usb3_port+1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) ret = tegra_xusb_mbox_send(tegra, &msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) dev_info(tegra->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) "failed to RESET_SSPI %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) tegra_xhci_set_port_power(tegra, false, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) tegra_xhci_set_port_power(tegra, true, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) if (tegra->otg_usb3_port >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) tegra_xhci_set_port_power(tegra, false, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) tegra_xhci_set_port_power(tegra, true, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) static int tegra_xusb_get_usb2_port(struct tegra_xusb *tegra,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) struct usb_phy *usbphy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) for (i = 0; i < tegra->num_usb_phys; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) if (tegra->usbphy[i] && usbphy == tegra->usbphy[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) return i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) static int tegra_xhci_id_notify(struct notifier_block *nb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) unsigned long action, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) struct tegra_xusb *tegra = container_of(nb, struct tegra_xusb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) id_nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) struct usb_phy *usbphy = (struct usb_phy *)data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) dev_dbg(tegra->dev, "%s(): action is %d", __func__, usbphy->last_event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) if ((tegra->host_mode && usbphy->last_event == USB_EVENT_ID) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) (!tegra->host_mode && usbphy->last_event != USB_EVENT_ID)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) dev_dbg(tegra->dev, "Same role(%d) received. Ignore",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) tegra->host_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) return NOTIFY_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) tegra->otg_usb2_port = tegra_xusb_get_usb2_port(tegra, usbphy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) tegra->otg_usb3_port = tegra_xusb_padctl_get_usb3_companion(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) tegra->padctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) tegra->otg_usb2_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) tegra->host_mode = (usbphy->last_event == USB_EVENT_ID) ? true : false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) schedule_work(&tegra->id_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) return NOTIFY_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) static int tegra_xusb_init_usb_phy(struct tegra_xusb *tegra)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) tegra->usbphy = devm_kcalloc(tegra->dev, tegra->num_usb_phys,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) sizeof(*tegra->usbphy), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) if (!tegra->usbphy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) INIT_WORK(&tegra->id_work, tegra_xhci_id_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) tegra->id_nb.notifier_call = tegra_xhci_id_notify;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) tegra->otg_usb2_port = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) tegra->otg_usb3_port = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) for (i = 0; i < tegra->num_usb_phys; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) struct phy *phy = tegra_xusb_get_phy(tegra, "usb2", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) if (!phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) tegra->usbphy[i] = devm_usb_get_phy_by_node(tegra->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) phy->dev.of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) &tegra->id_nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) if (!IS_ERR(tegra->usbphy[i])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) dev_dbg(tegra->dev, "usbphy-%d registered", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) otg_set_host(tegra->usbphy[i]->otg, &tegra->hcd->self);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) * usb-phy is optional, continue if its not available.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) tegra->usbphy[i] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) static void tegra_xusb_deinit_usb_phy(struct tegra_xusb *tegra)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) cancel_work_sync(&tegra->id_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) for (i = 0; i < tegra->num_usb_phys; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) if (tegra->usbphy[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) otg_set_host(tegra->usbphy[i]->otg, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) static int tegra_xusb_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) struct tegra_xusb *tegra;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) struct resource *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) struct xhci_hcd *xhci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) unsigned int i, j, k;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) struct phy *phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) BUILD_BUG_ON(sizeof(struct tegra_xusb_fw_header) != 256);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) tegra = devm_kzalloc(&pdev->dev, sizeof(*tegra), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) if (!tegra)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) tegra->soc = of_device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) mutex_init(&tegra->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) tegra->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) err = tegra_xusb_init_context(tegra);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) tegra->regs = devm_ioremap_resource(&pdev->dev, regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) if (IS_ERR(tegra->regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) return PTR_ERR(tegra->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) tegra->fpci_base = devm_platform_ioremap_resource(pdev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) if (IS_ERR(tegra->fpci_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) return PTR_ERR(tegra->fpci_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) if (tegra->soc->has_ipfs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) tegra->ipfs_base = devm_platform_ioremap_resource(pdev, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) if (IS_ERR(tegra->ipfs_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) return PTR_ERR(tegra->ipfs_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) tegra->xhci_irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) if (tegra->xhci_irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) return tegra->xhci_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) tegra->mbox_irq = platform_get_irq(pdev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) if (tegra->mbox_irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) return tegra->mbox_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) tegra->padctl = tegra_xusb_padctl_get(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) if (IS_ERR(tegra->padctl))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) return PTR_ERR(tegra->padctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) tegra->host_clk = devm_clk_get(&pdev->dev, "xusb_host");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) if (IS_ERR(tegra->host_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) err = PTR_ERR(tegra->host_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) dev_err(&pdev->dev, "failed to get xusb_host: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) goto put_padctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) tegra->falcon_clk = devm_clk_get(&pdev->dev, "xusb_falcon_src");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) if (IS_ERR(tegra->falcon_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) err = PTR_ERR(tegra->falcon_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) dev_err(&pdev->dev, "failed to get xusb_falcon_src: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) goto put_padctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) tegra->ss_clk = devm_clk_get(&pdev->dev, "xusb_ss");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) if (IS_ERR(tegra->ss_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) err = PTR_ERR(tegra->ss_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) dev_err(&pdev->dev, "failed to get xusb_ss: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) goto put_padctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) tegra->ss_src_clk = devm_clk_get(&pdev->dev, "xusb_ss_src");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) if (IS_ERR(tegra->ss_src_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) err = PTR_ERR(tegra->ss_src_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) dev_err(&pdev->dev, "failed to get xusb_ss_src: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) goto put_padctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) tegra->hs_src_clk = devm_clk_get(&pdev->dev, "xusb_hs_src");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) if (IS_ERR(tegra->hs_src_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) err = PTR_ERR(tegra->hs_src_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) dev_err(&pdev->dev, "failed to get xusb_hs_src: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) goto put_padctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) tegra->fs_src_clk = devm_clk_get(&pdev->dev, "xusb_fs_src");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) if (IS_ERR(tegra->fs_src_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) err = PTR_ERR(tegra->fs_src_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) dev_err(&pdev->dev, "failed to get xusb_fs_src: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) goto put_padctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) tegra->pll_u_480m = devm_clk_get(&pdev->dev, "pll_u_480m");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) if (IS_ERR(tegra->pll_u_480m)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) err = PTR_ERR(tegra->pll_u_480m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) dev_err(&pdev->dev, "failed to get pll_u_480m: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) goto put_padctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) tegra->clk_m = devm_clk_get(&pdev->dev, "clk_m");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) if (IS_ERR(tegra->clk_m)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) err = PTR_ERR(tegra->clk_m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) dev_err(&pdev->dev, "failed to get clk_m: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) goto put_padctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) tegra->pll_e = devm_clk_get(&pdev->dev, "pll_e");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) if (IS_ERR(tegra->pll_e)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) err = PTR_ERR(tegra->pll_e);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) dev_err(&pdev->dev, "failed to get pll_e: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) goto put_padctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) if (!of_property_read_bool(pdev->dev.of_node, "power-domains")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) tegra->host_rst = devm_reset_control_get(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) "xusb_host");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) if (IS_ERR(tegra->host_rst)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) err = PTR_ERR(tegra->host_rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) "failed to get xusb_host reset: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) goto put_padctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) tegra->ss_rst = devm_reset_control_get(&pdev->dev, "xusb_ss");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) if (IS_ERR(tegra->ss_rst)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) err = PTR_ERR(tegra->ss_rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) dev_err(&pdev->dev, "failed to get xusb_ss reset: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) goto put_padctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_XUSBA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) tegra->ss_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) tegra->ss_rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) "failed to enable XUSBA domain: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) goto put_padctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_XUSBC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) tegra->host_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) tegra->host_rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) tegra_powergate_power_off(TEGRA_POWERGATE_XUSBA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) "failed to enable XUSBC domain: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) goto put_padctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) err = tegra_xusb_powerdomain_init(&pdev->dev, tegra);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) goto put_powerdomains;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) tegra->supplies = devm_kcalloc(&pdev->dev, tegra->soc->num_supplies,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) sizeof(*tegra->supplies), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) if (!tegra->supplies) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) goto put_powerdomains;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) regulator_bulk_set_supply_names(tegra->supplies,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) tegra->soc->supply_names,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) tegra->soc->num_supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) err = devm_regulator_bulk_get(&pdev->dev, tegra->soc->num_supplies,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) tegra->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) dev_err(&pdev->dev, "failed to get regulators: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) goto put_powerdomains;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) for (i = 0; i < tegra->soc->num_types; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) if (!strncmp(tegra->soc->phy_types[i].name, "usb2", 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) tegra->num_usb_phys = tegra->soc->phy_types[i].num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) tegra->num_phys += tegra->soc->phy_types[i].num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) tegra->phys = devm_kcalloc(&pdev->dev, tegra->num_phys,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) sizeof(*tegra->phys), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) if (!tegra->phys) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) goto put_powerdomains;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) for (i = 0, k = 0; i < tegra->soc->num_types; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) char prop[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) for (j = 0; j < tegra->soc->phy_types[i].num; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) snprintf(prop, sizeof(prop), "%s-%d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) tegra->soc->phy_types[i].name, j);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) phy = devm_phy_optional_get(&pdev->dev, prop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) if (IS_ERR(phy)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) "failed to get PHY %s: %ld\n", prop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) PTR_ERR(phy));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) err = PTR_ERR(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) goto put_powerdomains;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) tegra->phys[k++] = phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) tegra->hcd = usb_create_hcd(&tegra_xhci_hc_driver, &pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) dev_name(&pdev->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) if (!tegra->hcd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) goto put_powerdomains;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) tegra->hcd->regs = tegra->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) tegra->hcd->rsrc_start = regs->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) tegra->hcd->rsrc_len = resource_size(regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) * This must happen after usb_create_hcd(), because usb_create_hcd()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) * will overwrite the drvdata of the device with the hcd it creates.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) platform_set_drvdata(pdev, tegra);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) err = tegra_xusb_phy_enable(tegra);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) dev_err(&pdev->dev, "failed to enable PHYs: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) goto put_hcd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) * The XUSB Falcon microcontroller can only address 40 bits, so set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) * the DMA mask accordingly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) err = dma_set_mask_and_coherent(tegra->dev, DMA_BIT_MASK(40));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) dev_err(&pdev->dev, "failed to set DMA mask: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) goto disable_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) err = tegra_xusb_request_firmware(tegra);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) dev_err(&pdev->dev, "failed to request firmware: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) goto disable_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) pm_runtime_enable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) if (!pm_runtime_enabled(&pdev->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) err = tegra_xusb_runtime_resume(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) err = pm_runtime_get_sync(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) dev_err(&pdev->dev, "failed to enable device: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) goto free_firmware;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) tegra_xusb_config(tegra);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) err = tegra_xusb_load_firmware(tegra);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) dev_err(&pdev->dev, "failed to load firmware: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) goto put_rpm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) err = usb_add_hcd(tegra->hcd, tegra->xhci_irq, IRQF_SHARED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) dev_err(&pdev->dev, "failed to add USB HCD: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) goto put_rpm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) device_wakeup_enable(tegra->hcd->self.controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) xhci = hcd_to_xhci(tegra->hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) xhci->shared_hcd = usb_create_shared_hcd(&tegra_xhci_hc_driver,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) &pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) dev_name(&pdev->dev),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) tegra->hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) if (!xhci->shared_hcd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) dev_err(&pdev->dev, "failed to create shared HCD\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) goto remove_usb2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) err = usb_add_hcd(xhci->shared_hcd, tegra->xhci_irq, IRQF_SHARED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) dev_err(&pdev->dev, "failed to add shared HCD: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) goto put_usb3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) err = tegra_xusb_enable_firmware_messages(tegra);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) dev_err(&pdev->dev, "failed to enable messages: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) goto remove_usb3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) err = devm_request_threaded_irq(&pdev->dev, tegra->mbox_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) tegra_xusb_mbox_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) tegra_xusb_mbox_thread, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) dev_name(&pdev->dev), tegra);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) dev_err(&pdev->dev, "failed to request IRQ: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) goto remove_usb3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) err = tegra_xusb_init_usb_phy(tegra);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) dev_err(&pdev->dev, "failed to init USB PHY: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) goto remove_usb3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) remove_usb3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) usb_remove_hcd(xhci->shared_hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) put_usb3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) usb_put_hcd(xhci->shared_hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) remove_usb2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) usb_remove_hcd(tegra->hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) put_rpm:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) if (!pm_runtime_status_suspended(&pdev->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) tegra_xusb_runtime_suspend(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) put_hcd:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) usb_put_hcd(tegra->hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) free_firmware:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) dma_free_coherent(&pdev->dev, tegra->fw.size, tegra->fw.virt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) tegra->fw.phys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) disable_phy:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) tegra_xusb_phy_disable(tegra);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) put_powerdomains:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) if (!of_property_read_bool(pdev->dev.of_node, "power-domains")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) tegra_powergate_power_off(TEGRA_POWERGATE_XUSBC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) tegra_powergate_power_off(TEGRA_POWERGATE_XUSBA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) tegra_xusb_powerdomain_remove(&pdev->dev, tegra);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) put_padctl:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) tegra_xusb_padctl_put(tegra->padctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) static int tegra_xusb_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) struct tegra_xusb *tegra = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) struct xhci_hcd *xhci = hcd_to_xhci(tegra->hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) tegra_xusb_deinit_usb_phy(tegra);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) usb_remove_hcd(xhci->shared_hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) usb_put_hcd(xhci->shared_hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) xhci->shared_hcd = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) usb_remove_hcd(tegra->hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) usb_put_hcd(tegra->hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) dma_free_coherent(&pdev->dev, tegra->fw.size, tegra->fw.virt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) tegra->fw.phys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) pm_runtime_put_sync(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) if (!of_property_read_bool(pdev->dev.of_node, "power-domains")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) tegra_powergate_power_off(TEGRA_POWERGATE_XUSBC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) tegra_powergate_power_off(TEGRA_POWERGATE_XUSBA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) tegra_xusb_powerdomain_remove(&pdev->dev, tegra);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) tegra_xusb_phy_disable(tegra);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) tegra_xusb_padctl_put(tegra->padctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) static bool xhci_hub_ports_suspended(struct xhci_hub *hub)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) struct device *dev = hub->hcd->self.controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) bool status = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) for (i = 0; i < hub->num_ports; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) value = readl(hub->ports[i]->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) if ((value & PORT_PE) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) if ((value & PORT_PLS_MASK) != XDEV_U3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) dev_info(dev, "%u-%u isn't suspended: %#010x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) hub->hcd->self.busnum, i + 1, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) status = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) static int tegra_xusb_check_ports(struct tegra_xusb *tegra)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) struct xhci_hcd *xhci = hcd_to_xhci(tegra->hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) spin_lock_irqsave(&xhci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) if (!xhci_hub_ports_suspended(&xhci->usb2_rhub) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) !xhci_hub_ports_suspended(&xhci->usb3_rhub))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) err = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) spin_unlock_irqrestore(&xhci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) static void tegra_xusb_save_context(struct tegra_xusb *tegra)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) const struct tegra_xusb_context_soc *soc = tegra->soc->context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) struct tegra_xusb_context *ctx = &tegra->context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) if (soc->ipfs.num_offsets > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) for (i = 0; i < soc->ipfs.num_offsets; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) ctx->ipfs[i] = ipfs_readl(tegra, soc->ipfs.offsets[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) if (soc->fpci.num_offsets > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) for (i = 0; i < soc->fpci.num_offsets; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) ctx->fpci[i] = fpci_readl(tegra, soc->fpci.offsets[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) static void tegra_xusb_restore_context(struct tegra_xusb *tegra)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) const struct tegra_xusb_context_soc *soc = tegra->soc->context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) struct tegra_xusb_context *ctx = &tegra->context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) if (soc->fpci.num_offsets > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) for (i = 0; i < soc->fpci.num_offsets; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) fpci_writel(tegra, ctx->fpci[i], soc->fpci.offsets[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) if (soc->ipfs.num_offsets > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) for (i = 0; i < soc->ipfs.num_offsets; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) ipfs_writel(tegra, ctx->ipfs[i], soc->ipfs.offsets[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) static int tegra_xusb_enter_elpg(struct tegra_xusb *tegra, bool wakeup)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) struct xhci_hcd *xhci = hcd_to_xhci(tegra->hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) err = tegra_xusb_check_ports(tegra);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) dev_err(tegra->dev, "not all ports suspended: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) err = xhci_suspend(xhci, wakeup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) dev_err(tegra->dev, "failed to suspend XHCI: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) tegra_xusb_save_context(tegra);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) tegra_xusb_phy_disable(tegra);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) tegra_xusb_clk_disable(tegra);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) static int tegra_xusb_exit_elpg(struct tegra_xusb *tegra, bool wakeup)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) struct xhci_hcd *xhci = hcd_to_xhci(tegra->hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) err = tegra_xusb_clk_enable(tegra);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) dev_err(tegra->dev, "failed to enable clocks: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) err = tegra_xusb_phy_enable(tegra);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) dev_err(tegra->dev, "failed to enable PHYs: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) goto disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) tegra_xusb_config(tegra);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) tegra_xusb_restore_context(tegra);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) err = tegra_xusb_load_firmware(tegra);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) dev_err(tegra->dev, "failed to load firmware: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) goto disable_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) err = __tegra_xusb_enable_firmware_messages(tegra);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) dev_err(tegra->dev, "failed to enable messages: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) goto disable_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) err = xhci_resume(xhci, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) dev_err(tegra->dev, "failed to resume XHCI: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) goto disable_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) disable_phy:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) tegra_xusb_phy_disable(tegra);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) disable_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) tegra_xusb_clk_disable(tegra);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) static int tegra_xusb_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) struct tegra_xusb *tegra = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) bool wakeup = device_may_wakeup(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) synchronize_irq(tegra->mbox_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) mutex_lock(&tegra->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) err = tegra_xusb_enter_elpg(tegra, wakeup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) mutex_unlock(&tegra->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) static int tegra_xusb_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) struct tegra_xusb *tegra = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) bool wakeup = device_may_wakeup(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) mutex_lock(&tegra->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) err = tegra_xusb_exit_elpg(tegra, wakeup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) mutex_unlock(&tegra->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) static const struct dev_pm_ops tegra_xusb_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) SET_RUNTIME_PM_OPS(tegra_xusb_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) tegra_xusb_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) SET_SYSTEM_SLEEP_PM_OPS(tegra_xusb_suspend, tegra_xusb_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) static const char * const tegra124_supply_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) "avddio-pex",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) "dvddio-pex",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) "avdd-usb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) "hvdd-usb-ss",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) static const struct tegra_xusb_phy_type tegra124_phy_types[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) { .name = "usb3", .num = 2, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) { .name = "usb2", .num = 3, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) { .name = "hsic", .num = 2, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) static const unsigned int tegra124_xusb_context_ipfs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) IPFS_XUSB_HOST_MSI_BAR_SZ_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) IPFS_XUSB_HOST_MSI_AXI_BAR_ST_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) IPFS_XUSB_HOST_MSI_FPCI_BAR_ST_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) IPFS_XUSB_HOST_MSI_VEC0_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) IPFS_XUSB_HOST_MSI_EN_VEC0_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) IPFS_XUSB_HOST_FPCI_ERROR_MASKS_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) IPFS_XUSB_HOST_INTR_MASK_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) IPFS_XUSB_HOST_INTR_ENABLE_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) IPFS_XUSB_HOST_UFPCI_CONFIG_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) IPFS_XUSB_HOST_CLKGATE_HYSTERESIS_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) IPFS_XUSB_HOST_MCCIF_FIFOCTRL_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) static const unsigned int tegra124_xusb_context_fpci[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) XUSB_CFG_ARU_CONTEXT_HS_PLS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) XUSB_CFG_ARU_CONTEXT_FS_PLS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) XUSB_CFG_ARU_CONTEXT_HSFS_SPEED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) XUSB_CFG_ARU_CONTEXT_HSFS_PP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) XUSB_CFG_ARU_CONTEXT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) XUSB_CFG_AXI_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) XUSB_CFG_24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) XUSB_CFG_16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) static const struct tegra_xusb_context_soc tegra124_xusb_context = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) .ipfs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) .num_offsets = ARRAY_SIZE(tegra124_xusb_context_ipfs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) .offsets = tegra124_xusb_context_ipfs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) .fpci = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) .num_offsets = ARRAY_SIZE(tegra124_xusb_context_fpci),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) .offsets = tegra124_xusb_context_fpci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) static const struct tegra_xusb_soc tegra124_soc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) .firmware = "nvidia/tegra124/xusb.bin",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) .supply_names = tegra124_supply_names,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) .num_supplies = ARRAY_SIZE(tegra124_supply_names),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) .phy_types = tegra124_phy_types,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) .num_types = ARRAY_SIZE(tegra124_phy_types),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) .context = &tegra124_xusb_context,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) .ports = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) .usb2 = { .offset = 4, .count = 4, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) .hsic = { .offset = 6, .count = 2, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) .usb3 = { .offset = 0, .count = 2, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) .scale_ss_clock = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) .has_ipfs = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) .otg_reset_sspi = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) .mbox = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) .cmd = 0xe4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) .data_in = 0xe8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) .data_out = 0xec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) .owner = 0xf0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) MODULE_FIRMWARE("nvidia/tegra124/xusb.bin");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) static const char * const tegra210_supply_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) "dvddio-pex",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) "hvddio-pex",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) "avdd-usb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) static const struct tegra_xusb_phy_type tegra210_phy_types[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) { .name = "usb3", .num = 4, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) { .name = "usb2", .num = 4, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) { .name = "hsic", .num = 1, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) static const struct tegra_xusb_soc tegra210_soc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) .firmware = "nvidia/tegra210/xusb.bin",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) .supply_names = tegra210_supply_names,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) .num_supplies = ARRAY_SIZE(tegra210_supply_names),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) .phy_types = tegra210_phy_types,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) .num_types = ARRAY_SIZE(tegra210_phy_types),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) .context = &tegra124_xusb_context,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) .ports = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) .usb2 = { .offset = 4, .count = 4, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) .hsic = { .offset = 8, .count = 1, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) .usb3 = { .offset = 0, .count = 4, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) .scale_ss_clock = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) .has_ipfs = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) .otg_reset_sspi = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) .mbox = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) .cmd = 0xe4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) .data_in = 0xe8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) .data_out = 0xec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) .owner = 0xf0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) MODULE_FIRMWARE("nvidia/tegra210/xusb.bin");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) static const char * const tegra186_supply_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) MODULE_FIRMWARE("nvidia/tegra186/xusb.bin");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) static const struct tegra_xusb_phy_type tegra186_phy_types[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) { .name = "usb3", .num = 3, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) { .name = "usb2", .num = 3, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) { .name = "hsic", .num = 1, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) static const struct tegra_xusb_context_soc tegra186_xusb_context = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) .fpci = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) .num_offsets = ARRAY_SIZE(tegra124_xusb_context_fpci),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) .offsets = tegra124_xusb_context_fpci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) static const struct tegra_xusb_soc tegra186_soc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) .firmware = "nvidia/tegra186/xusb.bin",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) .supply_names = tegra186_supply_names,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) .num_supplies = ARRAY_SIZE(tegra186_supply_names),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) .phy_types = tegra186_phy_types,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) .num_types = ARRAY_SIZE(tegra186_phy_types),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) .context = &tegra186_xusb_context,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) .ports = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) .usb3 = { .offset = 0, .count = 3, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) .usb2 = { .offset = 3, .count = 3, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) .hsic = { .offset = 6, .count = 1, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) .scale_ss_clock = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) .has_ipfs = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) .otg_reset_sspi = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) .mbox = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) .cmd = 0xe4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) .data_in = 0xe8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) .data_out = 0xec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) .owner = 0xf0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) .lpm_support = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) static const char * const tegra194_supply_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) static const struct tegra_xusb_phy_type tegra194_phy_types[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) { .name = "usb3", .num = 4, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) { .name = "usb2", .num = 4, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) static const struct tegra_xusb_soc tegra194_soc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) .firmware = "nvidia/tegra194/xusb.bin",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) .supply_names = tegra194_supply_names,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) .num_supplies = ARRAY_SIZE(tegra194_supply_names),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) .phy_types = tegra194_phy_types,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) .num_types = ARRAY_SIZE(tegra194_phy_types),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) .context = &tegra186_xusb_context,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) .ports = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) .usb3 = { .offset = 0, .count = 4, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) .usb2 = { .offset = 4, .count = 4, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) .scale_ss_clock = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) .has_ipfs = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) .otg_reset_sspi = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) .mbox = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) .cmd = 0x68,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) .data_in = 0x6c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) .data_out = 0x70,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) .owner = 0x74,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) .lpm_support = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) MODULE_FIRMWARE("nvidia/tegra194/xusb.bin");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) static const struct of_device_id tegra_xusb_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) { .compatible = "nvidia,tegra124-xusb", .data = &tegra124_soc },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) { .compatible = "nvidia,tegra210-xusb", .data = &tegra210_soc },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) { .compatible = "nvidia,tegra186-xusb", .data = &tegra186_soc },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) { .compatible = "nvidia,tegra194-xusb", .data = &tegra194_soc },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) MODULE_DEVICE_TABLE(of, tegra_xusb_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) static struct platform_driver tegra_xusb_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) .probe = tegra_xusb_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) .remove = tegra_xusb_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) .name = "tegra-xusb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) .pm = &tegra_xusb_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) .of_match_table = tegra_xusb_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) static void tegra_xhci_quirks(struct device *dev, struct xhci_hcd *xhci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) struct tegra_xusb *tegra = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) xhci->quirks |= XHCI_PLAT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) if (tegra && tegra->soc->lpm_support)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) xhci->quirks |= XHCI_LPM_SUPPORT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) static int tegra_xhci_setup(struct usb_hcd *hcd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) return xhci_gen_setup(hcd, tegra_xhci_quirks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) static const struct xhci_driver_overrides tegra_xhci_overrides __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) .reset = tegra_xhci_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) static int __init tegra_xusb_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) xhci_init_driver(&tegra_xhci_hc_driver, &tegra_xhci_overrides);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) return platform_driver_register(&tegra_xusb_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) module_init(tegra_xusb_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) static void __exit tegra_xusb_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) platform_driver_unregister(&tegra_xusb_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) module_exit(tegra_xusb_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) MODULE_AUTHOR("Andrew Bresticker <abrestic@chromium.org>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) MODULE_DESCRIPTION("NVIDIA Tegra XUSB xHCI host-controller driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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