^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * xHCI host controller driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2008 Intel Corp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author: Sarah Sharp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Some code borrowed from the Linux EHCI driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Ring initialization rules:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * 1. Each segment is initialized to zero, except for link TRBs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * 2. Ring cycle state = 0. This represents Producer Cycle State (PCS) or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * Consumer Cycle State (CCS), depending on ring function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * Ring behavior rules:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * 1. A ring is empty if enqueue == dequeue. This means there will always be at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * least one free TRB in the ring. This is useful if you want to turn that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * into a link TRB and expand the ring.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * link TRB, then load the pointer with the address in the link TRB. If the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * link TRB had its toggle bit set, you may need to update the ring cycle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * state (see cycle bit rules). You may have to do this multiple times
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * until you reach a non-link TRB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * 3. A ring is full if enqueue++ (for the definition of increment above)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * equals the dequeue pointer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * Cycle bit rules:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * 1. When a consumer increments a dequeue pointer and encounters a toggle bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * in a link TRB, it must toggle the ring cycle state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * 2. When a producer increments an enqueue pointer and encounters a toggle bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * in a link TRB, it must toggle the ring cycle state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * Producer rules:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * 1. Check if ring is full before you enqueue.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * Update enqueue pointer between each write (which may update the ring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * cycle state).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * 3. Notify consumer. If SW is producer, it rings the doorbell for command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * and endpoint rings. If HC is the producer for the event ring,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * and it generates an interrupt according to interrupt modulation rules.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * Consumer rules:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * 1. Check if TRB belongs to you. If the cycle bit == your ring cycle state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * the TRB is owned by the consumer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * 2. Update dequeue pointer (which may update the ring cycle state) and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * continue processing TRBs until you reach a TRB which is not owned by you.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * 3. Notify the producer. SW is the consumer for the event ring, and it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * updates event ring dequeue pointer. HC is the consumer for the command and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * endpoint rings; it generates events on the event ring for these.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #include <linux/scatterlist.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #include "xhci.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #include "xhci-trace.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) static int queue_command(struct xhci_hcd *xhci, struct xhci_command *cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) u32 field1, u32 field2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) u32 field3, u32 field4, bool command_must_succeed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * address of the TRB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) union xhci_trb *trb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) unsigned long segment_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) if (!seg || !trb || trb < seg->trbs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /* offset in TRBs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) segment_offset = trb - seg->trbs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) if (segment_offset >= TRBS_PER_SEGMENT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) return seg->dma + (segment_offset * sizeof(*trb));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) EXPORT_SYMBOL_GPL(xhci_trb_virt_to_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) static bool trb_is_noop(union xhci_trb *trb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) return TRB_TYPE_NOOP_LE32(trb->generic.field[3]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static bool trb_is_link(union xhci_trb *trb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) return TRB_TYPE_LINK_LE32(trb->link.control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) static bool last_trb_on_seg(struct xhci_segment *seg, union xhci_trb *trb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) return trb == &seg->trbs[TRBS_PER_SEGMENT - 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) static bool last_trb_on_ring(struct xhci_ring *ring,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) struct xhci_segment *seg, union xhci_trb *trb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) return last_trb_on_seg(seg, trb) && (seg->next == ring->first_seg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static bool link_trb_toggles_cycle(union xhci_trb *trb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) return le32_to_cpu(trb->link.control) & LINK_TOGGLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static bool last_td_in_urb(struct xhci_td *td)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) struct urb_priv *urb_priv = td->urb->hcpriv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) return urb_priv->num_tds_done == urb_priv->num_tds;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static void inc_td_cnt(struct urb *urb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) struct urb_priv *urb_priv = urb->hcpriv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) urb_priv->num_tds_done++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static void trb_to_noop(union xhci_trb *trb, u32 noop_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) if (trb_is_link(trb)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /* unchain chained link TRBs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) trb->link.control &= cpu_to_le32(~TRB_CHAIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) trb->generic.field[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) trb->generic.field[1] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) trb->generic.field[2] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /* Preserve only the cycle bit of this TRB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) trb->generic.field[3] &= cpu_to_le32(TRB_CYCLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) trb->generic.field[3] |= cpu_to_le32(TRB_TYPE(noop_type));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) /* Updates trb to point to the next TRB in the ring, and updates seg if the next
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) * TRB is in a new segment. This does not skip over link TRBs, and it does not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) * effect the ring dequeue or enqueue pointers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static void next_trb(struct xhci_hcd *xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct xhci_ring *ring,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) struct xhci_segment **seg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) union xhci_trb **trb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) if (trb_is_link(*trb)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) *seg = (*seg)->next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) *trb = ((*seg)->trbs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) (*trb)++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) * See Cycle bit rules. SW is the consumer for the event ring only.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) unsigned int link_trb_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) /* event ring doesn't have link trbs, check for last trb */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) if (ring->type == TYPE_EVENT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) if (!last_trb_on_seg(ring->deq_seg, ring->dequeue)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) ring->dequeue++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) if (last_trb_on_ring(ring, ring->deq_seg, ring->dequeue))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) ring->cycle_state ^= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) ring->deq_seg = ring->deq_seg->next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) ring->dequeue = ring->deq_seg->trbs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) /* All other rings have link trbs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) if (!trb_is_link(ring->dequeue)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) if (last_trb_on_seg(ring->deq_seg, ring->dequeue)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) xhci_warn(xhci, "Missing link TRB at end of segment\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) ring->dequeue++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) ring->num_trbs_free++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) while (trb_is_link(ring->dequeue)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) ring->deq_seg = ring->deq_seg->next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) ring->dequeue = ring->deq_seg->trbs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) if (link_trb_count++ > ring->num_segs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) xhci_warn(xhci, "Ring is an endless link TRB loop\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) trace_xhci_inc_deq(ring);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) * See Cycle bit rules. SW is the consumer for the event ring only.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) * If we've just enqueued a TRB that is in the middle of a TD (meaning the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) * chain bit is set), then set the chain bit in all the following link TRBs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) * If we've enqueued the last TRB in a TD, make sure the following link TRBs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) * have their chain bit cleared (so that each Link TRB is a separate TD).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) * set, but other sections talk about dealing with the chain bit set. This was
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) * fixed in the 0.96 specification errata, but we have to assume that all 0.95
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) * xHCI hardware can't handle the chain bit being cleared on a link TRB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) * @more_trbs_coming: Will you enqueue more TRBs before calling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) * prepare_transfer()?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) bool more_trbs_coming)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) u32 chain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) union xhci_trb *next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) unsigned int link_trb_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) chain = le32_to_cpu(ring->enqueue->generic.field[3]) & TRB_CHAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) /* If this is not event ring, there is one less usable TRB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) if (!trb_is_link(ring->enqueue))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) ring->num_trbs_free--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) if (last_trb_on_seg(ring->enq_seg, ring->enqueue)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) xhci_err(xhci, "Tried to move enqueue past ring segment\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) next = ++(ring->enqueue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) /* Update the dequeue pointer further if that was a link TRB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) while (trb_is_link(next)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) * If the caller doesn't plan on enqueueing more TDs before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) * ringing the doorbell, then we don't want to give the link TRB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) * to the hardware just yet. We'll give the link TRB back in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) * prepare_ring() just before we enqueue the TD at the top of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) * the ring.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) if (!chain && !more_trbs_coming)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) /* If we're not dealing with 0.95 hardware or isoc rings on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) * AMD 0.96 host, carry over the chain bit of the previous TRB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) * (which may mean the chain bit is cleared).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) if (!(ring->type == TYPE_ISOC &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) (xhci->quirks & XHCI_AMD_0x96_HOST)) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) !xhci_link_trb_quirk(xhci)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) next->link.control &= cpu_to_le32(~TRB_CHAIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) next->link.control |= cpu_to_le32(chain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) /* Give this link TRB to the hardware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) next->link.control ^= cpu_to_le32(TRB_CYCLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) /* Toggle the cycle bit after the last ring segment. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) if (link_trb_toggles_cycle(next))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) ring->cycle_state ^= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) ring->enq_seg = ring->enq_seg->next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) ring->enqueue = ring->enq_seg->trbs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) next = ring->enqueue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) if (link_trb_count++ > ring->num_segs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) xhci_warn(xhci, "%s: Ring link TRB loop\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) trace_xhci_inc_enq(ring);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) * Check to see if there's room to enqueue num_trbs on the ring and make sure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) * enqueue pointer will not advance into dequeue segment. See rules above.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) static inline int room_on_ring(struct xhci_hcd *xhci, struct xhci_ring *ring,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) unsigned int num_trbs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) int num_trbs_in_deq_seg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) if (ring->num_trbs_free < num_trbs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) if (ring->type != TYPE_COMMAND && ring->type != TYPE_EVENT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) num_trbs_in_deq_seg = ring->dequeue - ring->deq_seg->trbs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) if (ring->num_trbs_free < num_trbs + num_trbs_in_deq_seg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) /* Ring the host controller doorbell after placing a command on the ring */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) void xhci_ring_cmd_db(struct xhci_hcd *xhci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) if (!(xhci->cmd_ring_state & CMD_RING_STATE_RUNNING))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) xhci_dbg(xhci, "// Ding dong!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) trace_xhci_ring_host_doorbell(0, DB_VALUE_HOST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) writel(DB_VALUE_HOST, &xhci->dba->doorbell[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) /* Flush PCI posted writes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) readl(&xhci->dba->doorbell[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) EXPORT_SYMBOL_GPL(xhci_ring_cmd_db);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) static bool xhci_mod_cmd_timer(struct xhci_hcd *xhci, unsigned long delay)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) return mod_delayed_work(system_wq, &xhci->cmd_timer, delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) static struct xhci_command *xhci_next_queued_cmd(struct xhci_hcd *xhci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) return list_first_entry_or_null(&xhci->cmd_list, struct xhci_command,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) cmd_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) * Turn all commands on command ring with status set to "aborted" to no-op trbs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) * If there are other commands waiting then restart the ring and kick the timer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) * This must be called with command ring stopped and xhci->lock held.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) static void xhci_handle_stopped_cmd_ring(struct xhci_hcd *xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) struct xhci_command *cur_cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) struct xhci_command *i_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) /* Turn all aborted commands in list to no-ops, then restart */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) list_for_each_entry(i_cmd, &xhci->cmd_list, cmd_list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) if (i_cmd->status != COMP_COMMAND_ABORTED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) i_cmd->status = COMP_COMMAND_RING_STOPPED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) xhci_dbg(xhci, "Turn aborted command %p to no-op\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) i_cmd->command_trb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) trb_to_noop(i_cmd->command_trb, TRB_CMD_NOOP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) * caller waiting for completion is called when command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) * completion event is received for these no-op commands
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) xhci->cmd_ring_state = CMD_RING_STATE_RUNNING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) /* ring command ring doorbell to restart the command ring */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) if ((xhci->cmd_ring->dequeue != xhci->cmd_ring->enqueue) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) !(xhci->xhc_state & XHCI_STATE_DYING)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) xhci->current_cmd = cur_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) xhci_mod_cmd_timer(xhci, XHCI_CMD_DEFAULT_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) xhci_ring_cmd_db(xhci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) /* Must be called with xhci->lock held, releases and aquires lock back */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) static int xhci_abort_cmd_ring(struct xhci_hcd *xhci, unsigned long flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) struct xhci_segment *new_seg = xhci->cmd_ring->deq_seg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) union xhci_trb *new_deq = xhci->cmd_ring->dequeue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) u64 crcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) xhci_dbg(xhci, "Abort command ring\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) reinit_completion(&xhci->cmd_ring_stop_completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) * The control bits like command stop, abort are located in lower
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) * dword of the command ring control register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) * Some controllers require all 64 bits to be written to abort the ring.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) * Make sure the upper dword is valid, pointing to the next command,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) * avoiding corrupting the command ring pointer in case the command ring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) * is stopped by the time the upper dword is written.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) next_trb(xhci, NULL, &new_seg, &new_deq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) if (trb_is_link(new_deq))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) next_trb(xhci, NULL, &new_seg, &new_deq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) crcr = xhci_trb_virt_to_dma(new_seg, new_deq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) xhci_write_64(xhci, crcr | CMD_RING_ABORT, &xhci->op_regs->cmd_ring);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) /* Section 4.6.1.2 of xHCI 1.0 spec says software should also time the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) * completion of the Command Abort operation. If CRR is not negated in 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) * seconds then driver handles it as if host died (-ENODEV).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) * In the future we should distinguish between -ENODEV and -ETIMEDOUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) * and try to recover a -ETIMEDOUT with a host controller reset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) ret = xhci_handshake(&xhci->op_regs->cmd_ring,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) CMD_RING_RUNNING, 0, 5 * 1000 * 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) xhci_err(xhci, "Abort failed to stop command ring: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) xhci_halt(xhci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) xhci_hc_died(xhci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) * Writing the CMD_RING_ABORT bit should cause a cmd completion event,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) * however on some host hw the CMD_RING_RUNNING bit is correctly cleared
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) * but the completion event in never sent. Wait 2 secs (arbitrary
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) * number) to handle those cases after negation of CMD_RING_RUNNING.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) spin_unlock_irqrestore(&xhci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) ret = wait_for_completion_timeout(&xhci->cmd_ring_stop_completion,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) msecs_to_jiffies(2000));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) spin_lock_irqsave(&xhci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) xhci_dbg(xhci, "No stop event for abort, ring start fail?\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) xhci_cleanup_command_queue(xhci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) xhci_handle_stopped_cmd_ring(xhci, xhci_next_queued_cmd(xhci));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) void xhci_ring_ep_doorbell(struct xhci_hcd *xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) unsigned int slot_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) unsigned int ep_index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) unsigned int stream_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) __le32 __iomem *db_addr = &xhci->dba->doorbell[slot_id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) unsigned int ep_state = ep->ep_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) /* Don't ring the doorbell for this endpoint if there are pending
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) * cancellations because we don't want to interrupt processing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) * We don't want to restart any stream rings if there's a set dequeue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) * pointer command pending because the device can choose to start any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) * stream once the endpoint is on the HW schedule.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) if ((ep_state & EP_STOP_CMD_PENDING) || (ep_state & SET_DEQ_PENDING) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) (ep_state & EP_HALTED) || (ep_state & EP_CLEARING_TT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) trace_xhci_ring_ep_doorbell(slot_id, DB_VALUE(ep_index, stream_id));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) writel(DB_VALUE(ep_index, stream_id), db_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) /* flush the write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) readl(db_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) /* Ring the doorbell for any rings with pending URBs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) static void ring_doorbell_for_active_rings(struct xhci_hcd *xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) unsigned int slot_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) unsigned int ep_index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) unsigned int stream_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) struct xhci_virt_ep *ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) ep = &xhci->devs[slot_id]->eps[ep_index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) /* A ring has pending URBs if its TD list is not empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) if (!(ep->ep_state & EP_HAS_STREAMS)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) if (ep->ring && !(list_empty(&ep->ring->td_list)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) xhci_ring_ep_doorbell(xhci, slot_id, ep_index, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) for (stream_id = 1; stream_id < ep->stream_info->num_streams;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) stream_id++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) struct xhci_stream_info *stream_info = ep->stream_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) if (!list_empty(&stream_info->stream_rings[stream_id]->td_list))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) xhci_ring_ep_doorbell(xhci, slot_id, ep_index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) stream_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) void xhci_ring_doorbell_for_active_rings(struct xhci_hcd *xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) unsigned int slot_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) unsigned int ep_index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) static struct xhci_virt_ep *xhci_get_virt_ep(struct xhci_hcd *xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) unsigned int slot_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) unsigned int ep_index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) if (slot_id == 0 || slot_id >= MAX_HC_SLOTS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) xhci_warn(xhci, "Invalid slot_id %u\n", slot_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) if (ep_index >= EP_CTX_PER_DEV) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) xhci_warn(xhci, "Invalid endpoint index %u\n", ep_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) if (!xhci->devs[slot_id]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) xhci_warn(xhci, "No xhci virt device for slot_id %u\n", slot_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) return &xhci->devs[slot_id]->eps[ep_index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) static struct xhci_ring *xhci_virt_ep_to_ring(struct xhci_hcd *xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) struct xhci_virt_ep *ep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) unsigned int stream_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) /* common case, no streams */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) if (!(ep->ep_state & EP_HAS_STREAMS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) return ep->ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) if (!ep->stream_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) if (stream_id == 0 || stream_id >= ep->stream_info->num_streams) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) xhci_warn(xhci, "Invalid stream_id %u request for slot_id %u ep_index %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) stream_id, ep->vdev->slot_id, ep->ep_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) return ep->stream_info->stream_rings[stream_id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) /* Get the right ring for the given slot_id, ep_index and stream_id.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) * If the endpoint supports streams, boundary check the URB's stream ID.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) * If the endpoint doesn't support streams, return the singular endpoint ring.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) unsigned int slot_id, unsigned int ep_index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) unsigned int stream_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) struct xhci_virt_ep *ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) ep = xhci_get_virt_ep(xhci, slot_id, ep_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) if (!ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) return xhci_virt_ep_to_ring(xhci, ep, stream_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) * Get the hw dequeue pointer xHC stopped on, either directly from the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) * endpoint context, or if streams are in use from the stream context.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) * The returned hw_dequeue contains the lowest four bits with cycle state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) * and possbile stream context type.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) static u64 xhci_get_hw_deq(struct xhci_hcd *xhci, struct xhci_virt_device *vdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) unsigned int ep_index, unsigned int stream_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) struct xhci_ep_ctx *ep_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) struct xhci_stream_ctx *st_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) struct xhci_virt_ep *ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) ep = &vdev->eps[ep_index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) if (ep->ep_state & EP_HAS_STREAMS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) st_ctx = &ep->stream_info->stream_ctx_array[stream_id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) return le64_to_cpu(st_ctx->stream_ring);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) ep_ctx = xhci_get_ep_ctx(xhci, vdev->out_ctx, ep_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) return le64_to_cpu(ep_ctx->deq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) static int xhci_move_dequeue_past_td(struct xhci_hcd *xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) unsigned int slot_id, unsigned int ep_index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) unsigned int stream_id, struct xhci_td *td)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) struct xhci_virt_device *dev = xhci->devs[slot_id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) struct xhci_virt_ep *ep = &dev->eps[ep_index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) struct xhci_ring *ep_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) struct xhci_command *cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) struct xhci_segment *new_seg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) struct xhci_segment *halted_seg = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) union xhci_trb *new_deq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) int new_cycle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) union xhci_trb *halted_trb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) int index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) dma_addr_t addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) u64 hw_dequeue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) bool cycle_found = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) bool td_last_trb_found = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) u32 trb_sct = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) ep_ring = xhci_triad_to_transfer_ring(xhci, slot_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) ep_index, stream_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) if (!ep_ring) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) xhci_warn(xhci, "WARN can't find new dequeue, invalid stream ID %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) stream_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) * A cancelled TD can complete with a stall if HW cached the trb.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) * In this case driver can't find td, but if the ring is empty we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) * can move the dequeue pointer to the current enqueue position.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) * We shouldn't hit this anymore as cached cancelled TRBs are given back
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) * after clearing the cache, but be on the safe side and keep it anyway
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) if (!td) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) if (list_empty(&ep_ring->td_list)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) new_seg = ep_ring->enq_seg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) new_deq = ep_ring->enqueue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) new_cycle = ep_ring->cycle_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) xhci_dbg(xhci, "ep ring empty, Set new dequeue = enqueue");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) goto deq_found;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) xhci_warn(xhci, "Can't find new dequeue state, missing td\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) hw_dequeue = xhci_get_hw_deq(xhci, dev, ep_index, stream_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) new_seg = ep_ring->deq_seg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) new_deq = ep_ring->dequeue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) * Quirk: xHC write-back of the DCS field in the hardware dequeue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) * pointer is wrong - use the cycle state of the TRB pointed to by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) * the dequeue pointer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) if (xhci->quirks & XHCI_EP_CTX_BROKEN_DCS &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) !(ep->ep_state & EP_HAS_STREAMS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) halted_seg = trb_in_td(xhci, td->start_seg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) td->first_trb, td->last_trb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) hw_dequeue & ~0xf, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) if (halted_seg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) index = ((dma_addr_t)(hw_dequeue & ~0xf) - halted_seg->dma) /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) sizeof(*halted_trb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) halted_trb = &halted_seg->trbs[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) new_cycle = halted_trb->generic.field[3] & 0x1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) xhci_dbg(xhci, "Endpoint DCS = %d TRB index = %d cycle = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) (u8)(hw_dequeue & 0x1), index, new_cycle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) new_cycle = hw_dequeue & 0x1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) * We want to find the pointer, segment and cycle state of the new trb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) * (the one after current TD's last_trb). We know the cycle state at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) * hw_dequeue, so walk the ring until both hw_dequeue and last_trb are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) * found.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) if (!cycle_found && xhci_trb_virt_to_dma(new_seg, new_deq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) == (dma_addr_t)(hw_dequeue & ~0xf)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) cycle_found = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) if (td_last_trb_found)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) if (new_deq == td->last_trb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) td_last_trb_found = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) if (cycle_found && trb_is_link(new_deq) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) link_trb_toggles_cycle(new_deq))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) new_cycle ^= 0x1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) next_trb(xhci, ep_ring, &new_seg, &new_deq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) /* Search wrapped around, bail out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) if (new_deq == ep->ring->dequeue) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) xhci_err(xhci, "Error: Failed finding new dequeue state\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) } while (!cycle_found || !td_last_trb_found);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) deq_found:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) /* Don't update the ring cycle state for the producer (us). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) addr = xhci_trb_virt_to_dma(new_seg, new_deq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) if (addr == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) xhci_warn(xhci, "Can't find dma of new dequeue ptr\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) xhci_warn(xhci, "deq seg = %p, deq ptr = %p\n", new_seg, new_deq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) if ((ep->ep_state & SET_DEQ_PENDING)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) xhci_warn(xhci, "Set TR Deq already pending, don't submit for 0x%pad\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) &addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) /* This function gets called from contexts where it cannot sleep */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) cmd = xhci_alloc_command(xhci, false, GFP_ATOMIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) if (!cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) xhci_warn(xhci, "Can't alloc Set TR Deq cmd 0x%pad\n", &addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) if (stream_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) trb_sct = SCT_FOR_TRB(SCT_PRI_TR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) ret = queue_command(xhci, cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) lower_32_bits(addr) | trb_sct | new_cycle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) upper_32_bits(addr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) STREAM_ID_FOR_TRB(stream_id), SLOT_ID_FOR_TRB(slot_id) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) EP_ID_FOR_TRB(ep_index) | TRB_TYPE(TRB_SET_DEQ), false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) xhci_free_command(xhci, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) ep->queued_deq_seg = new_seg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) ep->queued_deq_ptr = new_deq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) "Set TR Deq ptr 0x%llx, cycle %u\n", addr, new_cycle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) /* Stop the TD queueing code from ringing the doorbell until
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) * this command completes. The HC won't set the dequeue pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) * if the ring is running, and ringing the doorbell starts the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) * ring running.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) ep->ep_state |= SET_DEQ_PENDING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) xhci_ring_cmd_db(xhci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) /* flip_cycle means flip the cycle bit of all but the first and last TRB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) * (The last TRB actually points to the ring enqueue pointer, which is not part
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) * of this TD.) This is used to remove partially enqueued isoc TDs from a ring.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) static void td_to_noop(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) struct xhci_td *td, bool flip_cycle)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) struct xhci_segment *seg = td->start_seg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) union xhci_trb *trb = td->first_trb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) while (1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) trb_to_noop(trb, TRB_TR_NOOP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) /* flip cycle if asked to */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) if (flip_cycle && trb != td->first_trb && trb != td->last_trb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) trb->generic.field[3] ^= cpu_to_le32(TRB_CYCLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) if (trb == td->last_trb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) next_trb(xhci, ep_ring, &seg, &trb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) static void xhci_stop_watchdog_timer_in_irq(struct xhci_hcd *xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) struct xhci_virt_ep *ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) ep->ep_state &= ~EP_STOP_CMD_PENDING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) /* Can't del_timer_sync in interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) del_timer(&ep->stop_cmd_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) * Must be called with xhci->lock held in interrupt context,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) * releases and re-acquires xhci->lock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) static void xhci_giveback_urb_in_irq(struct xhci_hcd *xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) struct xhci_td *cur_td, int status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) struct urb *urb = cur_td->urb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) struct urb_priv *urb_priv = urb->hcpriv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) struct usb_hcd *hcd = bus_to_hcd(urb->dev->bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) if (xhci->quirks & XHCI_AMD_PLL_FIX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) usb_amd_quirk_pll_enable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) xhci_urb_free_priv(urb_priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) usb_hcd_unlink_urb_from_ep(hcd, urb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) trace_xhci_urb_giveback(urb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) usb_hcd_giveback_urb(hcd, urb, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) static void xhci_unmap_td_bounce_buffer(struct xhci_hcd *xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) struct xhci_ring *ring, struct xhci_td *td)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) struct device *dev = xhci_to_hcd(xhci)->self.controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) struct xhci_segment *seg = td->bounce_seg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) struct urb *urb = td->urb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) size_t len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) if (!ring || !seg || !urb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) if (usb_urb_dir_out(urb)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) dma_unmap_single(dev, seg->bounce_dma, ring->bounce_buf_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) dma_unmap_single(dev, seg->bounce_dma, ring->bounce_buf_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) /* for in tranfers we need to copy the data from bounce to sg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) if (urb->num_sgs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) len = sg_pcopy_from_buffer(urb->sg, urb->num_sgs, seg->bounce_buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) seg->bounce_len, seg->bounce_offs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) if (len != seg->bounce_len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) xhci_warn(xhci, "WARN Wrong bounce buffer read length: %zu != %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) len, seg->bounce_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) memcpy(urb->transfer_buffer + seg->bounce_offs, seg->bounce_buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) seg->bounce_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) seg->bounce_len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) seg->bounce_offs = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) static int xhci_td_cleanup(struct xhci_hcd *xhci, struct xhci_td *td,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) struct xhci_ring *ep_ring, int status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) struct urb *urb = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) /* Clean up the endpoint's TD list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) urb = td->urb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) /* if a bounce buffer was used to align this td then unmap it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) xhci_unmap_td_bounce_buffer(xhci, ep_ring, td);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) /* Do one last check of the actual transfer length.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) * If the host controller said we transferred more data than the buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) * length, urb->actual_length will be a very big number (since it's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) * unsigned). Play it safe and say we didn't transfer anything.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) if (urb->actual_length > urb->transfer_buffer_length) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) xhci_warn(xhci, "URB req %u and actual %u transfer length mismatch\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) urb->transfer_buffer_length, urb->actual_length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) urb->actual_length = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) /* TD might be removed from td_list if we are giving back a cancelled URB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) if (!list_empty(&td->td_list))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) list_del_init(&td->td_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) /* Giving back a cancelled URB, or if a slated TD completed anyway */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) if (!list_empty(&td->cancelled_td_list))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) list_del_init(&td->cancelled_td_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) inc_td_cnt(urb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) /* Giveback the urb when all the tds are completed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) if (last_td_in_urb(td)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) if ((urb->actual_length != urb->transfer_buffer_length &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) (urb->transfer_flags & URB_SHORT_NOT_OK)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) (status != 0 && !usb_endpoint_xfer_isoc(&urb->ep->desc)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) xhci_dbg(xhci, "Giveback URB %p, len = %d, expected = %d, status = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) urb, urb->actual_length,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) urb->transfer_buffer_length, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) /* set isoc urb status to 0 just as EHCI, UHCI, and OHCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) xhci_giveback_urb_in_irq(xhci, td, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) /* Complete the cancelled URBs we unlinked from td_list. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) static void xhci_giveback_invalidated_tds(struct xhci_virt_ep *ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) struct xhci_ring *ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) struct xhci_td *td, *tmp_td;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) list_for_each_entry_safe(td, tmp_td, &ep->cancelled_td_list,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) cancelled_td_list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) ring = xhci_urb_to_transfer_ring(ep->xhci, td->urb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) if (td->cancel_status == TD_CLEARED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) xhci_dbg(ep->xhci, "%s: Giveback cancelled URB %p TD\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) __func__, td->urb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) xhci_td_cleanup(ep->xhci, td, ring, td->status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) xhci_dbg(ep->xhci, "%s: Keep cancelled URB %p TD as cancel_status is %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) __func__, td->urb, td->cancel_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) if (ep->xhci->xhc_state & XHCI_STATE_DYING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) static int xhci_reset_halted_ep(struct xhci_hcd *xhci, unsigned int slot_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) unsigned int ep_index, enum xhci_ep_reset_type reset_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) struct xhci_command *command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) command = xhci_alloc_command(xhci, false, GFP_ATOMIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) if (!command) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) xhci_dbg(xhci, "%s-reset ep %u, slot %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) (reset_type == EP_HARD_RESET) ? "Hard" : "Soft",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) ep_index, slot_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) ret = xhci_queue_reset_ep(xhci, command, slot_id, ep_index, reset_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) xhci_err(xhci, "ERROR queuing reset endpoint for slot %d ep_index %d, %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) slot_id, ep_index, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) static int xhci_handle_halted_endpoint(struct xhci_hcd *xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) struct xhci_virt_ep *ep, unsigned int stream_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) struct xhci_td *td,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) enum xhci_ep_reset_type reset_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) unsigned int slot_id = ep->vdev->slot_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) * Avoid resetting endpoint if link is inactive. Can cause host hang.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) * Device will be reset soon to recover the link so don't do anything
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) if (ep->vdev->flags & VDEV_PORT_ERROR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) /* add td to cancelled list and let reset ep handler take care of it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) if (reset_type == EP_HARD_RESET) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) ep->ep_state |= EP_HARD_CLEAR_TOGGLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) if (td && list_empty(&td->cancelled_td_list)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) list_add_tail(&td->cancelled_td_list, &ep->cancelled_td_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) td->cancel_status = TD_HALTED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) if (ep->ep_state & EP_HALTED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) xhci_dbg(xhci, "Reset ep command for ep_index %d already pending\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) ep->ep_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) err = xhci_reset_halted_ep(xhci, slot_id, ep->ep_index, reset_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) ep->ep_state |= EP_HALTED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) xhci_ring_cmd_db(xhci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) * Fix up the ep ring first, so HW stops executing cancelled TDs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) * We have the xHCI lock, so nothing can modify this list until we drop it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) * We're also in the event handler, so we can't get re-interrupted if another
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) * Stop Endpoint command completes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) * only call this when ring is not in a running state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) static int xhci_invalidate_cancelled_tds(struct xhci_virt_ep *ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) struct xhci_hcd *xhci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) struct xhci_td *td = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) struct xhci_td *tmp_td = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) struct xhci_td *cached_td = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) struct xhci_ring *ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) u64 hw_deq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) unsigned int slot_id = ep->vdev->slot_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) xhci = ep->xhci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) list_for_each_entry_safe(td, tmp_td, &ep->cancelled_td_list, cancelled_td_list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) "Removing canceled TD starting at 0x%llx (dma) in stream %u URB %p",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) (unsigned long long)xhci_trb_virt_to_dma(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) td->start_seg, td->first_trb),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) td->urb->stream_id, td->urb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) list_del_init(&td->td_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) ring = xhci_urb_to_transfer_ring(xhci, td->urb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) if (!ring) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) xhci_warn(xhci, "WARN Cancelled URB %p has invalid stream ID %u.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) td->urb, td->urb->stream_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) * If a ring stopped on the TD we need to cancel then we have to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) * move the xHC endpoint ring dequeue pointer past this TD.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) * Rings halted due to STALL may show hw_deq is past the stalled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) * TD, but still require a set TR Deq command to flush xHC cache.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) hw_deq = xhci_get_hw_deq(xhci, ep->vdev, ep->ep_index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) td->urb->stream_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) hw_deq &= ~0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) if (td->cancel_status == TD_HALTED ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) trb_in_td(xhci, td->start_seg, td->first_trb, td->last_trb, hw_deq, false)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) switch (td->cancel_status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) case TD_CLEARED: /* TD is already no-op */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) case TD_CLEARING_CACHE: /* set TR deq command already queued */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) case TD_DIRTY: /* TD is cached, clear it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) case TD_HALTED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) td->cancel_status = TD_CLEARING_CACHE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) if (cached_td)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) /* FIXME stream case, several stopped rings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) xhci_dbg(xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) "Move dq past stream %u URB %p instead of stream %u URB %p\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) td->urb->stream_id, td->urb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) cached_td->urb->stream_id, cached_td->urb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) cached_td = td;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) td_to_noop(xhci, ring, td, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) td->cancel_status = TD_CLEARED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) /* If there's no need to move the dequeue pointer then we're done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) if (!cached_td)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) err = xhci_move_dequeue_past_td(xhci, slot_id, ep->ep_index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) cached_td->urb->stream_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) cached_td);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) /* Failed to move past cached td, just set cached TDs to no-op */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) list_for_each_entry_safe(td, tmp_td, &ep->cancelled_td_list, cancelled_td_list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) if (td->cancel_status != TD_CLEARING_CACHE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) xhci_dbg(xhci, "Failed to clear cancelled cached URB %p, mark clear anyway\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) td->urb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) td_to_noop(xhci, ring, td, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) td->cancel_status = TD_CLEARED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) * Returns the TD the endpoint ring halted on.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) * Only call for non-running rings without streams.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) static struct xhci_td *find_halted_td(struct xhci_virt_ep *ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) struct xhci_td *td;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) u64 hw_deq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) if (!list_empty(&ep->ring->td_list)) { /* Not streams compatible */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) hw_deq = xhci_get_hw_deq(ep->xhci, ep->vdev, ep->ep_index, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) hw_deq &= ~0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) td = list_first_entry(&ep->ring->td_list, struct xhci_td, td_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) if (trb_in_td(ep->xhci, td->start_seg, td->first_trb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) td->last_trb, hw_deq, false))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) return td;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) * When we get a command completion for a Stop Endpoint Command, we need to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) * unlink any cancelled TDs from the ring. There are two ways to do that:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) * 1. If the HW was in the middle of processing the TD that needs to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) * cancelled, then we must move the ring's dequeue pointer past the last TRB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) * in the TD with a Set Dequeue Pointer Command.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) * 2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) * bit cleared) so that the HW will skip over them.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) static void xhci_handle_cmd_stop_ep(struct xhci_hcd *xhci, int slot_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) union xhci_trb *trb, u32 comp_code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) unsigned int ep_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) struct xhci_virt_ep *ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) struct xhci_ep_ctx *ep_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) struct xhci_td *td = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) enum xhci_ep_reset_type reset_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) struct xhci_command *command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) if (unlikely(TRB_TO_SUSPEND_PORT(le32_to_cpu(trb->generic.field[3])))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) if (!xhci->devs[slot_id])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) xhci_warn(xhci, "Stop endpoint command completion for disabled slot %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) slot_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) ep = xhci_get_virt_ep(xhci, slot_id, ep_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) if (!ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) ep_ctx = xhci_get_ep_ctx(xhci, ep->vdev->out_ctx, ep_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) trace_xhci_handle_cmd_stop_ep(ep_ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) if (comp_code == COMP_CONTEXT_STATE_ERROR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) * If stop endpoint command raced with a halting endpoint we need to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) * reset the host side endpoint first.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) * If the TD we halted on isn't cancelled the TD should be given back
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) * with a proper error code, and the ring dequeue moved past the TD.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) * If streams case we can't find hw_deq, or the TD we halted on so do a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) * soft reset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) * Proper error code is unknown here, it would be -EPIPE if device side
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) * of enadpoit halted (aka STALL), and -EPROTO if not (transaction error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) * We use -EPROTO, if device is stalled it should return a stall error on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) * next transfer, which then will return -EPIPE, and device side stall is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) * noted and cleared by class driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) switch (GET_EP_CTX_STATE(ep_ctx)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) case EP_STATE_HALTED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) xhci_dbg(xhci, "Stop ep completion raced with stall, reset ep\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) if (ep->ep_state & EP_HAS_STREAMS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) reset_type = EP_SOFT_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) reset_type = EP_HARD_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) td = find_halted_td(ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) if (td)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) td->status = -EPROTO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) /* reset ep, reset handler cleans up cancelled tds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) err = xhci_handle_halted_endpoint(xhci, ep, 0, td,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) reset_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) xhci_stop_watchdog_timer_in_irq(xhci, ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) case EP_STATE_RUNNING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) /* Race, HW handled stop ep cmd before ep was running */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) xhci_dbg(xhci, "Stop ep completion ctx error, ep is running\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) command = xhci_alloc_command(xhci, false, GFP_ATOMIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) if (!command)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) xhci_stop_watchdog_timer_in_irq(xhci, ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) mod_timer(&ep->stop_cmd_timer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) jiffies + XHCI_STOP_EP_CMD_TIMEOUT * HZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) xhci_queue_stop_endpoint(xhci, command, slot_id, ep_index, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) xhci_ring_cmd_db(xhci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) /* will queue a set TR deq if stopped on a cancelled, uncleared TD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) xhci_invalidate_cancelled_tds(ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) xhci_stop_watchdog_timer_in_irq(xhci, ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) /* Otherwise ring the doorbell(s) to restart queued transfers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) xhci_giveback_invalidated_tds(ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) static void xhci_kill_ring_urbs(struct xhci_hcd *xhci, struct xhci_ring *ring)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) struct xhci_td *cur_td;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) struct xhci_td *tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) list_for_each_entry_safe(cur_td, tmp, &ring->td_list, td_list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) list_del_init(&cur_td->td_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) if (!list_empty(&cur_td->cancelled_td_list))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) list_del_init(&cur_td->cancelled_td_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) xhci_unmap_td_bounce_buffer(xhci, ring, cur_td);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) inc_td_cnt(cur_td->urb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) if (last_td_in_urb(cur_td))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) xhci_giveback_urb_in_irq(xhci, cur_td, -ESHUTDOWN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) static void xhci_kill_endpoint_urbs(struct xhci_hcd *xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) int slot_id, int ep_index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) struct xhci_td *cur_td;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) struct xhci_td *tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) struct xhci_virt_ep *ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) struct xhci_ring *ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) ep = &xhci->devs[slot_id]->eps[ep_index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) if ((ep->ep_state & EP_HAS_STREAMS) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) (ep->ep_state & EP_GETTING_NO_STREAMS)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) int stream_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) for (stream_id = 1; stream_id < ep->stream_info->num_streams;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) stream_id++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) ring = ep->stream_info->stream_rings[stream_id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) if (!ring)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) "Killing URBs for slot ID %u, ep index %u, stream %u",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) slot_id, ep_index, stream_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) xhci_kill_ring_urbs(xhci, ring);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) ring = ep->ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) if (!ring)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) "Killing URBs for slot ID %u, ep index %u",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) slot_id, ep_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) xhci_kill_ring_urbs(xhci, ring);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) list_for_each_entry_safe(cur_td, tmp, &ep->cancelled_td_list,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) cancelled_td_list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) list_del_init(&cur_td->cancelled_td_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) inc_td_cnt(cur_td->urb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) if (last_td_in_urb(cur_td))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) xhci_giveback_urb_in_irq(xhci, cur_td, -ESHUTDOWN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) * host controller died, register read returns 0xffffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) * Complete pending commands, mark them ABORTED.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) * URBs need to be given back as usb core might be waiting with device locks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) * held for the URBs to finish during device disconnect, blocking host remove.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) * Call with xhci->lock held.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) * lock is relased and re-acquired while giving back urb.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) void xhci_hc_died(struct xhci_hcd *xhci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) int i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) if (xhci->xhc_state & XHCI_STATE_DYING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) xhci_err(xhci, "xHCI host controller not responding, assume dead\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) xhci->xhc_state |= XHCI_STATE_DYING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) xhci_cleanup_command_queue(xhci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) /* return any pending urbs, remove may be waiting for them */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) for (i = 0; i <= HCS_MAX_SLOTS(xhci->hcs_params1); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) if (!xhci->devs[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) for (j = 0; j < 31; j++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) xhci_kill_endpoint_urbs(xhci, i, j);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) /* inform usb core hc died if PCI remove isn't already handling it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) if (!(xhci->xhc_state & XHCI_STATE_REMOVING))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) usb_hc_died(xhci_to_hcd(xhci));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) /* Watchdog timer function for when a stop endpoint command fails to complete.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) * In this case, we assume the host controller is broken or dying or dead. The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) * host may still be completing some other events, so we have to be careful to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) * let the event ring handler and the URB dequeueing/enqueueing functions know
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) * through xhci->state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) * The timer may also fire if the host takes a very long time to respond to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) * command, and the stop endpoint command completion handler cannot delete the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) * timer before the timer function is called. Another endpoint cancellation may
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) * sneak in before the timer function can grab the lock, and that may queue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) * another stop endpoint command and add the timer back. So we cannot use a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) * simple flag to say whether there is a pending stop endpoint command for a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) * particular endpoint.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) * Instead we use a combination of that flag and checking if a new timer is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) * pending.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) void xhci_stop_endpoint_command_watchdog(struct timer_list *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) struct xhci_virt_ep *ep = from_timer(ep, t, stop_cmd_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) struct xhci_hcd *xhci = ep->xhci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) u32 usbsts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) char str[XHCI_MSG_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) spin_lock_irqsave(&xhci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) /* bail out if cmd completed but raced with stop ep watchdog timer.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) if (!(ep->ep_state & EP_STOP_CMD_PENDING) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) timer_pending(&ep->stop_cmd_timer)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) spin_unlock_irqrestore(&xhci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) xhci_dbg(xhci, "Stop EP timer raced with cmd completion, exit");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) usbsts = readl(&xhci->op_regs->status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) xhci_warn(xhci, "xHCI host not responding to stop endpoint command.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) xhci_warn(xhci, "USBSTS:%s\n", xhci_decode_usbsts(str, usbsts));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) ep->ep_state &= ~EP_STOP_CMD_PENDING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) xhci_halt(xhci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) * handle a stop endpoint cmd timeout as if host died (-ENODEV).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) * In the future we could distinguish between -ENODEV and -ETIMEDOUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) * and try to recover a -ETIMEDOUT with a host controller reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) xhci_hc_died(xhci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) spin_unlock_irqrestore(&xhci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) "xHCI host controller is dead.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) static void update_ring_for_set_deq_completion(struct xhci_hcd *xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) struct xhci_virt_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) struct xhci_ring *ep_ring,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) unsigned int ep_index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) union xhci_trb *dequeue_temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) int num_trbs_free_temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) bool revert = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) num_trbs_free_temp = ep_ring->num_trbs_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) dequeue_temp = ep_ring->dequeue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) /* If we get two back-to-back stalls, and the first stalled transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) * ends just before a link TRB, the dequeue pointer will be left on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) * the link TRB by the code in the while loop. So we have to update
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) * the dequeue pointer one segment further, or we'll jump off
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) * the segment into la-la-land.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) if (trb_is_link(ep_ring->dequeue)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) ep_ring->deq_seg = ep_ring->deq_seg->next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) ep_ring->dequeue = ep_ring->deq_seg->trbs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) while (ep_ring->dequeue != dev->eps[ep_index].queued_deq_ptr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) /* We have more usable TRBs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) ep_ring->num_trbs_free++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) ep_ring->dequeue++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) if (trb_is_link(ep_ring->dequeue)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) if (ep_ring->dequeue ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) dev->eps[ep_index].queued_deq_ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) ep_ring->deq_seg = ep_ring->deq_seg->next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) ep_ring->dequeue = ep_ring->deq_seg->trbs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) if (ep_ring->dequeue == dequeue_temp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) revert = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) if (revert) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) xhci_dbg(xhci, "Unable to find new dequeue pointer\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) ep_ring->num_trbs_free = num_trbs_free_temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) * When we get a completion for a Set Transfer Ring Dequeue Pointer command,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) * we need to clear the set deq pending flag in the endpoint ring state, so that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) * the TD queueing code can ring the doorbell again. We also need to ring the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) * endpoint doorbell to restart the ring, but only if there aren't more
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) * cancellations pending.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) static void xhci_handle_cmd_set_deq(struct xhci_hcd *xhci, int slot_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) union xhci_trb *trb, u32 cmd_comp_code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) unsigned int ep_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) unsigned int stream_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) struct xhci_ring *ep_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) struct xhci_virt_ep *ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) struct xhci_ep_ctx *ep_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) struct xhci_slot_ctx *slot_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) struct xhci_td *td, *tmp_td;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) stream_id = TRB_TO_STREAM_ID(le32_to_cpu(trb->generic.field[2]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) ep = xhci_get_virt_ep(xhci, slot_id, ep_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) if (!ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) ep_ring = xhci_virt_ep_to_ring(xhci, ep, stream_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) if (!ep_ring) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) xhci_warn(xhci, "WARN Set TR deq ptr command for freed stream ID %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) stream_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) /* XXX: Harmless??? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) goto cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) ep_ctx = xhci_get_ep_ctx(xhci, ep->vdev->out_ctx, ep_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) slot_ctx = xhci_get_slot_ctx(xhci, ep->vdev->out_ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) trace_xhci_handle_cmd_set_deq(slot_ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) trace_xhci_handle_cmd_set_deq_ep(ep_ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) if (cmd_comp_code != COMP_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) unsigned int ep_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) unsigned int slot_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) switch (cmd_comp_code) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) case COMP_TRB_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) xhci_warn(xhci, "WARN Set TR Deq Ptr cmd invalid because of stream ID configuration\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) case COMP_CONTEXT_STATE_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed due to incorrect slot or ep state.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) ep_state = GET_EP_CTX_STATE(ep_ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) slot_state = le32_to_cpu(slot_ctx->dev_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) slot_state = GET_SLOT_STATE(slot_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) "Slot state = %u, EP state = %u",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) slot_state, ep_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) case COMP_SLOT_NOT_ENABLED_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed because slot %u was not enabled.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) slot_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) xhci_warn(xhci, "WARN Set TR Deq Ptr cmd with unknown completion code of %u.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) cmd_comp_code);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) /* OK what do we do now? The endpoint state is hosed, and we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) * should never get to this point if the synchronization between
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) * queueing, and endpoint state are correct. This might happen
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) * if the device gets disconnected after we've finished
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) * cancelling URBs, which might not be an error...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) u64 deq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) /* 4.6.10 deq ptr is written to the stream ctx for streams */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) if (ep->ep_state & EP_HAS_STREAMS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) struct xhci_stream_ctx *ctx =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) &ep->stream_info->stream_ctx_array[stream_id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) deq = le64_to_cpu(ctx->stream_ring) & SCTX_DEQ_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) deq = le64_to_cpu(ep_ctx->deq) & ~EP_CTX_CYCLE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) "Successful Set TR Deq Ptr cmd, deq = @%08llx", deq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) if (xhci_trb_virt_to_dma(ep->queued_deq_seg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) ep->queued_deq_ptr) == deq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) /* Update the ring's dequeue segment and dequeue pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) * to reflect the new position.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) update_ring_for_set_deq_completion(xhci, ep->vdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) ep_ring, ep_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) xhci_warn(xhci, "Mismatch between completed Set TR Deq Ptr command & xHCI internal state.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) xhci_warn(xhci, "ep deq seg = %p, deq ptr = %p\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) ep->queued_deq_seg, ep->queued_deq_ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) /* HW cached TDs cleared from cache, give them back */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) list_for_each_entry_safe(td, tmp_td, &ep->cancelled_td_list,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) cancelled_td_list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) ep_ring = xhci_urb_to_transfer_ring(ep->xhci, td->urb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) if (td->cancel_status == TD_CLEARING_CACHE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) td->cancel_status = TD_CLEARED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) xhci_dbg(ep->xhci, "%s: Giveback cancelled URB %p TD\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) __func__, td->urb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) xhci_td_cleanup(ep->xhci, td, ep_ring, td->status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) xhci_dbg(ep->xhci, "%s: Keep cancelled URB %p TD as cancel_status is %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) __func__, td->urb, td->cancel_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) cleanup:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) ep->ep_state &= ~SET_DEQ_PENDING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) ep->queued_deq_seg = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) ep->queued_deq_ptr = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) /* Restart any rings with pending URBs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) static void xhci_handle_cmd_reset_ep(struct xhci_hcd *xhci, int slot_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) union xhci_trb *trb, u32 cmd_comp_code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) struct xhci_virt_ep *ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) struct xhci_ep_ctx *ep_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) unsigned int ep_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) ep = xhci_get_virt_ep(xhci, slot_id, ep_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) if (!ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) ep_ctx = xhci_get_ep_ctx(xhci, ep->vdev->out_ctx, ep_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) trace_xhci_handle_cmd_reset_ep(ep_ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) /* This command will only fail if the endpoint wasn't halted,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) * but we don't care.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) "Ignoring reset ep completion code of %u", cmd_comp_code);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) /* Cleanup cancelled TDs as ep is stopped. May queue a Set TR Deq cmd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) xhci_invalidate_cancelled_tds(ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) if (xhci->quirks & XHCI_RESET_EP_QUIRK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) xhci_dbg(xhci, "Note: Removed workaround to queue config ep for this hw");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) /* Clear our internal halted state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) ep->ep_state &= ~EP_HALTED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) xhci_giveback_invalidated_tds(ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) /* if this was a soft reset, then restart */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) if ((le32_to_cpu(trb->generic.field[3])) & TRB_TSP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) static void xhci_handle_cmd_enable_slot(struct xhci_hcd *xhci, int slot_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) struct xhci_command *command, u32 cmd_comp_code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) if (cmd_comp_code == COMP_SUCCESS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) command->slot_id = slot_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) command->slot_id = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) static void xhci_handle_cmd_disable_slot(struct xhci_hcd *xhci, int slot_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) struct xhci_virt_device *virt_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) struct xhci_slot_ctx *slot_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) virt_dev = xhci->devs[slot_id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) if (!virt_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) trace_xhci_handle_cmd_disable_slot(slot_ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) if (xhci->quirks & XHCI_EP_LIMIT_QUIRK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) /* Delete default control endpoint resources */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) xhci_free_device_endpoint_resources(xhci, virt_dev, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) static void xhci_handle_cmd_config_ep(struct xhci_hcd *xhci, int slot_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) u32 cmd_comp_code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) struct xhci_virt_device *virt_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) struct xhci_input_control_ctx *ctrl_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) struct xhci_ep_ctx *ep_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) unsigned int ep_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) unsigned int ep_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) u32 add_flags, drop_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) * Configure endpoint commands can come from the USB core
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) * configuration or alt setting changes, or because the HW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) * needed an extra configure endpoint command after a reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) * endpoint command or streams were being configured.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) * If the command was for a halted endpoint, the xHCI driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) * is not waiting on the configure endpoint command.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) virt_dev = xhci->devs[slot_id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) if (!virt_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) if (!ctrl_ctx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) xhci_warn(xhci, "Could not get input context, bad type.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) add_flags = le32_to_cpu(ctrl_ctx->add_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) /* Input ctx add_flags are the endpoint index plus one */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) ep_index = xhci_last_valid_endpoint(add_flags) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->out_ctx, ep_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) trace_xhci_handle_cmd_config_ep(ep_ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) /* A usb_set_interface() call directly after clearing a halted
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) * condition may race on this quirky hardware. Not worth
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) * worrying about, since this is prototype hardware. Not sure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) * if this will work for streams, but streams support was
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) * untested on this prototype.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) if (xhci->quirks & XHCI_RESET_EP_QUIRK &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) ep_index != (unsigned int) -1 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) add_flags - SLOT_FLAG == drop_flags) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) ep_state = virt_dev->eps[ep_index].ep_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) if (!(ep_state & EP_HALTED))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) "Completed config ep cmd - "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) "last ep index = %d, state = %d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) ep_index, ep_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) /* Clear internal halted state and restart ring(s) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) virt_dev->eps[ep_index].ep_state &= ~EP_HALTED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) static void xhci_handle_cmd_addr_dev(struct xhci_hcd *xhci, int slot_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) struct xhci_virt_device *vdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) struct xhci_slot_ctx *slot_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) vdev = xhci->devs[slot_id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) if (!vdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) slot_ctx = xhci_get_slot_ctx(xhci, vdev->out_ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) trace_xhci_handle_cmd_addr_dev(slot_ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) static void xhci_handle_cmd_reset_dev(struct xhci_hcd *xhci, int slot_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) struct xhci_virt_device *vdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) struct xhci_slot_ctx *slot_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) vdev = xhci->devs[slot_id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) if (!vdev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) xhci_warn(xhci, "Reset device command completion for disabled slot %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) slot_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) slot_ctx = xhci_get_slot_ctx(xhci, vdev->out_ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) trace_xhci_handle_cmd_reset_dev(slot_ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) xhci_dbg(xhci, "Completed reset device command.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) static void xhci_handle_cmd_nec_get_fw(struct xhci_hcd *xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) struct xhci_event_cmd *event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) if (!(xhci->quirks & XHCI_NEC_HOST)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) xhci_warn(xhci, "WARN NEC_GET_FW command on non-NEC host\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) "NEC firmware version %2x.%02x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) NEC_FW_MAJOR(le32_to_cpu(event->status)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) NEC_FW_MINOR(le32_to_cpu(event->status)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) static void xhci_complete_del_and_free_cmd(struct xhci_command *cmd, u32 status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) list_del(&cmd->cmd_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) if (cmd->completion) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) cmd->status = status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) complete(cmd->completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) kfree(cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) void xhci_cleanup_command_queue(struct xhci_hcd *xhci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) struct xhci_command *cur_cmd, *tmp_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) xhci->current_cmd = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) list_for_each_entry_safe(cur_cmd, tmp_cmd, &xhci->cmd_list, cmd_list)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) xhci_complete_del_and_free_cmd(cur_cmd, COMP_COMMAND_ABORTED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) void xhci_handle_command_timeout(struct work_struct *work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) struct xhci_hcd *xhci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) u64 hw_ring_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) xhci = container_of(to_delayed_work(work), struct xhci_hcd, cmd_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) spin_lock_irqsave(&xhci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) * If timeout work is pending, or current_cmd is NULL, it means we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) * raced with command completion. Command is handled so just return.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) if (!xhci->current_cmd || delayed_work_pending(&xhci->cmd_timer)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) spin_unlock_irqrestore(&xhci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) /* mark this command to be cancelled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) xhci->current_cmd->status = COMP_COMMAND_ABORTED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) /* Make sure command ring is running before aborting it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) hw_ring_state = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) if (hw_ring_state == ~(u64)0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) xhci_hc_died(xhci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) goto time_out_completed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) if ((xhci->cmd_ring_state & CMD_RING_STATE_RUNNING) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) (hw_ring_state & CMD_RING_RUNNING)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) /* Prevent new doorbell, and start command abort */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) xhci->cmd_ring_state = CMD_RING_STATE_ABORTED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) xhci_dbg(xhci, "Command timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) xhci_abort_cmd_ring(xhci, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) goto time_out_completed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) /* host removed. Bail out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) if (xhci->xhc_state & XHCI_STATE_REMOVING) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) xhci_dbg(xhci, "host removed, ring start fail?\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) xhci_cleanup_command_queue(xhci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) goto time_out_completed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) /* command timeout on stopped ring, ring can't be aborted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) xhci_dbg(xhci, "Command timeout on stopped ring\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) xhci_handle_stopped_cmd_ring(xhci, xhci->current_cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) time_out_completed:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) spin_unlock_irqrestore(&xhci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) static void handle_cmd_completion(struct xhci_hcd *xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) struct xhci_event_cmd *event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) unsigned int slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) u64 cmd_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) dma_addr_t cmd_dequeue_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) u32 cmd_comp_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) union xhci_trb *cmd_trb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) struct xhci_command *cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) u32 cmd_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) if (slot_id >= MAX_HC_SLOTS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) xhci_warn(xhci, "Invalid slot_id %u\n", slot_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) cmd_dma = le64_to_cpu(event->cmd_trb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) cmd_trb = xhci->cmd_ring->dequeue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) trace_xhci_handle_command(xhci->cmd_ring, &cmd_trb->generic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) cmd_dequeue_dma = xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) cmd_trb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) * Check whether the completion event is for our internal kept
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) * command.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) if (!cmd_dequeue_dma || cmd_dma != (u64)cmd_dequeue_dma) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) xhci_warn(xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) "ERROR mismatched command completion event\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) cmd = list_first_entry(&xhci->cmd_list, struct xhci_command, cmd_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) cancel_delayed_work(&xhci->cmd_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) cmd_comp_code = GET_COMP_CODE(le32_to_cpu(event->status));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) /* If CMD ring stopped we own the trbs between enqueue and dequeue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) if (cmd_comp_code == COMP_COMMAND_RING_STOPPED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) complete_all(&xhci->cmd_ring_stop_completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) if (cmd->command_trb != xhci->cmd_ring->dequeue) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) xhci_err(xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) "Command completion event does not match command\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) * Host aborted the command ring, check if the current command was
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) * supposed to be aborted, otherwise continue normally.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) * The command ring is stopped now, but the xHC will issue a Command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) * Ring Stopped event which will cause us to restart it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) if (cmd_comp_code == COMP_COMMAND_ABORTED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) if (cmd->status == COMP_COMMAND_ABORTED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) if (xhci->current_cmd == cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) xhci->current_cmd = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) goto event_handled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) cmd_type = TRB_FIELD_TO_TYPE(le32_to_cpu(cmd_trb->generic.field[3]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) switch (cmd_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) case TRB_ENABLE_SLOT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) xhci_handle_cmd_enable_slot(xhci, slot_id, cmd, cmd_comp_code);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) case TRB_DISABLE_SLOT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) xhci_handle_cmd_disable_slot(xhci, slot_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) case TRB_CONFIG_EP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) if (!cmd->completion)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) xhci_handle_cmd_config_ep(xhci, slot_id, cmd_comp_code);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) case TRB_EVAL_CONTEXT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) case TRB_ADDR_DEV:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) xhci_handle_cmd_addr_dev(xhci, slot_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) case TRB_STOP_RING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) WARN_ON(slot_id != TRB_TO_SLOT_ID(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) le32_to_cpu(cmd_trb->generic.field[3])));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) if (!cmd->completion)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) xhci_handle_cmd_stop_ep(xhci, slot_id, cmd_trb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) cmd_comp_code);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) case TRB_SET_DEQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) WARN_ON(slot_id != TRB_TO_SLOT_ID(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) le32_to_cpu(cmd_trb->generic.field[3])));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) xhci_handle_cmd_set_deq(xhci, slot_id, cmd_trb, cmd_comp_code);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) case TRB_CMD_NOOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) /* Is this an aborted command turned to NO-OP? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) if (cmd->status == COMP_COMMAND_RING_STOPPED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) cmd_comp_code = COMP_COMMAND_RING_STOPPED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) case TRB_RESET_EP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) WARN_ON(slot_id != TRB_TO_SLOT_ID(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) le32_to_cpu(cmd_trb->generic.field[3])));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) xhci_handle_cmd_reset_ep(xhci, slot_id, cmd_trb, cmd_comp_code);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) case TRB_RESET_DEV:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) /* SLOT_ID field in reset device cmd completion event TRB is 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) * Use the SLOT_ID from the command TRB instead (xhci 4.6.11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) slot_id = TRB_TO_SLOT_ID(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) le32_to_cpu(cmd_trb->generic.field[3]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) xhci_handle_cmd_reset_dev(xhci, slot_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) case TRB_NEC_GET_FW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) xhci_handle_cmd_nec_get_fw(xhci, event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) /* Skip over unknown commands on the event ring */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) xhci_info(xhci, "INFO unknown command type %d\n", cmd_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) /* restart timer if this wasn't the last command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) if (!list_is_singular(&xhci->cmd_list)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) xhci->current_cmd = list_first_entry(&cmd->cmd_list,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) struct xhci_command, cmd_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) xhci_mod_cmd_timer(xhci, XHCI_CMD_DEFAULT_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) } else if (xhci->current_cmd == cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) xhci->current_cmd = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) event_handled:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) xhci_complete_del_and_free_cmd(cmd, cmd_comp_code);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) inc_deq(xhci, xhci->cmd_ring);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) static void handle_vendor_event(struct xhci_hcd *xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) union xhci_trb *event, u32 trb_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) xhci_dbg(xhci, "Vendor specific event TRB type = %u\n", trb_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) if (trb_type == TRB_NEC_CMD_COMP && (xhci->quirks & XHCI_NEC_HOST))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) handle_cmd_completion(xhci, &event->event_cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) static void handle_device_notification(struct xhci_hcd *xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) union xhci_trb *event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) u32 slot_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) struct usb_device *udev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->generic.field[3]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) if (!xhci->devs[slot_id]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) xhci_warn(xhci, "Device Notification event for "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) "unused slot %u\n", slot_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) xhci_dbg(xhci, "Device Wake Notification event for slot ID %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) slot_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) udev = xhci->devs[slot_id]->udev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) if (udev && udev->parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) usb_wakeup_notification(udev->parent, udev->portnum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) * Quirk hanlder for errata seen on Cavium ThunderX2 processor XHCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) * Controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) * As per ThunderX2errata-129 USB 2 device may come up as USB 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) * If a connection to a USB 1 device is followed by another connection
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) * to a USB 2 device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) * Reset the PHY after the USB device is disconnected if device speed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) * is less than HCD_USB3.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) * Retry the reset sequence max of 4 times checking the PLL lock status.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) static void xhci_cavium_reset_phy_quirk(struct xhci_hcd *xhci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) struct usb_hcd *hcd = xhci_to_hcd(xhci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) u32 pll_lock_check;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) u32 retry_count = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) /* Assert PHY reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) writel(0x6F, hcd->regs + 0x1048);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) /* De-assert the PHY reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) writel(0x7F, hcd->regs + 0x1048);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) udelay(200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) pll_lock_check = readl(hcd->regs + 0x1070);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) } while (!(pll_lock_check & 0x1) && --retry_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) static void handle_port_status(struct xhci_hcd *xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) union xhci_trb *event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) struct usb_hcd *hcd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) u32 port_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) u32 portsc, cmd_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) int max_ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) int slot_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) unsigned int hcd_portnum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) struct xhci_bus_state *bus_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) bool bogus_port_status = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) struct xhci_port *port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) /* Port status change events always have a successful completion code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) if (GET_COMP_CODE(le32_to_cpu(event->generic.field[2])) != COMP_SUCCESS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) xhci_warn(xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) "WARN: xHC returned failed port status event\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) port_id = GET_PORT_ID(le32_to_cpu(event->generic.field[0]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) max_ports = HCS_MAX_PORTS(xhci->hcs_params1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) if ((port_id <= 0) || (port_id > max_ports)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) xhci_warn(xhci, "Port change event with invalid port ID %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) port_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) inc_deq(xhci, xhci->event_ring);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) port = &xhci->hw_ports[port_id - 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) if (!port || !port->rhub || port->hcd_portnum == DUPLICATE_ENTRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) xhci_warn(xhci, "Port change event, no port for port ID %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) port_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) bogus_port_status = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) goto cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) /* We might get interrupts after shared_hcd is removed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) if (port->rhub == &xhci->usb3_rhub && xhci->shared_hcd == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) xhci_dbg(xhci, "ignore port event for removed USB3 hcd\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) bogus_port_status = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) goto cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) hcd = port->rhub->hcd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) bus_state = &port->rhub->bus_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) hcd_portnum = port->hcd_portnum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) portsc = readl(port->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) xhci_dbg(xhci, "Port change event, %d-%d, id %d, portsc: 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) hcd->self.busnum, hcd_portnum + 1, port_id, portsc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) trace_xhci_handle_port_status(hcd_portnum, portsc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) if (hcd->state == HC_STATE_SUSPENDED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) xhci_dbg(xhci, "resume root hub\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) usb_hcd_resume_root_hub(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) if (hcd->speed >= HCD_USB3 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) (portsc & PORT_PLS_MASK) == XDEV_INACTIVE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) slot_id = xhci_find_slot_id_by_port(hcd, xhci, hcd_portnum + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) if (slot_id && xhci->devs[slot_id])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) xhci->devs[slot_id]->flags |= VDEV_PORT_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) if ((portsc & PORT_PLC) && (portsc & PORT_PLS_MASK) == XDEV_RESUME) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) xhci_dbg(xhci, "port resume event for port %d\n", port_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) cmd_reg = readl(&xhci->op_regs->command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) if (!(cmd_reg & CMD_RUN)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) xhci_warn(xhci, "xHC is not running.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) goto cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) if (DEV_SUPERSPEED_ANY(portsc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) xhci_dbg(xhci, "remote wake SS port %d\n", port_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) /* Set a flag to say the port signaled remote wakeup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) * so we can tell the difference between the end of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) * device and host initiated resume.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) bus_state->port_remote_wakeup |= 1 << hcd_portnum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) xhci_test_and_clear_bit(xhci, port, PORT_PLC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) usb_hcd_start_port_resume(&hcd->self, hcd_portnum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) xhci_set_link_state(xhci, port, XDEV_U0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) /* Need to wait until the next link state change
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) * indicates the device is actually in U0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) bogus_port_status = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) goto cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) } else if (!test_bit(hcd_portnum, &bus_state->resuming_ports)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) xhci_dbg(xhci, "resume HS port %d\n", port_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) bus_state->resume_done[hcd_portnum] = jiffies +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) msecs_to_jiffies(USB_RESUME_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) set_bit(hcd_portnum, &bus_state->resuming_ports);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) /* Do the rest in GetPortStatus after resume time delay.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) * Avoid polling roothub status before that so that a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) * usb device auto-resume latency around ~40ms.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) mod_timer(&hcd->rh_timer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) bus_state->resume_done[hcd_portnum]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) usb_hcd_start_port_resume(&hcd->self, hcd_portnum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) bogus_port_status = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) if ((portsc & PORT_PLC) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) DEV_SUPERSPEED_ANY(portsc) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) ((portsc & PORT_PLS_MASK) == XDEV_U0 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) (portsc & PORT_PLS_MASK) == XDEV_U1 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) (portsc & PORT_PLS_MASK) == XDEV_U2)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) xhci_dbg(xhci, "resume SS port %d finished\n", port_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) complete(&bus_state->u3exit_done[hcd_portnum]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) /* We've just brought the device into U0/1/2 through either the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) * Resume state after a device remote wakeup, or through the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) * U3Exit state after a host-initiated resume. If it's a device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) * initiated remote wake, don't pass up the link state change,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) * so the roothub behavior is consistent with external
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) * USB 3.0 hub behavior.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) slot_id = xhci_find_slot_id_by_port(hcd, xhci, hcd_portnum + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) if (slot_id && xhci->devs[slot_id])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) xhci_ring_device(xhci, slot_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) if (bus_state->port_remote_wakeup & (1 << hcd_portnum)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) xhci_test_and_clear_bit(xhci, port, PORT_PLC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) usb_wakeup_notification(hcd->self.root_hub,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) hcd_portnum + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) bogus_port_status = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) goto cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) * Check to see if xhci-hub.c is waiting on RExit to U0 transition (or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) * RExit to a disconnect state). If so, let the the driver know it's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) * out of the RExit state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) if (!DEV_SUPERSPEED_ANY(portsc) && hcd->speed < HCD_USB3 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) test_and_clear_bit(hcd_portnum,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) &bus_state->rexit_ports)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) complete(&bus_state->rexit_done[hcd_portnum]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) bogus_port_status = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) goto cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) if (hcd->speed < HCD_USB3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) xhci_test_and_clear_bit(xhci, port, PORT_PLC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) if ((xhci->quirks & XHCI_RESET_PLL_ON_DISCONNECT) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) (portsc & PORT_CSC) && !(portsc & PORT_CONNECT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) xhci_cavium_reset_phy_quirk(xhci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) cleanup:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) /* Update event ring dequeue pointer before dropping the lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) inc_deq(xhci, xhci->event_ring);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) /* Don't make the USB core poll the roothub if we got a bad port status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) * change event. Besides, at that point we can't tell which roothub
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) * (USB 2.0 or USB 3.0) to kick.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) if (bogus_port_status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) * xHCI port-status-change events occur when the "or" of all the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) * status-change bits in the portsc register changes from 0 to 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) * New status changes won't cause an event if any other change
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) * bits are still set. When an event occurs, switch over to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) * polling to avoid losing status changes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) xhci_dbg(xhci, "%s: starting usb%d port polling.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) __func__, hcd->self.busnum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) spin_unlock(&xhci->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) /* Pass this up to the core */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) usb_hcd_poll_rh_status(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) spin_lock(&xhci->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) * This TD is defined by the TRBs starting at start_trb in start_seg and ending
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) * at end_trb, which may be in another segment. If the suspect DMA address is a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) * TRB in this TD, this function returns that TRB's segment. Otherwise it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) * returns 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) struct xhci_segment *trb_in_td(struct xhci_hcd *xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) struct xhci_segment *start_seg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) union xhci_trb *start_trb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) union xhci_trb *end_trb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) dma_addr_t suspect_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) bool debug)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) dma_addr_t start_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) dma_addr_t end_seg_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) dma_addr_t end_trb_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) struct xhci_segment *cur_seg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) start_dma = xhci_trb_virt_to_dma(start_seg, start_trb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) cur_seg = start_seg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) if (start_dma == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) /* We may get an event for a Link TRB in the middle of a TD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) end_seg_dma = xhci_trb_virt_to_dma(cur_seg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) &cur_seg->trbs[TRBS_PER_SEGMENT - 1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) /* If the end TRB isn't in this segment, this is set to 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) end_trb_dma = xhci_trb_virt_to_dma(cur_seg, end_trb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) if (debug)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) xhci_warn(xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) "Looking for event-dma %016llx trb-start %016llx trb-end %016llx seg-start %016llx seg-end %016llx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) (unsigned long long)suspect_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) (unsigned long long)start_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) (unsigned long long)end_trb_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) (unsigned long long)cur_seg->dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) (unsigned long long)end_seg_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) if (end_trb_dma > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) /* The end TRB is in this segment, so suspect should be here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) if (start_dma <= end_trb_dma) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) if (suspect_dma >= start_dma && suspect_dma <= end_trb_dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) return cur_seg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) /* Case for one segment with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) * a TD wrapped around to the top
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) if ((suspect_dma >= start_dma &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) suspect_dma <= end_seg_dma) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) (suspect_dma >= cur_seg->dma &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) suspect_dma <= end_trb_dma))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) return cur_seg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) /* Might still be somewhere in this segment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) if (suspect_dma >= start_dma && suspect_dma <= end_seg_dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) return cur_seg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) cur_seg = cur_seg->next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) start_dma = xhci_trb_virt_to_dma(cur_seg, &cur_seg->trbs[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) } while (cur_seg != start_seg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) static void xhci_clear_hub_tt_buffer(struct xhci_hcd *xhci, struct xhci_td *td,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) struct xhci_virt_ep *ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) * As part of low/full-speed endpoint-halt processing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) * we must clear the TT buffer (USB 2.0 specification 11.17.5).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) if (td->urb->dev->tt && !usb_pipeint(td->urb->pipe) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) (td->urb->dev->tt->hub != xhci_to_hcd(xhci)->self.root_hub) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) !(ep->ep_state & EP_CLEARING_TT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) ep->ep_state |= EP_CLEARING_TT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) td->urb->ep->hcpriv = td->urb->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) if (usb_hub_clear_tt_buffer(td->urb))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) ep->ep_state &= ~EP_CLEARING_TT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) /* Check if an error has halted the endpoint ring. The class driver will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) * cleanup the halt for a non-default control endpoint if we indicate a stall.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) * However, a babble and other errors also halt the endpoint ring, and the class
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) * driver won't clear the halt in that case, so we need to issue a Set Transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) * Ring Dequeue Pointer command manually.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) static int xhci_requires_manual_halt_cleanup(struct xhci_hcd *xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) struct xhci_ep_ctx *ep_ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) unsigned int trb_comp_code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) /* TRB completion codes that may require a manual halt cleanup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) if (trb_comp_code == COMP_USB_TRANSACTION_ERROR ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) trb_comp_code == COMP_BABBLE_DETECTED_ERROR ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) trb_comp_code == COMP_SPLIT_TRANSACTION_ERROR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) /* The 0.95 spec says a babbling control endpoint
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) * is not halted. The 0.96 spec says it is. Some HW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) * claims to be 0.95 compliant, but it halts the control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) * endpoint anyway. Check if a babble halted the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) * endpoint.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) if (GET_EP_CTX_STATE(ep_ctx) == EP_STATE_HALTED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) if (trb_comp_code >= 224 && trb_comp_code <= 255) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) /* Vendor defined "informational" completion code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) * treat as not-an-error.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) xhci_dbg(xhci, "Vendor defined info completion code %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) trb_comp_code);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) xhci_dbg(xhci, "Treating code as success.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) static int finish_td(struct xhci_hcd *xhci, struct xhci_virt_ep *ep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) struct xhci_ring *ep_ring, struct xhci_td *td,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) u32 trb_comp_code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) struct xhci_ep_ctx *ep_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) ep_ctx = xhci_get_ep_ctx(xhci, ep->vdev->out_ctx, ep->ep_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) switch (trb_comp_code) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) case COMP_STOPPED_LENGTH_INVALID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) case COMP_STOPPED_SHORT_PACKET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) case COMP_STOPPED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) * The "Stop Endpoint" completion will take care of any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) * stopped TDs. A stopped TD may be restarted, so don't update
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) * the ring dequeue pointer or take this TD off any lists yet.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) case COMP_USB_TRANSACTION_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) case COMP_BABBLE_DETECTED_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) case COMP_SPLIT_TRANSACTION_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) * If endpoint context state is not halted we might be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) * racing with a reset endpoint command issued by a unsuccessful
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) * stop endpoint completion (context error). In that case the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) * td should be on the cancelled list, and EP_HALTED flag set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) * Or then it's not halted due to the 0.95 spec stating that a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) * babbling control endpoint should not halt. The 0.96 spec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) * again says it should. Some HW claims to be 0.95 compliant,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) * but it halts the control endpoint anyway.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) if (GET_EP_CTX_STATE(ep_ctx) != EP_STATE_HALTED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) * If EP_HALTED is set and TD is on the cancelled list
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) * the TD and dequeue pointer will be handled by reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) * ep command completion
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) if ((ep->ep_state & EP_HALTED) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) !list_empty(&td->cancelled_td_list)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) xhci_dbg(xhci, "Already resolving halted ep for 0x%llx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) (unsigned long long)xhci_trb_virt_to_dma(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) td->start_seg, td->first_trb));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) /* endpoint not halted, don't reset it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) /* Almost same procedure as for STALL_ERROR below */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) xhci_clear_hub_tt_buffer(xhci, td, ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) xhci_handle_halted_endpoint(xhci, ep, ep_ring->stream_id, td,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) EP_HARD_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) case COMP_STALL_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) * xhci internal endpoint state will go to a "halt" state for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) * any stall, including default control pipe protocol stall.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) * To clear the host side halt we need to issue a reset endpoint
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) * command, followed by a set dequeue command to move past the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) * TD.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) * Class drivers clear the device side halt from a functional
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) * stall later. Hub TT buffer should only be cleared for FS/LS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) * devices behind HS hubs for functional stalls.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) if (ep->ep_index != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) xhci_clear_hub_tt_buffer(xhci, td, ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) xhci_handle_halted_endpoint(xhci, ep, ep_ring->stream_id, td,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) EP_HARD_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) return 0; /* xhci_handle_halted_endpoint marked td cancelled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) /* Update ring dequeue pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) ep_ring->dequeue = td->last_trb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) ep_ring->deq_seg = td->last_trb_seg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) ep_ring->num_trbs_free += td->num_trbs - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) inc_deq(xhci, ep_ring);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) return xhci_td_cleanup(xhci, td, ep_ring, td->status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) /* sum trb lengths from ring dequeue up to stop_trb, _excluding_ stop_trb */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) static int sum_trb_lengths(struct xhci_hcd *xhci, struct xhci_ring *ring,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) union xhci_trb *stop_trb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) u32 sum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) union xhci_trb *trb = ring->dequeue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) struct xhci_segment *seg = ring->deq_seg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) for (sum = 0; trb != stop_trb; next_trb(xhci, ring, &seg, &trb)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) if (!trb_is_noop(trb) && !trb_is_link(trb))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) sum += TRB_LEN(le32_to_cpu(trb->generic.field[2]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) return sum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) * Process control tds, update urb status and actual_length.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) static int process_ctrl_td(struct xhci_hcd *xhci, struct xhci_virt_ep *ep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) struct xhci_ring *ep_ring, struct xhci_td *td,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) union xhci_trb *ep_trb, struct xhci_transfer_event *event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) struct xhci_ep_ctx *ep_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) u32 trb_comp_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) u32 remaining, requested;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) u32 trb_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(ep_trb->generic.field[3]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) ep_ctx = xhci_get_ep_ctx(xhci, ep->vdev->out_ctx, ep->ep_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) requested = td->urb->transfer_buffer_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) remaining = EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) switch (trb_comp_code) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) case COMP_SUCCESS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) if (trb_type != TRB_STATUS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) xhci_warn(xhci, "WARN: Success on ctrl %s TRB without IOC set?\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) (trb_type == TRB_DATA) ? "data" : "setup");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) td->status = -ESHUTDOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) td->status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) case COMP_SHORT_PACKET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) td->status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) case COMP_STOPPED_SHORT_PACKET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) if (trb_type == TRB_DATA || trb_type == TRB_NORMAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) td->urb->actual_length = remaining;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) xhci_warn(xhci, "WARN: Stopped Short Packet on ctrl setup or status TRB\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) goto finish_td;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) case COMP_STOPPED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) switch (trb_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) case TRB_SETUP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) td->urb->actual_length = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) goto finish_td;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) case TRB_DATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) case TRB_NORMAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) td->urb->actual_length = requested - remaining;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) goto finish_td;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) case TRB_STATUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) td->urb->actual_length = requested;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) goto finish_td;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) xhci_warn(xhci, "WARN: unexpected TRB Type %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) trb_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) goto finish_td;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) case COMP_STOPPED_LENGTH_INVALID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) goto finish_td;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) if (!xhci_requires_manual_halt_cleanup(xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) ep_ctx, trb_comp_code))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) xhci_dbg(xhci, "TRB error %u, halted endpoint index = %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) trb_comp_code, ep->ep_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) case COMP_STALL_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) /* Did we transfer part of the data (middle) phase? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) if (trb_type == TRB_DATA || trb_type == TRB_NORMAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) td->urb->actual_length = requested - remaining;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) else if (!td->urb_length_set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) td->urb->actual_length = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) goto finish_td;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) /* stopped at setup stage, no data transferred */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) if (trb_type == TRB_SETUP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) goto finish_td;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) * if on data stage then update the actual_length of the URB and flag it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) * as set, so it won't be overwritten in the event for the last TRB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) if (trb_type == TRB_DATA ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) trb_type == TRB_NORMAL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) td->urb_length_set = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) td->urb->actual_length = requested - remaining;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) xhci_dbg(xhci, "Waiting for status stage event\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) /* at status stage */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) if (!td->urb_length_set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) td->urb->actual_length = requested;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) finish_td:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) return finish_td(xhci, ep, ep_ring, td, trb_comp_code);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) * Process isochronous tds, update urb packet status and actual_length.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) static int process_isoc_td(struct xhci_hcd *xhci, struct xhci_virt_ep *ep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) struct xhci_ring *ep_ring, struct xhci_td *td,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) union xhci_trb *ep_trb, struct xhci_transfer_event *event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) struct urb_priv *urb_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) struct usb_iso_packet_descriptor *frame;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) u32 trb_comp_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) bool sum_trbs_for_length = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) u32 remaining, requested, ep_trb_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) int short_framestatus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) urb_priv = td->urb->hcpriv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) idx = urb_priv->num_tds_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) frame = &td->urb->iso_frame_desc[idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) requested = frame->length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) remaining = EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) ep_trb_len = TRB_LEN(le32_to_cpu(ep_trb->generic.field[2]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) short_framestatus = td->urb->transfer_flags & URB_SHORT_NOT_OK ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) -EREMOTEIO : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) /* handle completion code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) switch (trb_comp_code) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) case COMP_SUCCESS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) if (remaining) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) frame->status = short_framestatus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) if (xhci->quirks & XHCI_TRUST_TX_LENGTH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) sum_trbs_for_length = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) frame->status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) case COMP_SHORT_PACKET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) frame->status = short_framestatus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) sum_trbs_for_length = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) case COMP_BANDWIDTH_OVERRUN_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) frame->status = -ECOMM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) case COMP_ISOCH_BUFFER_OVERRUN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) case COMP_BABBLE_DETECTED_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) frame->status = -EOVERFLOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) case COMP_INCOMPATIBLE_DEVICE_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) case COMP_STALL_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) frame->status = -EPROTO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) case COMP_USB_TRANSACTION_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) frame->status = -EPROTO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) if (ep_trb != td->last_trb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) case COMP_STOPPED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) sum_trbs_for_length = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) case COMP_STOPPED_SHORT_PACKET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) /* field normally containing residue now contains tranferred */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) frame->status = short_framestatus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) requested = remaining;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) case COMP_STOPPED_LENGTH_INVALID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) requested = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) remaining = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) sum_trbs_for_length = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) frame->status = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) if (sum_trbs_for_length)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) frame->actual_length = sum_trb_lengths(xhci, ep->ring, ep_trb) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) ep_trb_len - remaining;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) frame->actual_length = requested;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) td->urb->actual_length += frame->actual_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) return finish_td(xhci, ep, ep_ring, td, trb_comp_code);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) static int skip_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) struct xhci_virt_ep *ep, int status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) struct urb_priv *urb_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) struct usb_iso_packet_descriptor *frame;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) urb_priv = td->urb->hcpriv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) idx = urb_priv->num_tds_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) frame = &td->urb->iso_frame_desc[idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) /* The transfer is partly done. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) frame->status = -EXDEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) /* calc actual length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) frame->actual_length = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501) /* Update ring dequeue pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) ep->ring->dequeue = td->last_trb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) ep->ring->deq_seg = td->last_trb_seg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504) ep->ring->num_trbs_free += td->num_trbs - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505) inc_deq(xhci, ep->ring);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507) return xhci_td_cleanup(xhci, td, ep->ring, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) * Process bulk and interrupt tds, update urb status and actual_length.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513) static int process_bulk_intr_td(struct xhci_hcd *xhci, struct xhci_virt_ep *ep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514) struct xhci_ring *ep_ring, struct xhci_td *td,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) union xhci_trb *ep_trb, struct xhci_transfer_event *event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517) struct xhci_slot_ctx *slot_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) u32 trb_comp_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) u32 remaining, requested, ep_trb_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) slot_ctx = xhci_get_slot_ctx(xhci, ep->vdev->out_ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) remaining = EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524) ep_trb_len = TRB_LEN(le32_to_cpu(ep_trb->generic.field[2]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) requested = td->urb->transfer_buffer_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) switch (trb_comp_code) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528) case COMP_SUCCESS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) ep_ring->err_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530) /* handle success with untransferred data as short packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531) if (ep_trb != td->last_trb || remaining) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532) xhci_warn(xhci, "WARN Successful completion on short TX\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) xhci_dbg(xhci, "ep %#x - asked for %d bytes, %d bytes untransferred\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534) td->urb->ep->desc.bEndpointAddress,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535) requested, remaining);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537) td->status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539) case COMP_SHORT_PACKET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540) xhci_dbg(xhci, "ep %#x - asked for %d bytes, %d bytes untransferred\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) td->urb->ep->desc.bEndpointAddress,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542) requested, remaining);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543) td->status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545) case COMP_STOPPED_SHORT_PACKET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546) td->urb->actual_length = remaining;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547) goto finish_td;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) case COMP_STOPPED_LENGTH_INVALID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549) /* stopped on ep trb with invalid length, exclude it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) ep_trb_len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551) remaining = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553) case COMP_USB_TRANSACTION_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554) if (xhci->quirks & XHCI_NO_SOFT_RETRY ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555) (ep_ring->err_count++ > MAX_SOFT_RETRY) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556) le32_to_cpu(slot_ctx->tt_info) & TT_SLOT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559) td->status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561) xhci_handle_halted_endpoint(xhci, ep, ep_ring->stream_id, td,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562) EP_SOFT_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565) /* do nothing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569) if (ep_trb == td->last_trb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570) td->urb->actual_length = requested - remaining;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572) td->urb->actual_length =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) sum_trb_lengths(xhci, ep_ring, ep_trb) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574) ep_trb_len - remaining;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575) finish_td:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576) if (remaining > requested) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577) xhci_warn(xhci, "bad transfer trb length %d in event trb\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578) remaining);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579) td->urb->actual_length = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582) return finish_td(xhci, ep, ep_ring, td, trb_comp_code);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586) * If this function returns an error condition, it means it got a Transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587) * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588) * At this point, the host controller is probably hosed and should be reset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590) static int handle_tx_event(struct xhci_hcd *xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591) struct xhci_transfer_event *event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593) struct xhci_virt_ep *ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) struct xhci_ring *ep_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595) unsigned int slot_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596) int ep_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597) struct xhci_td *td = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598) dma_addr_t ep_trb_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599) struct xhci_segment *ep_seg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600) union xhci_trb *ep_trb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601) int status = -EINPROGRESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602) struct xhci_ep_ctx *ep_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603) struct list_head *tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604) u32 trb_comp_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605) int td_num = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606) bool handling_skipped_tds = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608) slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609) ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610) trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611) ep_trb_dma = le64_to_cpu(event->buffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613) ep = xhci_get_virt_ep(xhci, slot_id, ep_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614) if (!ep) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615) xhci_err(xhci, "ERROR Invalid Transfer event\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619) ep_ring = xhci_dma_to_transfer_ring(ep, ep_trb_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620) ep_ctx = xhci_get_ep_ctx(xhci, ep->vdev->out_ctx, ep_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622) if (GET_EP_CTX_STATE(ep_ctx) == EP_STATE_DISABLED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623) xhci_err(xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624) "ERROR Transfer event for disabled endpoint slot %u ep %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625) slot_id, ep_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629) /* Some transfer events don't always point to a trb, see xhci 4.17.4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630) if (!ep_ring) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631) switch (trb_comp_code) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632) case COMP_STALL_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633) case COMP_USB_TRANSACTION_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634) case COMP_INVALID_STREAM_TYPE_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635) case COMP_INVALID_STREAM_ID_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636) xhci_handle_halted_endpoint(xhci, ep, 0, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637) EP_SOFT_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638) goto cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639) case COMP_RING_UNDERRUN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640) case COMP_RING_OVERRUN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641) case COMP_STOPPED_LENGTH_INVALID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642) goto cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644) xhci_err(xhci, "ERROR Transfer event for unknown stream ring slot %u ep %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645) slot_id, ep_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650) /* Count current td numbers if ep->skip is set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651) if (ep->skip) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652) list_for_each(tmp, &ep_ring->td_list)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653) td_num++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656) /* Look for common error cases */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657) switch (trb_comp_code) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658) /* Skip codes that require special handling depending on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659) * transfer type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661) case COMP_SUCCESS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662) if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664) if (xhci->quirks & XHCI_TRUST_TX_LENGTH ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665) ep_ring->last_td_was_short)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666) trb_comp_code = COMP_SHORT_PACKET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668) xhci_warn_ratelimited(xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669) "WARN Successful completion on short TX for slot %u ep %u: needs XHCI_TRUST_TX_LENGTH quirk?\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670) slot_id, ep_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671) case COMP_SHORT_PACKET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673) /* Completion codes for endpoint stopped state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674) case COMP_STOPPED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675) xhci_dbg(xhci, "Stopped on Transfer TRB for slot %u ep %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2676) slot_id, ep_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2677) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2678) case COMP_STOPPED_LENGTH_INVALID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2679) xhci_dbg(xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2680) "Stopped on No-op or Link TRB for slot %u ep %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2681) slot_id, ep_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2682) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2683) case COMP_STOPPED_SHORT_PACKET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2684) xhci_dbg(xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2685) "Stopped with short packet transfer detected for slot %u ep %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2686) slot_id, ep_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2687) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2688) /* Completion codes for endpoint halted state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2689) case COMP_STALL_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2690) xhci_dbg(xhci, "Stalled endpoint for slot %u ep %u\n", slot_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2691) ep_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2692) status = -EPIPE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2693) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2694) case COMP_SPLIT_TRANSACTION_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2695) xhci_dbg(xhci, "Split transaction error for slot %u ep %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2696) slot_id, ep_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2697) status = -EPROTO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2698) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2699) case COMP_USB_TRANSACTION_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2700) xhci_dbg(xhci, "Transfer error for slot %u ep %u on endpoint\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2701) slot_id, ep_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2702) status = -EPROTO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2703) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2704) case COMP_BABBLE_DETECTED_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2705) xhci_dbg(xhci, "Babble error for slot %u ep %u on endpoint\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2706) slot_id, ep_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2707) status = -EOVERFLOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2708) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2709) /* Completion codes for endpoint error state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2710) case COMP_TRB_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2711) xhci_warn(xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2712) "WARN: TRB error for slot %u ep %u on endpoint\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2713) slot_id, ep_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2714) status = -EILSEQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2715) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2716) /* completion codes not indicating endpoint state change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2717) case COMP_DATA_BUFFER_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2718) xhci_warn(xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2719) "WARN: HC couldn't access mem fast enough for slot %u ep %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2720) slot_id, ep_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2721) status = -ENOSR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2722) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2723) case COMP_BANDWIDTH_OVERRUN_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2724) xhci_warn(xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2725) "WARN: bandwidth overrun event for slot %u ep %u on endpoint\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2726) slot_id, ep_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2727) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2728) case COMP_ISOCH_BUFFER_OVERRUN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2729) xhci_warn(xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2730) "WARN: buffer overrun event for slot %u ep %u on endpoint",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2731) slot_id, ep_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2732) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2733) case COMP_RING_UNDERRUN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2734) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2735) * When the Isoch ring is empty, the xHC will generate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2736) * a Ring Overrun Event for IN Isoch endpoint or Ring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2737) * Underrun Event for OUT Isoch endpoint.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2738) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2739) xhci_dbg(xhci, "underrun event on endpoint\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2740) if (!list_empty(&ep_ring->td_list))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2741) xhci_dbg(xhci, "Underrun Event for slot %d ep %d "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2742) "still with TDs queued?\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2743) TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2744) ep_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2745) goto cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2746) case COMP_RING_OVERRUN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2747) xhci_dbg(xhci, "overrun event on endpoint\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2748) if (!list_empty(&ep_ring->td_list))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2749) xhci_dbg(xhci, "Overrun Event for slot %d ep %d "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2750) "still with TDs queued?\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2751) TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2752) ep_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2753) goto cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2754) case COMP_MISSED_SERVICE_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2755) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2756) * When encounter missed service error, one or more isoc tds
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2757) * may be missed by xHC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2758) * Set skip flag of the ep_ring; Complete the missed tds as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2759) * short transfer when process the ep_ring next time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2760) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2761) ep->skip = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2762) xhci_dbg(xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2763) "Miss service interval error for slot %u ep %u, set skip flag\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2764) slot_id, ep_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2765) goto cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2766) case COMP_NO_PING_RESPONSE_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2767) ep->skip = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2768) xhci_dbg(xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2769) "No Ping response error for slot %u ep %u, Skip one Isoc TD\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2770) slot_id, ep_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2771) goto cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2773) case COMP_INCOMPATIBLE_DEVICE_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2774) /* needs disable slot command to recover */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2775) xhci_warn(xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2776) "WARN: detect an incompatible device for slot %u ep %u",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2777) slot_id, ep_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2778) status = -EPROTO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2779) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2780) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2781) if (xhci_is_vendor_info_code(xhci, trb_comp_code)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2782) status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2783) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2784) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2785) xhci_warn(xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2786) "ERROR Unknown event condition %u for slot %u ep %u , HC probably busted\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2787) trb_comp_code, slot_id, ep_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2788) goto cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2789) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2791) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2792) /* This TRB should be in the TD at the head of this ring's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2793) * TD list.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2794) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2795) if (list_empty(&ep_ring->td_list)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2796) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2797) * Don't print wanings if it's due to a stopped endpoint
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2798) * generating an extra completion event if the device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2799) * was suspended. Or, a event for the last TRB of a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2800) * short TD we already got a short event for.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2801) * The short TD is already removed from the TD list.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2802) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2804) if (!(trb_comp_code == COMP_STOPPED ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2805) trb_comp_code == COMP_STOPPED_LENGTH_INVALID ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2806) ep_ring->last_td_was_short)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2807) xhci_warn(xhci, "WARN Event TRB for slot %d ep %d with no TDs queued?\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2808) TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2809) ep_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2810) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2811) if (ep->skip) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2812) ep->skip = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2813) xhci_dbg(xhci, "td_list is empty while skip flag set. Clear skip flag for slot %u ep %u.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2814) slot_id, ep_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2815) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2816) if (trb_comp_code == COMP_STALL_ERROR ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2817) xhci_requires_manual_halt_cleanup(xhci, ep_ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2818) trb_comp_code)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2819) xhci_handle_halted_endpoint(xhci, ep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2820) ep_ring->stream_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2821) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2822) EP_HARD_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2823) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2824) goto cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2825) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2827) /* We've skipped all the TDs on the ep ring when ep->skip set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2828) if (ep->skip && td_num == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2829) ep->skip = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2830) xhci_dbg(xhci, "All tds on the ep_ring skipped. Clear skip flag for slot %u ep %u.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2831) slot_id, ep_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2832) goto cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2833) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2835) td = list_first_entry(&ep_ring->td_list, struct xhci_td,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2836) td_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2837) if (ep->skip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2838) td_num--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2840) /* Is this a TRB in the currently executing TD? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2841) ep_seg = trb_in_td(xhci, ep_ring->deq_seg, ep_ring->dequeue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2842) td->last_trb, ep_trb_dma, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2844) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2845) * Skip the Force Stopped Event. The event_trb(event_dma) of FSE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2846) * is not in the current TD pointed by ep_ring->dequeue because
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2847) * that the hardware dequeue pointer still at the previous TRB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2848) * of the current TD. The previous TRB maybe a Link TD or the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2849) * last TRB of the previous TD. The command completion handle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2850) * will take care the rest.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2851) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2852) if (!ep_seg && (trb_comp_code == COMP_STOPPED ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2853) trb_comp_code == COMP_STOPPED_LENGTH_INVALID)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2854) goto cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2855) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2857) if (!ep_seg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2858) if (!ep->skip ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2859) !usb_endpoint_xfer_isoc(&td->urb->ep->desc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2860) /* Some host controllers give a spurious
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2861) * successful event after a short transfer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2862) * Ignore it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2863) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2864) if ((xhci->quirks & XHCI_SPURIOUS_SUCCESS) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2865) ep_ring->last_td_was_short) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2866) ep_ring->last_td_was_short = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2867) goto cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2868) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2869) /* HC is busted, give up! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2870) xhci_err(xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2871) "ERROR Transfer event TRB DMA ptr not "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2872) "part of current TD ep_index %d "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2873) "comp_code %u\n", ep_index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2874) trb_comp_code);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2875) trb_in_td(xhci, ep_ring->deq_seg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2876) ep_ring->dequeue, td->last_trb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2877) ep_trb_dma, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2878) return -ESHUTDOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2879) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2881) skip_isoc_td(xhci, td, ep, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2882) goto cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2883) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2884) if (trb_comp_code == COMP_SHORT_PACKET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2885) ep_ring->last_td_was_short = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2886) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2887) ep_ring->last_td_was_short = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2889) if (ep->skip) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2890) xhci_dbg(xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2891) "Found td. Clear skip flag for slot %u ep %u.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2892) slot_id, ep_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2893) ep->skip = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2894) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2896) ep_trb = &ep_seg->trbs[(ep_trb_dma - ep_seg->dma) /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2897) sizeof(*ep_trb)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2899) trace_xhci_handle_transfer(ep_ring,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2900) (struct xhci_generic_trb *) ep_trb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2902) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2903) * No-op TRB could trigger interrupts in a case where
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2904) * a URB was killed and a STALL_ERROR happens right
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2905) * after the endpoint ring stopped. Reset the halted
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2906) * endpoint. Otherwise, the endpoint remains stalled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2907) * indefinitely.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2908) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2910) if (trb_is_noop(ep_trb)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2911) if (trb_comp_code == COMP_STALL_ERROR ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2912) xhci_requires_manual_halt_cleanup(xhci, ep_ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2913) trb_comp_code))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2914) xhci_handle_halted_endpoint(xhci, ep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2915) ep_ring->stream_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2916) td, EP_HARD_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2917) goto cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2918) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2920) td->status = status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2922) /* update the urb's actual_length and give back to the core */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2923) if (usb_endpoint_xfer_control(&td->urb->ep->desc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2924) process_ctrl_td(xhci, ep, ep_ring, td, ep_trb, event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2925) else if (usb_endpoint_xfer_isoc(&td->urb->ep->desc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2926) process_isoc_td(xhci, ep, ep_ring, td, ep_trb, event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2927) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2928) process_bulk_intr_td(xhci, ep, ep_ring, td, ep_trb, event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2929) cleanup:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2930) handling_skipped_tds = ep->skip &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2931) trb_comp_code != COMP_MISSED_SERVICE_ERROR &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2932) trb_comp_code != COMP_NO_PING_RESPONSE_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2934) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2935) * Do not update event ring dequeue pointer if we're in a loop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2936) * processing missed tds.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2937) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2938) if (!handling_skipped_tds)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2939) inc_deq(xhci, xhci->event_ring);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2941) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2942) * If ep->skip is set, it means there are missed tds on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2943) * endpoint ring need to take care of.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2944) * Process them as short transfer until reach the td pointed by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2945) * the event.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2946) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2947) } while (handling_skipped_tds);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2949) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2951) err_out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2952) xhci_err(xhci, "@%016llx %08x %08x %08x %08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2953) (unsigned long long) xhci_trb_virt_to_dma(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2954) xhci->event_ring->deq_seg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2955) xhci->event_ring->dequeue),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2956) lower_32_bits(le64_to_cpu(event->buffer)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2957) upper_32_bits(le64_to_cpu(event->buffer)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2958) le32_to_cpu(event->transfer_len),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2959) le32_to_cpu(event->flags));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2960) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2961) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2963) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2964) * This function handles all OS-owned events on the event ring. It may drop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2965) * xhci->lock between event processing (e.g. to pass up port status changes).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2966) * Returns >0 for "possibly more events to process" (caller should call again),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2967) * otherwise 0 if done. In future, <0 returns should indicate error code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2968) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2969) int xhci_handle_event(struct xhci_hcd *xhci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2970) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2971) union xhci_trb *event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2972) int update_ptrs = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2973) u32 trb_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2974) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2976) /* Event ring hasn't been allocated yet. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2977) if (!xhci->event_ring || !xhci->event_ring->dequeue) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2978) xhci_err(xhci, "ERROR event ring not ready\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2979) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2980) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2982) event = xhci->event_ring->dequeue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2983) /* Does the HC or OS own the TRB? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2984) if ((le32_to_cpu(event->event_cmd.flags) & TRB_CYCLE) !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2985) xhci->event_ring->cycle_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2986) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2988) trace_xhci_handle_event(xhci->event_ring, &event->generic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2990) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2991) * Barrier between reading the TRB_CYCLE (valid) flag above and any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2992) * speculative reads of the event's flags/data below.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2993) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2994) rmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2995) trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(event->event_cmd.flags));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2996) /* FIXME: Handle more event types. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2998) switch (trb_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2999) case TRB_COMPLETION:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3000) handle_cmd_completion(xhci, &event->event_cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3001) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3002) case TRB_PORT_STATUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3003) handle_port_status(xhci, event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3004) update_ptrs = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3005) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3006) case TRB_TRANSFER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3007) ret = handle_tx_event(xhci, &event->trans_event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3008) if (ret >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3009) update_ptrs = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3010) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3011) case TRB_DEV_NOTE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3012) handle_device_notification(xhci, event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3013) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3014) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3015) if (trb_type >= TRB_VENDOR_DEFINED_LOW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3016) handle_vendor_event(xhci, event, trb_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3017) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3018) xhci_warn(xhci, "ERROR unknown event type %d\n", trb_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3019) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3020) /* Any of the above functions may drop and re-acquire the lock, so check
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3021) * to make sure a watchdog timer didn't mark the host as non-responsive.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3022) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3023) if (xhci->xhc_state & XHCI_STATE_DYING) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3024) xhci_dbg(xhci, "xHCI host dying, returning from "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3025) "event handler.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3026) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3027) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3029) if (update_ptrs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3030) /* Update SW event ring dequeue pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3031) inc_deq(xhci, xhci->event_ring);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3033) /* Are there more items on the event ring? Caller will call us again to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3034) * check.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3035) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3036) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3037) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3038) EXPORT_SYMBOL_GPL(xhci_handle_event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3040) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3041) * Update Event Ring Dequeue Pointer:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3042) * - When all events have finished
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3043) * - To avoid "Event Ring Full Error" condition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3044) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3045) void xhci_update_erst_dequeue(struct xhci_hcd *xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3046) union xhci_trb *event_ring_deq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3047) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3048) u64 temp_64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3049) dma_addr_t deq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3051) temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3052) /* If necessary, update the HW's version of the event ring deq ptr. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3053) if (event_ring_deq != xhci->event_ring->dequeue) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3054) deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3055) xhci->event_ring->dequeue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3056) if (deq == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3057) xhci_warn(xhci, "WARN something wrong with SW event ring dequeue ptr\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3058) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3059) * Per 4.9.4, Software writes to the ERDP register shall
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3060) * always advance the Event Ring Dequeue Pointer value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3061) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3062) if ((temp_64 & (u64) ~ERST_PTR_MASK) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3063) ((u64) deq & (u64) ~ERST_PTR_MASK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3064) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3066) /* Update HC event ring dequeue pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3067) temp_64 &= ERST_PTR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3068) temp_64 |= ((u64) deq & (u64) ~ERST_PTR_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3069) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3071) /* Clear the event handler busy flag (RW1C) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3072) temp_64 |= ERST_EHB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3073) xhci_write_64(xhci, temp_64, &xhci->ir_set->erst_dequeue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3074) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3075) EXPORT_SYMBOL_GPL(xhci_update_erst_dequeue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3077) static irqreturn_t xhci_vendor_queue_irq_work(struct xhci_hcd *xhci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3078) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3079) struct xhci_vendor_ops *ops = xhci_vendor_get_ops(xhci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3081) if (ops && ops->queue_irq_work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3082) return ops->queue_irq_work(xhci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3083) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3084) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3086) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3087) * xHCI spec says we can get an interrupt, and if the HC has an error condition,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3088) * we might get bad data out of the event ring. Section 4.10.2.7 has a list of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3089) * indicators of an event TRB error, but we check the status *first* to be safe.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3090) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3091) irqreturn_t xhci_irq(struct usb_hcd *hcd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3092) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3093) struct xhci_hcd *xhci = hcd_to_xhci(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3094) union xhci_trb *event_ring_deq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3095) irqreturn_t ret = IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3096) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3097) u64 temp_64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3098) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3099) int event_loop = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3101) spin_lock_irqsave(&xhci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3102) /* Check if the xHC generated the interrupt, or the irq is shared */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3103) status = readl(&xhci->op_regs->status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3104) if (status == ~(u32)0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3105) xhci_hc_died(xhci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3106) ret = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3107) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3110) if (!(status & STS_EINT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3111) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3113) if (status & STS_FATAL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3114) xhci_warn(xhci, "WARNING: Host System Error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3115) xhci_halt(xhci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3116) ret = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3117) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3120) ret = xhci_vendor_queue_irq_work(xhci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3121) if (ret == IRQ_HANDLED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3122) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3124) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3125) * Clear the op reg interrupt status first,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3126) * so we can receive interrupts from other MSI-X interrupters.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3127) * Write 1 to clear the interrupt status.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3128) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3129) status |= STS_EINT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3130) writel(status, &xhci->op_regs->status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3132) if (!hcd->msi_enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3133) u32 irq_pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3134) irq_pending = readl(&xhci->ir_set->irq_pending);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3135) irq_pending |= IMAN_IP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3136) writel(irq_pending, &xhci->ir_set->irq_pending);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3139) if (xhci->xhc_state & XHCI_STATE_DYING ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3140) xhci->xhc_state & XHCI_STATE_HALTED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3141) xhci_dbg(xhci, "xHCI dying, ignoring interrupt. "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3142) "Shouldn't IRQs be disabled?\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3143) /* Clear the event handler busy flag (RW1C);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3144) * the event ring should be empty.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3145) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3146) temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3147) xhci_write_64(xhci, temp_64 | ERST_EHB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3148) &xhci->ir_set->erst_dequeue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3149) ret = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3150) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3153) event_ring_deq = xhci->event_ring->dequeue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3154) /* FIXME this should be a delayed service routine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3155) * that clears the EHB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3156) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3157) while (xhci_handle_event(xhci) > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3158) if (event_loop++ < TRBS_PER_SEGMENT / 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3159) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3160) xhci_update_erst_dequeue(xhci, event_ring_deq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3161) event_loop = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3164) xhci_update_erst_dequeue(xhci, event_ring_deq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3165) ret = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3167) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3168) spin_unlock_irqrestore(&xhci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3170) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3173) irqreturn_t xhci_msi_irq(int irq, void *hcd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3174) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3175) return xhci_irq(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3178) /**** Endpoint Ring Operations ****/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3180) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3181) * Generic function for queueing a TRB on a ring.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3182) * The caller must have checked to make sure there's room on the ring.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3183) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3184) * @more_trbs_coming: Will you enqueue more TRBs before calling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3185) * prepare_transfer()?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3186) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3187) static void queue_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3188) bool more_trbs_coming,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3189) u32 field1, u32 field2, u32 field3, u32 field4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3190) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3191) struct xhci_generic_trb *trb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3193) trb = &ring->enqueue->generic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3194) trb->field[0] = cpu_to_le32(field1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3195) trb->field[1] = cpu_to_le32(field2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3196) trb->field[2] = cpu_to_le32(field3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3197) /* make sure TRB is fully written before giving it to the controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3198) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3199) trb->field[3] = cpu_to_le32(field4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3201) trace_xhci_queue_trb(ring, trb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3203) inc_enq(xhci, ring, more_trbs_coming);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3206) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3207) * Does various checks on the endpoint ring, and makes it ready to queue num_trbs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3208) * FIXME allocate segments if the ring is full.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3209) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3210) static int prepare_ring(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3211) u32 ep_state, unsigned int num_trbs, gfp_t mem_flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3212) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3213) unsigned int num_trbs_needed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3214) unsigned int link_trb_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3216) /* Make sure the endpoint has been added to xHC schedule */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3217) switch (ep_state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3218) case EP_STATE_DISABLED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3219) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3220) * USB core changed config/interfaces without notifying us,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3221) * or hardware is reporting the wrong state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3222) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3223) xhci_warn(xhci, "WARN urb submitted to disabled ep\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3224) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3225) case EP_STATE_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3226) xhci_warn(xhci, "WARN waiting for error on ep to be cleared\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3227) /* FIXME event handling code for error needs to clear it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3228) /* XXX not sure if this should be -ENOENT or not */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3229) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3230) case EP_STATE_HALTED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3231) xhci_dbg(xhci, "WARN halted endpoint, queueing URB anyway.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3232) case EP_STATE_STOPPED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3233) case EP_STATE_RUNNING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3234) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3235) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3236) xhci_err(xhci, "ERROR unknown endpoint state for ep\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3237) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3238) * FIXME issue Configure Endpoint command to try to get the HC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3239) * back into a known state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3240) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3241) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3244) while (1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3245) if (room_on_ring(xhci, ep_ring, num_trbs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3246) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3248) if (ep_ring == xhci->cmd_ring) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3249) xhci_err(xhci, "Do not support expand command ring\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3250) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3253) xhci_dbg_trace(xhci, trace_xhci_dbg_ring_expansion,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3254) "ERROR no room on ep ring, try ring expansion");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3255) num_trbs_needed = num_trbs - ep_ring->num_trbs_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3256) if (xhci_ring_expansion(xhci, ep_ring, num_trbs_needed,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3257) mem_flags)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3258) xhci_err(xhci, "Ring expansion failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3259) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3263) while (trb_is_link(ep_ring->enqueue)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3264) /* If we're not dealing with 0.95 hardware or isoc rings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3265) * on AMD 0.96 host, clear the chain bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3266) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3267) if (!xhci_link_trb_quirk(xhci) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3268) !(ep_ring->type == TYPE_ISOC &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3269) (xhci->quirks & XHCI_AMD_0x96_HOST)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3270) ep_ring->enqueue->link.control &=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3271) cpu_to_le32(~TRB_CHAIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3272) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3273) ep_ring->enqueue->link.control |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3274) cpu_to_le32(TRB_CHAIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3276) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3277) ep_ring->enqueue->link.control ^= cpu_to_le32(TRB_CYCLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3279) /* Toggle the cycle bit after the last ring segment. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3280) if (link_trb_toggles_cycle(ep_ring->enqueue))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3281) ep_ring->cycle_state ^= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3283) ep_ring->enq_seg = ep_ring->enq_seg->next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3284) ep_ring->enqueue = ep_ring->enq_seg->trbs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3286) /* prevent infinite loop if all first trbs are link trbs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3287) if (link_trb_count++ > ep_ring->num_segs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3288) xhci_warn(xhci, "Ring is an endless link TRB loop\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3289) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3291) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3293) if (last_trb_on_seg(ep_ring->enq_seg, ep_ring->enqueue)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3294) xhci_warn(xhci, "Missing link TRB at end of ring segment\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3295) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3298) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3301) static int prepare_transfer(struct xhci_hcd *xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3302) struct xhci_virt_device *xdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3303) unsigned int ep_index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3304) unsigned int stream_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3305) unsigned int num_trbs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3306) struct urb *urb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3307) unsigned int td_index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3308) gfp_t mem_flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3309) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3310) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3311) struct urb_priv *urb_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3312) struct xhci_td *td;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3313) struct xhci_ring *ep_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3314) struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3316) ep_ring = xhci_triad_to_transfer_ring(xhci, xdev->slot_id, ep_index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3317) stream_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3318) if (!ep_ring) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3319) xhci_dbg(xhci, "Can't prepare ring for bad stream ID %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3320) stream_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3321) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3322) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3324) ret = prepare_ring(xhci, ep_ring, GET_EP_CTX_STATE(ep_ctx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3325) num_trbs, mem_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3326) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3327) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3329) urb_priv = urb->hcpriv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3330) td = &urb_priv->td[td_index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3332) INIT_LIST_HEAD(&td->td_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3333) INIT_LIST_HEAD(&td->cancelled_td_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3335) if (td_index == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3336) ret = usb_hcd_link_urb_to_ep(bus_to_hcd(urb->dev->bus), urb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3337) if (unlikely(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3338) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3341) td->urb = urb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3342) /* Add this TD to the tail of the endpoint ring's TD list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3343) list_add_tail(&td->td_list, &ep_ring->td_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3344) td->start_seg = ep_ring->enq_seg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3345) td->first_trb = ep_ring->enqueue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3347) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3350) unsigned int count_trbs(u64 addr, u64 len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3351) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3352) unsigned int num_trbs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3354) num_trbs = DIV_ROUND_UP(len + (addr & (TRB_MAX_BUFF_SIZE - 1)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3355) TRB_MAX_BUFF_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3356) if (num_trbs == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3357) num_trbs++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3359) return num_trbs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3362) static inline unsigned int count_trbs_needed(struct urb *urb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3363) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3364) return count_trbs(urb->transfer_dma, urb->transfer_buffer_length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3365) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3367) static unsigned int count_sg_trbs_needed(struct urb *urb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3368) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3369) struct scatterlist *sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3370) unsigned int i, len, full_len, num_trbs = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3372) full_len = urb->transfer_buffer_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3374) for_each_sg(urb->sg, sg, urb->num_mapped_sgs, i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3375) len = sg_dma_len(sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3376) num_trbs += count_trbs(sg_dma_address(sg), len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3377) len = min_t(unsigned int, len, full_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3378) full_len -= len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3379) if (full_len == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3380) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3381) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3383) return num_trbs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3386) static unsigned int count_isoc_trbs_needed(struct urb *urb, int i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3387) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3388) u64 addr, len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3390) addr = (u64) (urb->transfer_dma + urb->iso_frame_desc[i].offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3391) len = urb->iso_frame_desc[i].length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3393) return count_trbs(addr, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3396) static void check_trb_math(struct urb *urb, int running_total)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3397) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3398) if (unlikely(running_total != urb->transfer_buffer_length))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3399) dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated tx length, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3400) "queued %#x (%d), asked for %#x (%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3401) __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3402) urb->ep->desc.bEndpointAddress,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3403) running_total, running_total,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3404) urb->transfer_buffer_length,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3405) urb->transfer_buffer_length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3408) static void giveback_first_trb(struct xhci_hcd *xhci, int slot_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3409) unsigned int ep_index, unsigned int stream_id, int start_cycle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3410) struct xhci_generic_trb *start_trb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3411) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3412) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3413) * Pass all the TRBs to the hardware at once and make sure this write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3414) * isn't reordered.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3415) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3416) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3417) if (start_cycle)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3418) start_trb->field[3] |= cpu_to_le32(start_cycle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3419) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3420) start_trb->field[3] &= cpu_to_le32(~TRB_CYCLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3421) xhci_ring_ep_doorbell(xhci, slot_id, ep_index, stream_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3424) static void check_interval(struct xhci_hcd *xhci, struct urb *urb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3425) struct xhci_ep_ctx *ep_ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3426) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3427) int xhci_interval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3428) int ep_interval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3430) xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3431) ep_interval = urb->interval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3433) /* Convert to microframes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3434) if (urb->dev->speed == USB_SPEED_LOW ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3435) urb->dev->speed == USB_SPEED_FULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3436) ep_interval *= 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3438) /* FIXME change this to a warning and a suggestion to use the new API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3439) * to set the polling interval (once the API is added).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3440) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3441) if (xhci_interval != ep_interval) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3442) dev_dbg_ratelimited(&urb->dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3443) "Driver uses different interval (%d microframe%s) than xHCI (%d microframe%s)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3444) ep_interval, ep_interval == 1 ? "" : "s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3445) xhci_interval, xhci_interval == 1 ? "" : "s");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3446) urb->interval = xhci_interval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3447) /* Convert back to frames for LS/FS devices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3448) if (urb->dev->speed == USB_SPEED_LOW ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3449) urb->dev->speed == USB_SPEED_FULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3450) urb->interval /= 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3451) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3452) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3454) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3455) * xHCI uses normal TRBs for both bulk and interrupt. When the interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3456) * endpoint is to be serviced, the xHC will consume (at most) one TD. A TD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3457) * (comprised of sg list entries) can take several service intervals to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3458) * transmit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3459) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3460) int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3461) struct urb *urb, int slot_id, unsigned int ep_index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3462) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3463) struct xhci_ep_ctx *ep_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3465) ep_ctx = xhci_get_ep_ctx(xhci, xhci->devs[slot_id]->out_ctx, ep_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3466) check_interval(xhci, urb, ep_ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3468) return xhci_queue_bulk_tx(xhci, mem_flags, urb, slot_id, ep_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3469) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3471) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3472) * For xHCI 1.0 host controllers, TD size is the number of max packet sized
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3473) * packets remaining in the TD (*not* including this TRB).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3474) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3475) * Total TD packet count = total_packet_count =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3476) * DIV_ROUND_UP(TD size in bytes / wMaxPacketSize)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3477) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3478) * Packets transferred up to and including this TRB = packets_transferred =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3479) * rounddown(total bytes transferred including this TRB / wMaxPacketSize)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3480) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3481) * TD size = total_packet_count - packets_transferred
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3482) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3483) * For xHCI 0.96 and older, TD size field should be the remaining bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3484) * including this TRB, right shifted by 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3485) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3486) * For all hosts it must fit in bits 21:17, so it can't be bigger than 31.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3487) * This is taken care of in the TRB_TD_SIZE() macro
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3488) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3489) * The last TRB in a TD must have the TD size set to zero.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3490) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3491) static u32 xhci_td_remainder(struct xhci_hcd *xhci, int transferred,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3492) int trb_buff_len, unsigned int td_total_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3493) struct urb *urb, bool more_trbs_coming)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3494) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3495) u32 maxp, total_packet_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3497) /* MTK xHCI 0.96 contains some features from 1.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3498) if (xhci->hci_version < 0x100 && !(xhci->quirks & XHCI_MTK_HOST))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3499) return ((td_total_len - transferred) >> 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3501) /* One TRB with a zero-length data packet. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3502) if (!more_trbs_coming || (transferred == 0 && trb_buff_len == 0) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3503) trb_buff_len == td_total_len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3504) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3506) /* for MTK xHCI 0.96, TD size include this TRB, but not in 1.x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3507) if ((xhci->quirks & XHCI_MTK_HOST) && (xhci->hci_version < 0x100))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3508) trb_buff_len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3510) maxp = usb_endpoint_maxp(&urb->ep->desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3511) total_packet_count = DIV_ROUND_UP(td_total_len, maxp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3513) /* Queueing functions don't count the current TRB into transferred */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3514) return (total_packet_count - ((transferred + trb_buff_len) / maxp));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3515) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3518) static int xhci_align_td(struct xhci_hcd *xhci, struct urb *urb, u32 enqd_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3519) u32 *trb_buff_len, struct xhci_segment *seg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3520) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3521) struct device *dev = xhci_to_hcd(xhci)->self.controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3522) unsigned int unalign;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3523) unsigned int max_pkt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3524) u32 new_buff_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3525) size_t len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3527) max_pkt = usb_endpoint_maxp(&urb->ep->desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3528) unalign = (enqd_len + *trb_buff_len) % max_pkt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3530) /* we got lucky, last normal TRB data on segment is packet aligned */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3531) if (unalign == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3532) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3534) xhci_dbg(xhci, "Unaligned %d bytes, buff len %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3535) unalign, *trb_buff_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3537) /* is the last nornal TRB alignable by splitting it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3538) if (*trb_buff_len > unalign) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3539) *trb_buff_len -= unalign;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3540) xhci_dbg(xhci, "split align, new buff len %d\n", *trb_buff_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3541) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3542) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3544) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3545) * We want enqd_len + trb_buff_len to sum up to a number aligned to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3546) * number which is divisible by the endpoint's wMaxPacketSize. IOW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3547) * (size of currently enqueued TRBs + remainder) % wMaxPacketSize == 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3548) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3549) new_buff_len = max_pkt - (enqd_len % max_pkt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3551) if (new_buff_len > (urb->transfer_buffer_length - enqd_len))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3552) new_buff_len = (urb->transfer_buffer_length - enqd_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3554) /* create a max max_pkt sized bounce buffer pointed to by last trb */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3555) if (usb_urb_dir_out(urb)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3556) if (urb->num_sgs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3557) len = sg_pcopy_to_buffer(urb->sg, urb->num_sgs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3558) seg->bounce_buf, new_buff_len, enqd_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3559) if (len != new_buff_len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3560) xhci_warn(xhci, "WARN Wrong bounce buffer write length: %zu != %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3561) len, new_buff_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3562) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3563) memcpy(seg->bounce_buf, urb->transfer_buffer + enqd_len, new_buff_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3564) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3566) seg->bounce_dma = dma_map_single(dev, seg->bounce_buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3567) max_pkt, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3568) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3569) seg->bounce_dma = dma_map_single(dev, seg->bounce_buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3570) max_pkt, DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3571) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3573) if (dma_mapping_error(dev, seg->bounce_dma)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3574) /* try without aligning. Some host controllers survive */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3575) xhci_warn(xhci, "Failed mapping bounce buffer, not aligning\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3576) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3577) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3578) *trb_buff_len = new_buff_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3579) seg->bounce_len = new_buff_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3580) seg->bounce_offs = enqd_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3582) xhci_dbg(xhci, "Bounce align, new buff len %d\n", *trb_buff_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3584) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3585) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3587) /* This is very similar to what ehci-q.c qtd_fill() does */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3588) int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3589) struct urb *urb, int slot_id, unsigned int ep_index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3590) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3591) struct xhci_ring *ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3592) struct urb_priv *urb_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3593) struct xhci_td *td;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3594) struct xhci_generic_trb *start_trb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3595) struct scatterlist *sg = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3596) bool more_trbs_coming = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3597) bool need_zero_pkt = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3598) bool first_trb = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3599) unsigned int num_trbs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3600) unsigned int start_cycle, num_sgs = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3601) unsigned int enqd_len, block_len, trb_buff_len, full_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3602) int sent_len, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3603) u32 field, length_field, remainder;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3604) u64 addr, send_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3606) ring = xhci_urb_to_transfer_ring(xhci, urb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3607) if (!ring)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3608) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3610) full_len = urb->transfer_buffer_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3611) /* If we have scatter/gather list, we use it. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3612) if (urb->num_sgs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3613) num_sgs = urb->num_mapped_sgs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3614) sg = urb->sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3615) addr = (u64) sg_dma_address(sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3616) block_len = sg_dma_len(sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3617) num_trbs = count_sg_trbs_needed(urb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3618) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3619) num_trbs = count_trbs_needed(urb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3620) addr = (u64) urb->transfer_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3621) block_len = full_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3622) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3623) ret = prepare_transfer(xhci, xhci->devs[slot_id],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3624) ep_index, urb->stream_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3625) num_trbs, urb, 0, mem_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3626) if (unlikely(ret < 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3627) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3629) urb_priv = urb->hcpriv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3631) /* Deal with URB_ZERO_PACKET - need one more td/trb */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3632) if (urb->transfer_flags & URB_ZERO_PACKET && urb_priv->num_tds > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3633) need_zero_pkt = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3635) td = &urb_priv->td[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3637) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3638) * Don't give the first TRB to the hardware (by toggling the cycle bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3639) * until we've finished creating all the other TRBs. The ring's cycle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3640) * state may change as we enqueue the other TRBs, so save it too.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3641) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3642) start_trb = &ring->enqueue->generic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3643) start_cycle = ring->cycle_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3644) send_addr = addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3646) /* Queue the TRBs, even if they are zero-length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3647) for (enqd_len = 0; first_trb || enqd_len < full_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3648) enqd_len += trb_buff_len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3649) field = TRB_TYPE(TRB_NORMAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3651) /* TRB buffer should not cross 64KB boundaries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3652) trb_buff_len = TRB_BUFF_LEN_UP_TO_BOUNDARY(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3653) trb_buff_len = min_t(unsigned int, trb_buff_len, block_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3655) if (enqd_len + trb_buff_len > full_len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3656) trb_buff_len = full_len - enqd_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3658) /* Don't change the cycle bit of the first TRB until later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3659) if (first_trb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3660) first_trb = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3661) if (start_cycle == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3662) field |= TRB_CYCLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3663) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3664) field |= ring->cycle_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3666) /* Chain all the TRBs together; clear the chain bit in the last
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3667) * TRB to indicate it's the last TRB in the chain.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3668) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3669) if (enqd_len + trb_buff_len < full_len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3670) field |= TRB_CHAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3671) if (trb_is_link(ring->enqueue + 1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3672) if (xhci_align_td(xhci, urb, enqd_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3673) &trb_buff_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3674) ring->enq_seg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3675) send_addr = ring->enq_seg->bounce_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3676) /* assuming TD won't span 2 segs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3677) td->bounce_seg = ring->enq_seg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3678) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3679) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3680) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3681) if (enqd_len + trb_buff_len >= full_len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3682) field &= ~TRB_CHAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3683) field |= TRB_IOC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3684) more_trbs_coming = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3685) td->last_trb = ring->enqueue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3686) td->last_trb_seg = ring->enq_seg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3687) if (xhci_urb_suitable_for_idt(urb)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3688) memcpy(&send_addr, urb->transfer_buffer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3689) trb_buff_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3690) le64_to_cpus(&send_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3691) field |= TRB_IDT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3692) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3693) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3695) /* Only set interrupt on short packet for IN endpoints */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3696) if (usb_urb_dir_in(urb))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3697) field |= TRB_ISP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3699) /* Set the TRB length, TD size, and interrupter fields. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3700) remainder = xhci_td_remainder(xhci, enqd_len, trb_buff_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3701) full_len, urb, more_trbs_coming);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3703) length_field = TRB_LEN(trb_buff_len) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3704) TRB_TD_SIZE(remainder) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3705) TRB_INTR_TARGET(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3707) queue_trb(xhci, ring, more_trbs_coming | need_zero_pkt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3708) lower_32_bits(send_addr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3709) upper_32_bits(send_addr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3710) length_field,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3711) field);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3712) td->num_trbs++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3713) addr += trb_buff_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3714) sent_len = trb_buff_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3716) while (sg && sent_len >= block_len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3717) /* New sg entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3718) --num_sgs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3719) sent_len -= block_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3720) sg = sg_next(sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3721) if (num_sgs != 0 && sg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3722) block_len = sg_dma_len(sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3723) addr = (u64) sg_dma_address(sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3724) addr += sent_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3725) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3726) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3727) block_len -= sent_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3728) send_addr = addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3729) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3731) if (need_zero_pkt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3732) ret = prepare_transfer(xhci, xhci->devs[slot_id],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3733) ep_index, urb->stream_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3734) 1, urb, 1, mem_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3735) urb_priv->td[1].last_trb = ring->enqueue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3736) urb_priv->td[1].last_trb_seg = ring->enq_seg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3737) field = TRB_TYPE(TRB_NORMAL) | ring->cycle_state | TRB_IOC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3738) queue_trb(xhci, ring, 0, 0, 0, TRB_INTR_TARGET(0), field);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3739) urb_priv->td[1].num_trbs++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3740) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3742) check_trb_math(urb, enqd_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3743) giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3744) start_cycle, start_trb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3745) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3746) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3748) /* Caller must have locked xhci->lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3749) int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3750) struct urb *urb, int slot_id, unsigned int ep_index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3751) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3752) struct xhci_ring *ep_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3753) int num_trbs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3754) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3755) struct usb_ctrlrequest *setup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3756) struct xhci_generic_trb *start_trb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3757) int start_cycle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3758) u32 field;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3759) struct urb_priv *urb_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3760) struct xhci_td *td;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3762) ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3763) if (!ep_ring)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3764) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3766) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3767) * Need to copy setup packet into setup TRB, so we can't use the setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3768) * DMA address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3769) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3770) if (!urb->setup_packet)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3771) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3773) /* 1 TRB for setup, 1 for status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3774) num_trbs = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3775) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3776) * Don't need to check if we need additional event data and normal TRBs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3777) * since data in control transfers will never get bigger than 16MB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3778) * XXX: can we get a buffer that crosses 64KB boundaries?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3779) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3780) if (urb->transfer_buffer_length > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3781) num_trbs++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3782) ret = prepare_transfer(xhci, xhci->devs[slot_id],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3783) ep_index, urb->stream_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3784) num_trbs, urb, 0, mem_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3785) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3786) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3788) urb_priv = urb->hcpriv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3789) td = &urb_priv->td[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3790) td->num_trbs = num_trbs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3792) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3793) * Don't give the first TRB to the hardware (by toggling the cycle bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3794) * until we've finished creating all the other TRBs. The ring's cycle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3795) * state may change as we enqueue the other TRBs, so save it too.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3796) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3797) start_trb = &ep_ring->enqueue->generic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3798) start_cycle = ep_ring->cycle_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3800) /* Queue setup TRB - see section 6.4.1.2.1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3801) /* FIXME better way to translate setup_packet into two u32 fields? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3802) setup = (struct usb_ctrlrequest *) urb->setup_packet;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3803) field = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3804) field |= TRB_IDT | TRB_TYPE(TRB_SETUP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3805) if (start_cycle == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3806) field |= 0x1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3808) /* xHCI 1.0/1.1 6.4.1.2.1: Transfer Type field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3809) if ((xhci->hci_version >= 0x100) || (xhci->quirks & XHCI_MTK_HOST)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3810) if (urb->transfer_buffer_length > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3811) if (setup->bRequestType & USB_DIR_IN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3812) field |= TRB_TX_TYPE(TRB_DATA_IN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3813) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3814) field |= TRB_TX_TYPE(TRB_DATA_OUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3815) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3816) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3818) queue_trb(xhci, ep_ring, true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3819) setup->bRequestType | setup->bRequest << 8 | le16_to_cpu(setup->wValue) << 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3820) le16_to_cpu(setup->wIndex) | le16_to_cpu(setup->wLength) << 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3821) TRB_LEN(8) | TRB_INTR_TARGET(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3822) /* Immediate data in pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3823) field);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3825) /* If there's data, queue data TRBs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3826) /* Only set interrupt on short packet for IN endpoints */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3827) if (usb_urb_dir_in(urb))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3828) field = TRB_ISP | TRB_TYPE(TRB_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3829) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3830) field = TRB_TYPE(TRB_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3832) if (urb->transfer_buffer_length > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3833) u32 length_field, remainder;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3834) u64 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3836) if (xhci_urb_suitable_for_idt(urb)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3837) memcpy(&addr, urb->transfer_buffer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3838) urb->transfer_buffer_length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3839) le64_to_cpus(&addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3840) field |= TRB_IDT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3841) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3842) addr = (u64) urb->transfer_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3843) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3845) remainder = xhci_td_remainder(xhci, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3846) urb->transfer_buffer_length,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3847) urb->transfer_buffer_length,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3848) urb, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3849) length_field = TRB_LEN(urb->transfer_buffer_length) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3850) TRB_TD_SIZE(remainder) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3851) TRB_INTR_TARGET(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3852) if (setup->bRequestType & USB_DIR_IN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3853) field |= TRB_DIR_IN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3854) queue_trb(xhci, ep_ring, true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3855) lower_32_bits(addr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3856) upper_32_bits(addr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3857) length_field,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3858) field | ep_ring->cycle_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3859) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3861) /* Save the DMA address of the last TRB in the TD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3862) td->last_trb = ep_ring->enqueue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3863) td->last_trb_seg = ep_ring->enq_seg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3865) /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3866) /* If the device sent data, the status stage is an OUT transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3867) if (urb->transfer_buffer_length > 0 && setup->bRequestType & USB_DIR_IN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3868) field = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3869) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3870) field = TRB_DIR_IN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3871) queue_trb(xhci, ep_ring, false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3872) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3873) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3874) TRB_INTR_TARGET(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3875) /* Event on completion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3876) field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3878) giveback_first_trb(xhci, slot_id, ep_index, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3879) start_cycle, start_trb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3880) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3881) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3883) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3884) * The transfer burst count field of the isochronous TRB defines the number of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3885) * bursts that are required to move all packets in this TD. Only SuperSpeed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3886) * devices can burst up to bMaxBurst number of packets per service interval.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3887) * This field is zero based, meaning a value of zero in the field means one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3888) * burst. Basically, for everything but SuperSpeed devices, this field will be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3889) * zero. Only xHCI 1.0 host controllers support this field.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3890) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3891) static unsigned int xhci_get_burst_count(struct xhci_hcd *xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3892) struct urb *urb, unsigned int total_packet_count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3893) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3894) unsigned int max_burst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3896) if (xhci->hci_version < 0x100 || urb->dev->speed < USB_SPEED_SUPER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3897) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3899) max_burst = urb->ep->ss_ep_comp.bMaxBurst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3900) return DIV_ROUND_UP(total_packet_count, max_burst + 1) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3901) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3903) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3904) * Returns the number of packets in the last "burst" of packets. This field is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3905) * valid for all speeds of devices. USB 2.0 devices can only do one "burst", so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3906) * the last burst packet count is equal to the total number of packets in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3907) * TD. SuperSpeed endpoints can have up to 3 bursts. All but the last burst
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3908) * must contain (bMaxBurst + 1) number of packets, but the last burst can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3909) * contain 1 to (bMaxBurst + 1) packets.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3910) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3911) static unsigned int xhci_get_last_burst_packet_count(struct xhci_hcd *xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3912) struct urb *urb, unsigned int total_packet_count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3913) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3914) unsigned int max_burst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3915) unsigned int residue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3917) if (xhci->hci_version < 0x100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3918) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3920) if (urb->dev->speed >= USB_SPEED_SUPER) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3921) /* bMaxBurst is zero based: 0 means 1 packet per burst */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3922) max_burst = urb->ep->ss_ep_comp.bMaxBurst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3923) residue = total_packet_count % (max_burst + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3924) /* If residue is zero, the last burst contains (max_burst + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3925) * number of packets, but the TLBPC field is zero-based.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3926) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3927) if (residue == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3928) return max_burst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3929) return residue - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3930) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3931) if (total_packet_count == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3932) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3933) return total_packet_count - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3934) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3936) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3937) * Calculates Frame ID field of the isochronous TRB identifies the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3938) * target frame that the Interval associated with this Isochronous
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3939) * Transfer Descriptor will start on. Refer to 4.11.2.5 in 1.1 spec.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3940) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3941) * Returns actual frame id on success, negative value on error.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3942) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3943) static int xhci_get_isoc_frame_id(struct xhci_hcd *xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3944) struct urb *urb, int index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3945) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3946) int start_frame, ist, ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3947) int start_frame_id, end_frame_id, current_frame_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3949) if (urb->dev->speed == USB_SPEED_LOW ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3950) urb->dev->speed == USB_SPEED_FULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3951) start_frame = urb->start_frame + index * urb->interval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3952) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3953) start_frame = (urb->start_frame + index * urb->interval) >> 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3955) /* Isochronous Scheduling Threshold (IST, bits 0~3 in HCSPARAMS2):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3956) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3957) * If bit [3] of IST is cleared to '0', software can add a TRB no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3958) * later than IST[2:0] Microframes before that TRB is scheduled to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3959) * be executed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3960) * If bit [3] of IST is set to '1', software can add a TRB no later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3961) * than IST[2:0] Frames before that TRB is scheduled to be executed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3962) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3963) ist = HCS_IST(xhci->hcs_params2) & 0x7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3964) if (HCS_IST(xhci->hcs_params2) & (1 << 3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3965) ist <<= 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3967) /* Software shall not schedule an Isoch TD with a Frame ID value that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3968) * is less than the Start Frame ID or greater than the End Frame ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3969) * where:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3970) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3971) * End Frame ID = (Current MFINDEX register value + 895 ms.) MOD 2048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3972) * Start Frame ID = (Current MFINDEX register value + IST + 1) MOD 2048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3973) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3974) * Both the End Frame ID and Start Frame ID values are calculated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3975) * in microframes. When software determines the valid Frame ID value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3976) * The End Frame ID value should be rounded down to the nearest Frame
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3977) * boundary, and the Start Frame ID value should be rounded up to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3978) * nearest Frame boundary.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3979) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3980) current_frame_id = readl(&xhci->run_regs->microframe_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3981) start_frame_id = roundup(current_frame_id + ist + 1, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3982) end_frame_id = rounddown(current_frame_id + 895 * 8, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3984) start_frame &= 0x7ff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3985) start_frame_id = (start_frame_id >> 3) & 0x7ff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3986) end_frame_id = (end_frame_id >> 3) & 0x7ff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3988) xhci_dbg(xhci, "%s: index %d, reg 0x%x start_frame_id 0x%x, end_frame_id 0x%x, start_frame 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3989) __func__, index, readl(&xhci->run_regs->microframe_index),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3990) start_frame_id, end_frame_id, start_frame);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3992) if (start_frame_id < end_frame_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3993) if (start_frame > end_frame_id ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3994) start_frame < start_frame_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3995) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3996) } else if (start_frame_id > end_frame_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3997) if ((start_frame > end_frame_id &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3998) start_frame < start_frame_id))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3999) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4000) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4001) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4002) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4004) if (index == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4005) if (ret == -EINVAL || start_frame == start_frame_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4006) start_frame = start_frame_id + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4007) if (urb->dev->speed == USB_SPEED_LOW ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4008) urb->dev->speed == USB_SPEED_FULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4009) urb->start_frame = start_frame;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4010) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4011) urb->start_frame = start_frame << 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4012) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4013) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4014) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4016) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4017) xhci_warn(xhci, "Frame ID %d (reg %d, index %d) beyond range (%d, %d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4018) start_frame, current_frame_id, index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4019) start_frame_id, end_frame_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4020) xhci_warn(xhci, "Ignore frame ID field, use SIA bit instead\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4021) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4022) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4024) return start_frame;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4025) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4027) /* Check if we should generate event interrupt for a TD in an isoc URB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4028) static bool trb_block_event_intr(struct xhci_hcd *xhci, int num_tds, int i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4029) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4030) if (xhci->hci_version < 0x100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4031) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4032) /* always generate an event interrupt for the last TD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4033) if (i == num_tds - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4034) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4035) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4036) * If AVOID_BEI is set the host handles full event rings poorly,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4037) * generate an event at least every 8th TD to clear the event ring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4038) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4039) if (i && xhci->quirks & XHCI_AVOID_BEI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4040) return !!(i % 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4042) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4043) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4045) /* This is for isoc transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4046) static int xhci_queue_isoc_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4047) struct urb *urb, int slot_id, unsigned int ep_index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4048) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4049) struct xhci_ring *ep_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4050) struct urb_priv *urb_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4051) struct xhci_td *td;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4052) int num_tds, trbs_per_td;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4053) struct xhci_generic_trb *start_trb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4054) bool first_trb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4055) int start_cycle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4056) u32 field, length_field;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4057) int running_total, trb_buff_len, td_len, td_remain_len, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4058) u64 start_addr, addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4059) int i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4060) bool more_trbs_coming;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4061) struct xhci_virt_ep *xep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4062) int frame_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4064) xep = &xhci->devs[slot_id]->eps[ep_index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4065) ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4067) num_tds = urb->number_of_packets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4068) if (num_tds < 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4069) xhci_dbg(xhci, "Isoc URB with zero packets?\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4070) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4071) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4072) start_addr = (u64) urb->transfer_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4073) start_trb = &ep_ring->enqueue->generic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4074) start_cycle = ep_ring->cycle_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4076) urb_priv = urb->hcpriv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4077) /* Queue the TRBs for each TD, even if they are zero-length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4078) for (i = 0; i < num_tds; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4079) unsigned int total_pkt_count, max_pkt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4080) unsigned int burst_count, last_burst_pkt_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4081) u32 sia_frame_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4083) first_trb = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4084) running_total = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4085) addr = start_addr + urb->iso_frame_desc[i].offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4086) td_len = urb->iso_frame_desc[i].length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4087) td_remain_len = td_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4088) max_pkt = usb_endpoint_maxp(&urb->ep->desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4089) total_pkt_count = DIV_ROUND_UP(td_len, max_pkt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4091) /* A zero-length transfer still involves at least one packet. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4092) if (total_pkt_count == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4093) total_pkt_count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4094) burst_count = xhci_get_burst_count(xhci, urb, total_pkt_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4095) last_burst_pkt_count = xhci_get_last_burst_packet_count(xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4096) urb, total_pkt_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4098) trbs_per_td = count_isoc_trbs_needed(urb, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4100) ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4101) urb->stream_id, trbs_per_td, urb, i, mem_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4102) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4103) if (i == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4104) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4105) goto cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4107) td = &urb_priv->td[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4108) td->num_trbs = trbs_per_td;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4109) /* use SIA as default, if frame id is used overwrite it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4110) sia_frame_id = TRB_SIA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4111) if (!(urb->transfer_flags & URB_ISO_ASAP) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4112) HCC_CFC(xhci->hcc_params)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4113) frame_id = xhci_get_isoc_frame_id(xhci, urb, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4114) if (frame_id >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4115) sia_frame_id = TRB_FRAME_ID(frame_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4117) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4118) * Set isoc specific data for the first TRB in a TD.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4119) * Prevent HW from getting the TRBs by keeping the cycle state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4120) * inverted in the first TDs isoc TRB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4121) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4122) field = TRB_TYPE(TRB_ISOC) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4123) TRB_TLBPC(last_burst_pkt_count) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4124) sia_frame_id |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4125) (i ? ep_ring->cycle_state : !start_cycle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4127) /* xhci 1.1 with ETE uses TD_Size field for TBC, old is Rsvdz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4128) if (!xep->use_extended_tbc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4129) field |= TRB_TBC(burst_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4131) /* fill the rest of the TRB fields, and remaining normal TRBs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4132) for (j = 0; j < trbs_per_td; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4133) u32 remainder = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4135) /* only first TRB is isoc, overwrite otherwise */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4136) if (!first_trb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4137) field = TRB_TYPE(TRB_NORMAL) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4138) ep_ring->cycle_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4140) /* Only set interrupt on short packet for IN EPs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4141) if (usb_urb_dir_in(urb))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4142) field |= TRB_ISP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4144) /* Set the chain bit for all except the last TRB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4145) if (j < trbs_per_td - 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4146) more_trbs_coming = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4147) field |= TRB_CHAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4148) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4149) more_trbs_coming = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4150) td->last_trb = ep_ring->enqueue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4151) td->last_trb_seg = ep_ring->enq_seg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4152) field |= TRB_IOC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4153) if (trb_block_event_intr(xhci, num_tds, i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4154) field |= TRB_BEI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4156) /* Calculate TRB length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4157) trb_buff_len = TRB_BUFF_LEN_UP_TO_BOUNDARY(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4158) if (trb_buff_len > td_remain_len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4159) trb_buff_len = td_remain_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4161) /* Set the TRB length, TD size, & interrupter fields. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4162) remainder = xhci_td_remainder(xhci, running_total,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4163) trb_buff_len, td_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4164) urb, more_trbs_coming);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4166) length_field = TRB_LEN(trb_buff_len) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4167) TRB_INTR_TARGET(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4169) /* xhci 1.1 with ETE uses TD Size field for TBC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4170) if (first_trb && xep->use_extended_tbc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4171) length_field |= TRB_TD_SIZE_TBC(burst_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4172) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4173) length_field |= TRB_TD_SIZE(remainder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4174) first_trb = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4176) queue_trb(xhci, ep_ring, more_trbs_coming,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4177) lower_32_bits(addr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4178) upper_32_bits(addr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4179) length_field,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4180) field);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4181) running_total += trb_buff_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4183) addr += trb_buff_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4184) td_remain_len -= trb_buff_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4187) /* Check TD length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4188) if (running_total != td_len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4189) xhci_err(xhci, "ISOC TD length unmatch\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4190) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4191) goto cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4195) /* store the next frame id */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4196) if (HCC_CFC(xhci->hcc_params))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4197) xep->next_frame_id = urb->start_frame + num_tds * urb->interval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4199) if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4200) if (xhci->quirks & XHCI_AMD_PLL_FIX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4201) usb_amd_quirk_pll_disable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4203) xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4205) giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4206) start_cycle, start_trb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4207) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4208) cleanup:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4209) /* Clean up a partially enqueued isoc transfer. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4211) for (i--; i >= 0; i--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4212) list_del_init(&urb_priv->td[i].td_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4214) /* Use the first TD as a temporary variable to turn the TDs we've queued
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4215) * into No-ops with a software-owned cycle bit. That way the hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4216) * won't accidentally start executing bogus TDs when we partially
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4217) * overwrite them. td->first_trb and td->start_seg are already set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4218) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4219) urb_priv->td[0].last_trb = ep_ring->enqueue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4220) /* Every TRB except the first & last will have its cycle bit flipped. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4221) td_to_noop(xhci, ep_ring, &urb_priv->td[0], true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4223) /* Reset the ring enqueue back to the first TRB and its cycle bit. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4224) ep_ring->enqueue = urb_priv->td[0].first_trb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4225) ep_ring->enq_seg = urb_priv->td[0].start_seg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4226) ep_ring->cycle_state = start_cycle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4227) ep_ring->num_trbs_free = ep_ring->num_trbs_free_temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4228) usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4229) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4232) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4233) * Check transfer ring to guarantee there is enough room for the urb.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4234) * Update ISO URB start_frame and interval.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4235) * Update interval as xhci_queue_intr_tx does. Use xhci frame_index to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4236) * update urb->start_frame if URB_ISO_ASAP is set in transfer_flags or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4237) * Contiguous Frame ID is not supported by HC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4238) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4239) int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4240) struct urb *urb, int slot_id, unsigned int ep_index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4241) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4242) struct xhci_virt_device *xdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4243) struct xhci_ring *ep_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4244) struct xhci_ep_ctx *ep_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4245) int start_frame;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4246) int num_tds, num_trbs, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4247) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4248) struct xhci_virt_ep *xep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4249) int ist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4251) xdev = xhci->devs[slot_id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4252) xep = &xhci->devs[slot_id]->eps[ep_index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4253) ep_ring = xdev->eps[ep_index].ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4254) ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4256) num_trbs = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4257) num_tds = urb->number_of_packets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4258) for (i = 0; i < num_tds; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4259) num_trbs += count_isoc_trbs_needed(urb, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4261) /* Check the ring to guarantee there is enough room for the whole urb.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4262) * Do not insert any td of the urb to the ring if the check failed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4263) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4264) ret = prepare_ring(xhci, ep_ring, GET_EP_CTX_STATE(ep_ctx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4265) num_trbs, mem_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4266) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4267) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4269) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4270) * Check interval value. This should be done before we start to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4271) * calculate the start frame value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4272) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4273) check_interval(xhci, urb, ep_ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4275) /* Calculate the start frame and put it in urb->start_frame. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4276) if (HCC_CFC(xhci->hcc_params) && !list_empty(&ep_ring->td_list)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4277) if (GET_EP_CTX_STATE(ep_ctx) == EP_STATE_RUNNING) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4278) urb->start_frame = xep->next_frame_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4279) goto skip_start_over;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4283) start_frame = readl(&xhci->run_regs->microframe_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4284) start_frame &= 0x3fff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4285) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4286) * Round up to the next frame and consider the time before trb really
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4287) * gets scheduled by hardare.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4288) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4289) ist = HCS_IST(xhci->hcs_params2) & 0x7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4290) if (HCS_IST(xhci->hcs_params2) & (1 << 3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4291) ist <<= 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4292) start_frame += ist + XHCI_CFC_DELAY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4293) start_frame = roundup(start_frame, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4295) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4296) * Round up to the next ESIT (Endpoint Service Interval Time) if ESIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4297) * is greate than 8 microframes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4298) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4299) if (urb->dev->speed == USB_SPEED_LOW ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4300) urb->dev->speed == USB_SPEED_FULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4301) start_frame = roundup(start_frame, urb->interval << 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4302) urb->start_frame = start_frame >> 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4303) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4304) start_frame = roundup(start_frame, urb->interval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4305) urb->start_frame = start_frame;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4308) skip_start_over:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4309) ep_ring->num_trbs_free_temp = ep_ring->num_trbs_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4311) return xhci_queue_isoc_tx(xhci, mem_flags, urb, slot_id, ep_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4314) /**** Command Ring Operations ****/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4316) /* Generic function for queueing a command TRB on the command ring.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4317) * Check to make sure there's room on the command ring for one command TRB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4318) * Also check that there's room reserved for commands that must not fail.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4319) * If this is a command that must not fail, meaning command_must_succeed = TRUE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4320) * then only check for the number of reserved spots.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4321) * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4322) * because the command event handler may want to resubmit a failed command.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4323) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4324) static int queue_command(struct xhci_hcd *xhci, struct xhci_command *cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4325) u32 field1, u32 field2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4326) u32 field3, u32 field4, bool command_must_succeed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4327) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4328) int reserved_trbs = xhci->cmd_ring_reserved_trbs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4329) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4331) if ((xhci->xhc_state & XHCI_STATE_DYING) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4332) (xhci->xhc_state & XHCI_STATE_HALTED)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4333) xhci_dbg(xhci, "xHCI dying or halted, can't queue_command\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4334) return -ESHUTDOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4337) if (!command_must_succeed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4338) reserved_trbs++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4340) ret = prepare_ring(xhci, xhci->cmd_ring, EP_STATE_RUNNING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4341) reserved_trbs, GFP_ATOMIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4342) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4343) xhci_err(xhci, "ERR: No room for command on command ring\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4344) if (command_must_succeed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4345) xhci_err(xhci, "ERR: Reserved TRB counting for "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4346) "unfailable commands failed.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4347) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4350) cmd->command_trb = xhci->cmd_ring->enqueue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4352) /* if there are no other commands queued we start the timeout timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4353) if (list_empty(&xhci->cmd_list)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4354) xhci->current_cmd = cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4355) xhci_mod_cmd_timer(xhci, XHCI_CMD_DEFAULT_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4358) list_add_tail(&cmd->cmd_list, &xhci->cmd_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4360) queue_trb(xhci, xhci->cmd_ring, false, field1, field2, field3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4361) field4 | xhci->cmd_ring->cycle_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4362) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4365) /* Queue a slot enable or disable request on the command ring */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4366) int xhci_queue_slot_control(struct xhci_hcd *xhci, struct xhci_command *cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4367) u32 trb_type, u32 slot_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4368) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4369) return queue_command(xhci, cmd, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4370) TRB_TYPE(trb_type) | SLOT_ID_FOR_TRB(slot_id), false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4371) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4373) /* Queue an address device command TRB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4374) int xhci_queue_address_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4375) dma_addr_t in_ctx_ptr, u32 slot_id, enum xhci_setup_dev setup)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4376) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4377) return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4378) upper_32_bits(in_ctx_ptr), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4379) TRB_TYPE(TRB_ADDR_DEV) | SLOT_ID_FOR_TRB(slot_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4380) | (setup == SETUP_CONTEXT_ONLY ? TRB_BSR : 0), false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4381) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4383) int xhci_queue_vendor_command(struct xhci_hcd *xhci, struct xhci_command *cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4384) u32 field1, u32 field2, u32 field3, u32 field4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4385) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4386) return queue_command(xhci, cmd, field1, field2, field3, field4, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4389) /* Queue a reset device command TRB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4390) int xhci_queue_reset_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4391) u32 slot_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4392) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4393) return queue_command(xhci, cmd, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4394) TRB_TYPE(TRB_RESET_DEV) | SLOT_ID_FOR_TRB(slot_id),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4395) false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4396) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4398) /* Queue a configure endpoint command TRB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4399) int xhci_queue_configure_endpoint(struct xhci_hcd *xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4400) struct xhci_command *cmd, dma_addr_t in_ctx_ptr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4401) u32 slot_id, bool command_must_succeed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4402) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4403) return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4404) upper_32_bits(in_ctx_ptr), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4405) TRB_TYPE(TRB_CONFIG_EP) | SLOT_ID_FOR_TRB(slot_id),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4406) command_must_succeed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4407) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4409) /* Queue an evaluate context command TRB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4410) int xhci_queue_evaluate_context(struct xhci_hcd *xhci, struct xhci_command *cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4411) dma_addr_t in_ctx_ptr, u32 slot_id, bool command_must_succeed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4412) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4413) return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4414) upper_32_bits(in_ctx_ptr), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4415) TRB_TYPE(TRB_EVAL_CONTEXT) | SLOT_ID_FOR_TRB(slot_id),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4416) command_must_succeed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4417) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4419) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4420) * Suspend is set to indicate "Stop Endpoint Command" is being issued to stop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4421) * activity on an endpoint that is about to be suspended.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4422) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4423) int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, struct xhci_command *cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4424) int slot_id, unsigned int ep_index, int suspend)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4425) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4426) u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4427) u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4428) u32 type = TRB_TYPE(TRB_STOP_RING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4429) u32 trb_suspend = SUSPEND_PORT_FOR_TRB(suspend);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4431) return queue_command(xhci, cmd, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4432) trb_slot_id | trb_ep_index | type | trb_suspend, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4434) EXPORT_SYMBOL_GPL(xhci_queue_stop_endpoint);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4436) int xhci_queue_reset_ep(struct xhci_hcd *xhci, struct xhci_command *cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4437) int slot_id, unsigned int ep_index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4438) enum xhci_ep_reset_type reset_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4439) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4440) u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4441) u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4442) u32 type = TRB_TYPE(TRB_RESET_EP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4444) if (reset_type == EP_SOFT_RESET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4445) type |= TRB_TSP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4447) return queue_command(xhci, cmd, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4448) trb_slot_id | trb_ep_index | type, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4449) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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