^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * drivers/usb/host/xhci-rcar.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2014 Renesas Electronics Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #ifndef _XHCI_RCAR_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define _XHCI_RCAR_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define XHCI_RCAR_FIRMWARE_NAME_V1 "r8a779x_usb3_v1.dlmem"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define XHCI_RCAR_FIRMWARE_NAME_V2 "r8a779x_usb3_v2.dlmem"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define XHCI_RCAR_FIRMWARE_NAME_V3 "r8a779x_usb3_v3.dlmem"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #if IS_ENABLED(CONFIG_USB_XHCI_RCAR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) void xhci_rcar_start(struct usb_hcd *hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) int xhci_rcar_init_quirk(struct usb_hcd *hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) int xhci_rcar_resume_quirk(struct usb_hcd *hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) static inline void xhci_rcar_start(struct usb_hcd *hcd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) static inline int xhci_rcar_init_quirk(struct usb_hcd *hcd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) static inline int xhci_rcar_resume_quirk(struct usb_hcd *hcd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * On R-Car Gen2 and Gen3, the AC64 bit (bit 0) of HCCPARAMS1 is set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * to 1. However, these SoCs don't support 64-bit address memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * pointers. So, this driver clears the AC64 bit of xhci->hcc_params
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * to call dma_set_coherent_mask(dev, DMA_BIT_MASK(32)) in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * xhci_gen_setup() by using the XHCI_NO_64BIT_SUPPORT quirk.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * And, since the firmware/internal CPU control the USBSTS.STS_HALT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * and the process speed is down when the roothub port enters U3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * long delay for the handshake of STS_HALT is neeed in xhci_suspend()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * by using the XHCI_SLOW_SUSPEND quirk.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SET_XHCI_PLAT_PRIV_FOR_RCAR(firmware) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) .firmware_name = firmware, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) .quirks = XHCI_NO_64BIT_SUPPORT | XHCI_TRUST_TX_LENGTH | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) XHCI_SLOW_SUSPEND, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) .init_quirk = xhci_rcar_init_quirk, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) .plat_start = xhci_rcar_start, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) .resume_quirk = xhci_rcar_resume_quirk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #endif /* _XHCI_RCAR_H */