^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * xHCI host controller driver PCI Bus Glue.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2008 Intel Corp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author: Sarah Sharp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Some code borrowed from the Linux EHCI driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/acpi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "xhci.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "xhci-trace.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "xhci-pci.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define SSIC_PORT_NUM 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define SSIC_PORT_CFG2 0x880c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define SSIC_PORT_CFG2_OFFSET 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define PROG_DONE (1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define SSIC_PORT_UNUSED (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define SPARSE_DISABLE_BIT 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define SPARSE_CNTL_ENABLE 0xC12C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /* Device for a quirk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define PCI_VENDOR_ID_FRESCO_LOGIC 0x1b73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define PCI_DEVICE_ID_FRESCO_LOGIC_PDK 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1009 0x1009
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1100 0x1100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1400 0x1400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define PCI_VENDOR_ID_ETRON 0x1b6f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define PCI_DEVICE_ID_EJ168 0x7023
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI 0x8c31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI 0x9c31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI 0x9cb1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI 0x22b5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI 0xa12f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI 0x9d2f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI 0x0aa8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI 0x1aa8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define PCI_DEVICE_ID_INTEL_APL_XHCI 0x5aa8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define PCI_DEVICE_ID_INTEL_DNV_XHCI 0x19d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_XHCI 0x15b5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_XHCI 0x15b6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_XHCI 0x15c1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_XHCI 0x15db
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_XHCI 0x15d4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_XHCI 0x15e9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_XHCI 0x15ec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_XHCI 0x15f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define PCI_DEVICE_ID_INTEL_ICE_LAKE_XHCI 0x8a13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define PCI_DEVICE_ID_INTEL_CML_XHCI 0xa3af
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define PCI_DEVICE_ID_INTEL_TIGER_LAKE_XHCI 0x9a13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define PCI_DEVICE_ID_INTEL_MAPLE_RIDGE_XHCI 0x1138
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_XHCI 0x461e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define PCI_DEVICE_ID_AMD_PROMONTORYA_4 0x43b9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define PCI_DEVICE_ID_AMD_PROMONTORYA_3 0x43ba
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define PCI_DEVICE_ID_AMD_PROMONTORYA_2 0x43bb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define PCI_DEVICE_ID_AMD_PROMONTORYA_1 0x43bc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_1 0x161a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_2 0x161b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_3 0x161d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_4 0x161e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_5 0x15d6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_6 0x15d7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_7 0x161c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_8 0x161f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define PCI_DEVICE_ID_ASMEDIA_1042_XHCI 0x1042
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define PCI_DEVICE_ID_ASMEDIA_1042A_XHCI 0x1142
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define PCI_DEVICE_ID_ASMEDIA_1142_XHCI 0x1242
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define PCI_DEVICE_ID_ASMEDIA_2142_XHCI 0x2142
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define PCI_DEVICE_ID_ASMEDIA_3242_XHCI 0x3242
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) static const char hcd_name[] = "xhci_hcd";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) static struct hc_driver __read_mostly xhci_pci_hc_driver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static int xhci_pci_setup(struct usb_hcd *hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) static const struct xhci_driver_overrides xhci_pci_overrides __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) .reset = xhci_pci_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /* called after powerup, by probe or system-pm "wakeup" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * TODO: Implement finding debug ports later.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * TODO: see if there are any quirks that need to be added to handle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * new extended capabilities.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) if (!pci_set_mwi(pdev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) xhci_dbg(xhci, "MWI active\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) xhci_dbg(xhci, "Finished xhci_pci_reinit\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) struct pci_dev *pdev = to_pci_dev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) struct xhci_driver_data *driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) const struct pci_device_id *id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) id = pci_match_id(pdev->driver->id_table, pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) if (id && id->driver_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) driver_data = (struct xhci_driver_data *)id->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) xhci->quirks |= driver_data->quirks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) /* Look for vendor-specific quirks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1400)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) pdev->revision == 0x0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) xhci->quirks |= XHCI_RESET_EP_QUIRK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) "QUIRK: Fresco Logic xHC needs configure"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) " endpoint cmd after reset endpoint");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) pdev->revision == 0x4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) xhci->quirks |= XHCI_SLOW_SUSPEND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) "QUIRK: Fresco Logic xHC revision %u"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) "must be suspended extra slowly",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) pdev->revision);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) xhci->quirks |= XHCI_BROKEN_STREAMS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /* Fresco Logic confirms: all revisions of this chip do not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) * support MSI, even though some of them claim to in their PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) * capabilities.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) xhci->quirks |= XHCI_BROKEN_MSI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) "QUIRK: Fresco Logic revision %u "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) "has broken MSI implementation",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) pdev->revision);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) xhci->quirks |= XHCI_TRUST_TX_LENGTH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) xhci->quirks |= XHCI_BROKEN_STREAMS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) xhci->quirks |= XHCI_TRUST_TX_LENGTH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) if (pdev->vendor == PCI_VENDOR_ID_NEC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) xhci->quirks |= XHCI_NEC_HOST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) xhci->quirks |= XHCI_AMD_0x96_HOST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /* AMD PLL quirk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_quirk_pll_check())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) xhci->quirks |= XHCI_AMD_PLL_FIX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) if (pdev->vendor == PCI_VENDOR_ID_AMD &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) (pdev->device == 0x145c ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) pdev->device == 0x15e0 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) pdev->device == 0x15e1 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) pdev->device == 0x43bb))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) xhci->quirks |= XHCI_SUSPEND_DELAY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) if (pdev->vendor == PCI_VENDOR_ID_AMD &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) (pdev->device == 0x15e0 || pdev->device == 0x15e1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) xhci->quirks |= XHCI_SNPS_BROKEN_SUSPEND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) if (pdev->vendor == PCI_VENDOR_ID_AMD && pdev->device == 0x15e5) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) xhci->quirks |= XHCI_DISABLE_SPARSE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) xhci->quirks |= XHCI_RESET_ON_RESUME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) if (pdev->vendor == PCI_VENDOR_ID_AMD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) xhci->quirks |= XHCI_TRUST_TX_LENGTH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) if ((pdev->vendor == PCI_VENDOR_ID_AMD) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) ((pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_4) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_3) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_2) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_1)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) xhci->quirks |= XHCI_U2_DISABLE_WAKE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) xhci->quirks |= XHCI_LPM_SUPPORT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) xhci->quirks |= XHCI_INTEL_HOST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) xhci->quirks |= XHCI_AVOID_BEI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) xhci->quirks |= XHCI_EP_LIMIT_QUIRK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) xhci->limit_active_eps = 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) xhci->quirks |= XHCI_SW_BW_CHECKING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) * PPT desktop boards DH77EB and DH77DF will power back on after
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) * a few seconds of being shutdown. The fix for this is to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) * switch the ports from xHCI to EHCI on shutdown. We can't use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) * DMI information to find those particular boards (since each
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) * vendor will change the board name), so we have to key off all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) * PPT chipsets.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) xhci->quirks |= XHCI_SPURIOUS_REBOOT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) (pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) pdev->device == PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) xhci->quirks |= XHCI_SPURIOUS_REBOOT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) xhci->quirks |= XHCI_SPURIOUS_WAKEUP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) (pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) pdev->device == PCI_DEVICE_ID_INTEL_CML_XHCI)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) xhci->quirks |= XHCI_PME_STUCK_QUIRK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) xhci->quirks |= XHCI_SSIC_PORT_UNUSED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) xhci->quirks |= XHCI_INTEL_USB_ROLE_SW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) xhci->quirks |= XHCI_MISSING_CAS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) (pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_XHCI ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_XHCI ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_XHCI ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_XHCI ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_XHCI ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_XHCI ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_XHCI ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_XHCI ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) pdev->device == PCI_DEVICE_ID_INTEL_ICE_LAKE_XHCI ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) pdev->device == PCI_DEVICE_ID_INTEL_TIGER_LAKE_XHCI ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) pdev->device == PCI_DEVICE_ID_INTEL_MAPLE_RIDGE_XHCI ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) pdev->device == PCI_DEVICE_ID_INTEL_ALDER_LAKE_XHCI))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) xhci->quirks |= XHCI_DEFAULT_PM_RUNTIME_ALLOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) if (pdev->vendor == PCI_VENDOR_ID_ETRON &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) pdev->device == PCI_DEVICE_ID_EJ168) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) xhci->quirks |= XHCI_RESET_ON_RESUME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) xhci->quirks |= XHCI_TRUST_TX_LENGTH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) xhci->quirks |= XHCI_BROKEN_STREAMS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) pdev->device == 0x0014) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) xhci->quirks |= XHCI_TRUST_TX_LENGTH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) xhci->quirks |= XHCI_ZERO_64B_REGS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) pdev->device == 0x0015) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) xhci->quirks |= XHCI_RESET_ON_RESUME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) xhci->quirks |= XHCI_ZERO_64B_REGS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) if (pdev->vendor == PCI_VENDOR_ID_VIA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) xhci->quirks |= XHCI_RESET_ON_RESUME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) /* See https://bugzilla.kernel.org/show_bug.cgi?id=79511 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) if (pdev->vendor == PCI_VENDOR_ID_VIA &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) pdev->device == 0x3432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) xhci->quirks |= XHCI_BROKEN_STREAMS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) if (pdev->vendor == PCI_VENDOR_ID_VIA && pdev->device == 0x3483) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) xhci->quirks |= XHCI_LPM_SUPPORT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) xhci->quirks |= XHCI_EP_CTX_BROKEN_DCS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) pdev->device == PCI_DEVICE_ID_ASMEDIA_1042_XHCI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) xhci->quirks |= XHCI_BROKEN_STREAMS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) xhci->quirks |= XHCI_TRUST_TX_LENGTH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) xhci->quirks |= XHCI_NO_64BIT_SUPPORT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) (pdev->device == PCI_DEVICE_ID_ASMEDIA_1142_XHCI ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) pdev->device == PCI_DEVICE_ID_ASMEDIA_2142_XHCI ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) pdev->device == PCI_DEVICE_ID_ASMEDIA_3242_XHCI))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) xhci->quirks |= XHCI_NO_64BIT_SUPPORT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) xhci->quirks |= XHCI_ASMEDIA_MODIFY_FLOWCONTROL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) if (pdev->vendor == PCI_VENDOR_ID_TI && pdev->device == 0x8241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) xhci->quirks |= XHCI_LIMIT_ENDPOINT_INTERVAL_7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) if ((pdev->vendor == PCI_VENDOR_ID_BROADCOM ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) pdev->vendor == PCI_VENDOR_ID_CAVIUM) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) pdev->device == 0x9026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) xhci->quirks |= XHCI_RESET_PLL_ON_DISCONNECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) if (pdev->vendor == PCI_VENDOR_ID_AMD &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_2 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) xhci->quirks |= XHCI_NO_SOFT_RETRY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) if (pdev->vendor == PCI_VENDOR_ID_AMD &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) (pdev->device == PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_1 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) pdev->device == PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_2 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) pdev->device == PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_3 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) pdev->device == PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_4 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) pdev->device == PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_5 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) pdev->device == PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_6 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) pdev->device == PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_7 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) pdev->device == PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) xhci->quirks |= XHCI_DEFAULT_PM_RUNTIME_ALLOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) if (xhci->quirks & XHCI_RESET_ON_RESUME)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) "QUIRK: Resetting on resume");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #ifdef CONFIG_ACPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) static const guid_t intel_dsm_guid =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) GUID_INIT(0xac340cb7, 0xe901, 0x45bf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 0xb7, 0xe6, 0x2b, 0x34, 0xec, 0x93, 0x1e, 0x23);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) union acpi_object *obj;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) obj = acpi_evaluate_dsm(ACPI_HANDLE(&dev->dev), &intel_dsm_guid, 3, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) ACPI_FREE(obj);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #endif /* CONFIG_ACPI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) /* called during probe() after chip reset completes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) static int xhci_pci_setup(struct usb_hcd *hcd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) struct xhci_hcd *xhci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) int retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) xhci = hcd_to_xhci(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) if (!xhci->sbrn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) /* imod_interval is the interrupt moderation value in nanoseconds. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) xhci->imod_interval = 40000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) retval = xhci_gen_setup(hcd, xhci_pci_quirks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) if (retval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) if (!usb_hcd_is_primary_hcd(hcd))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) xhci_pme_acpi_rtd3_enable(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) /* Find any debug ports */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) return xhci_pci_reinit(xhci, pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) * We need to register our own PCI probe function (instead of the USB core's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) * function) in order to create a second roothub under xHCI.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) int retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) struct xhci_hcd *xhci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) struct usb_hcd *hcd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) struct xhci_driver_data *driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) struct reset_control *reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) driver_data = (struct xhci_driver_data *)id->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) if (driver_data && driver_data->quirks & XHCI_RENESAS_FW_QUIRK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) retval = renesas_xhci_check_request_fw(dev, id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) if (retval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) reset = devm_reset_control_get_optional_exclusive(&dev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) if (IS_ERR(reset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) return PTR_ERR(reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) reset_control_reset(reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) /* Prevent runtime suspending between USB-2 and USB-3 initialization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) pm_runtime_get_noresume(&dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) /* Register the USB 2.0 roothub.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) * FIXME: USB core must know to register the USB 2.0 roothub first.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) * This is sort of silly, because we could just set the HCD driver flags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) * to say USB 2.0, but I'm not sure what the implications would be in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) * the other parts of the HCD code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) retval = usb_hcd_pci_probe(dev, id, &xhci_pci_hc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) if (retval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) goto put_runtime_pm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) /* USB 2.0 roothub is stored in the PCI device now. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) hcd = dev_get_drvdata(&dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) xhci = hcd_to_xhci(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) xhci->reset = reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) xhci->shared_hcd = usb_create_shared_hcd(&xhci_pci_hc_driver, &dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) pci_name(dev), hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) if (!xhci->shared_hcd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) retval = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) goto dealloc_usb2_hcd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) retval = xhci_ext_cap_init(xhci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) if (retval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) goto put_usb3_hcd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) retval = usb_add_hcd(xhci->shared_hcd, dev->irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) IRQF_SHARED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) if (retval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) goto put_usb3_hcd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) /* Roothub already marked as USB 3.0 speed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) if (!(xhci->quirks & XHCI_BROKEN_STREAMS) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) HCC_MAX_PSA(xhci->hcc_params) >= 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) xhci->shared_hcd->can_do_streams = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) /* USB-2 and USB-3 roothubs initialized, allow runtime pm suspend */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) pm_runtime_put_noidle(&dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) if (xhci->quirks & XHCI_DEFAULT_PM_RUNTIME_ALLOW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) pm_runtime_allow(&dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) put_usb3_hcd:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) usb_put_hcd(xhci->shared_hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) dealloc_usb2_hcd:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) usb_hcd_pci_remove(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) put_runtime_pm:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) pm_runtime_put_noidle(&dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) static void xhci_pci_remove(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) struct xhci_hcd *xhci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) xhci = hcd_to_xhci(pci_get_drvdata(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) if (xhci->quirks & XHCI_RENESAS_FW_QUIRK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) renesas_xhci_pci_exit(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) xhci->xhc_state |= XHCI_STATE_REMOVING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) if (xhci->quirks & XHCI_DEFAULT_PM_RUNTIME_ALLOW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) pm_runtime_forbid(&dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) if (xhci->shared_hcd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) usb_remove_hcd(xhci->shared_hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) usb_put_hcd(xhci->shared_hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) xhci->shared_hcd = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) /* Workaround for spurious wakeups at shutdown with HSW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) pci_set_power_state(dev, PCI_D3hot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) usb_hcd_pci_remove(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) * In some Intel xHCI controllers, in order to get D3 working,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) * through a vendor specific SSIC CONFIG register at offset 0x883c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) * SSIC PORT need to be marked as "unused" before putting xHCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) * into D3. After D3 exit, the SSIC port need to be marked as "used".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) * Without this change, xHCI might not enter D3 state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) static void xhci_ssic_port_unused_quirk(struct usb_hcd *hcd, bool suspend)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) struct xhci_hcd *xhci = hcd_to_xhci(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) void __iomem *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) for (i = 0; i < SSIC_PORT_NUM; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) reg = (void __iomem *) xhci->cap_regs +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) SSIC_PORT_CFG2 +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) i * SSIC_PORT_CFG2_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) /* Notify SSIC that SSIC profile programming is not done. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) val = readl(reg) & ~PROG_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) writel(val, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) /* Mark SSIC port as unused(suspend) or used(resume) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) val = readl(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) if (suspend)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) val |= SSIC_PORT_UNUSED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) val &= ~SSIC_PORT_UNUSED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) writel(val, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) /* Notify SSIC that SSIC profile programming is done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) val = readl(reg) | PROG_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) writel(val, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) readl(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) * Make sure PME works on some Intel xHCI controllers by writing 1 to clear
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) * the Internal PME flag bit in vendor specific PMCTRL register at offset 0x80a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) static void xhci_pme_quirk(struct usb_hcd *hcd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) struct xhci_hcd *xhci = hcd_to_xhci(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) void __iomem *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) reg = (void __iomem *) xhci->cap_regs + 0x80a4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) val = readl(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) writel(val | BIT(28), reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) readl(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) static void xhci_sparse_control_quirk(struct usb_hcd *hcd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) reg = readl(hcd->regs + SPARSE_CNTL_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) reg &= ~BIT(SPARSE_DISABLE_BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) writel(reg, hcd->regs + SPARSE_CNTL_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) struct xhci_hcd *xhci = hcd_to_xhci(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) * Systems with the TI redriver that loses port status change events
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) * need to have the registers polled during D3, so avoid D3cold.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) if (xhci->quirks & XHCI_COMP_MODE_QUIRK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) pci_d3cold_disable(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) xhci_pme_quirk(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) if (xhci->quirks & XHCI_SSIC_PORT_UNUSED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) xhci_ssic_port_unused_quirk(hcd, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) if (xhci->quirks & XHCI_DISABLE_SPARSE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) xhci_sparse_control_quirk(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) ret = xhci_suspend(xhci, do_wakeup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) if (ret && (xhci->quirks & XHCI_SSIC_PORT_UNUSED))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) xhci_ssic_port_unused_quirk(hcd, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) static int xhci_pci_resume(struct usb_hcd *hcd, bool hibernated)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) struct xhci_hcd *xhci = hcd_to_xhci(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) int retval = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) reset_control_reset(xhci->reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) /* The BIOS on systems with the Intel Panther Point chipset may or may
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) * not support xHCI natively. That means that during system resume, it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) * may switch the ports back to EHCI so that users can use their
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) * keyboard to select a kernel from GRUB after resume from hibernate.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) * The BIOS is supposed to remember whether the OS had xHCI ports
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) * enabled before resume, and switch the ports back to xHCI when the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) * BIOS/OS semaphore is written, but we all know we can't trust BIOS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) * writers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) * Unconditionally switch the ports back to xHCI after a system resume.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) * It should not matter whether the EHCI or xHCI controller is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) * resumed first. It's enough to do the switchover in xHCI because
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) * USB core won't notice anything as the hub driver doesn't start
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) * running again until after all the devices (including both EHCI and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) * xHCI host controllers) have been resumed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) if (pdev->vendor == PCI_VENDOR_ID_INTEL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) usb_enable_intel_xhci_ports(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) if (xhci->quirks & XHCI_SSIC_PORT_UNUSED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) xhci_ssic_port_unused_quirk(hcd, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) xhci_pme_quirk(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) retval = xhci_resume(xhci, hibernated);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) static void xhci_pci_shutdown(struct usb_hcd *hcd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) struct xhci_hcd *xhci = hcd_to_xhci(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) xhci_shutdown(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) /* Yet another workaround for spurious wakeups at shutdown with HSW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) pci_set_power_state(pdev, PCI_D3hot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) #endif /* CONFIG_PM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) /*-------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) static const struct xhci_driver_data reneses_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) .quirks = XHCI_RENESAS_FW_QUIRK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) .firmware = "renesas_usb_fw.mem",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) /* PCI driver selection metadata; PCI hotplugging uses this */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) static const struct pci_device_id pci_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) { PCI_DEVICE(0x1912, 0x0014),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) .driver_data = (unsigned long)&reneses_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) { PCI_DEVICE(0x1912, 0x0015),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) .driver_data = (unsigned long)&reneses_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) /* handle any USB 3.0 xHCI controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) { /* end: all zeroes */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) MODULE_DEVICE_TABLE(pci, pci_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) * Without CONFIG_USB_XHCI_PCI_RENESAS renesas_xhci_check_request_fw() won't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) * load firmware, so don't encumber the xhci-pci driver with it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) #if IS_ENABLED(CONFIG_USB_XHCI_PCI_RENESAS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) MODULE_FIRMWARE("renesas_usb_fw.mem");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) /* pci driver glue; this is a "new style" PCI driver module */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) static struct pci_driver xhci_pci_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) .name = hcd_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) .id_table = pci_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) .probe = xhci_pci_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) .remove = xhci_pci_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) /* suspend and resume implemented later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) .shutdown = usb_hcd_pci_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) .pm = &usb_hcd_pci_pm_ops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) static int __init xhci_pci_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) xhci_init_driver(&xhci_pci_hc_driver, &xhci_pci_overrides);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) xhci_pci_hc_driver.pci_suspend = xhci_pci_suspend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) xhci_pci_hc_driver.pci_resume = xhci_pci_resume;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) xhci_pci_hc_driver.shutdown = xhci_pci_shutdown;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) return pci_register_driver(&xhci_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) module_init(xhci_pci_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) static void __exit xhci_pci_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) pci_unregister_driver(&xhci_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) module_exit(xhci_pci_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) MODULE_DESCRIPTION("xHCI PCI Host Controller Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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