^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2015 MediaTek Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Zhigang.Wei <zhigang.wei@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Chunfeng.Yun <chunfeng.yun@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #ifndef _XHCI_MTK_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define _XHCI_MTK_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include "xhci.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * To simplify scheduler algorithm, set a upper limit for ESIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * if a synchromous ep's ESIT is larger than @XHCI_MTK_MAX_ESIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * round down to the limit value, that means allocating more
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * bandwidth to it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define XHCI_MTK_MAX_ESIT 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * @ss_bit_map: used to avoid start split microframes overlay
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * @fs_bus_bw: array to keep track of bandwidth already used for FS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * @ep_list: Endpoints using this TT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) struct mu3h_sch_tt {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) DECLARE_BITMAP(ss_bit_map, XHCI_MTK_MAX_ESIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) u32 fs_bus_bw[XHCI_MTK_MAX_ESIT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) struct list_head ep_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * struct mu3h_sch_bw_info: schedule information for bandwidth domain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * @bus_bw: array to keep track of bandwidth already used at each uframes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * @bw_ep_list: eps in the bandwidth domain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * treat a HS root port as a bandwidth domain, but treat a SS root port as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * two bandwidth domains, one for IN eps and another for OUT eps.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) struct mu3h_sch_bw_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) u32 bus_bw[XHCI_MTK_MAX_ESIT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) struct list_head bw_ep_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * struct mu3h_sch_ep_info: schedule information for endpoint
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * @esit: unit is 125us, equal to 2 << Interval field in ep-context
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * @num_budget_microframes: number of continuous uframes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * (@repeat==1) scheduled within the interval
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * @bw_cost_per_microframe: bandwidth cost per microframe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * @endpoint: linked into bandwidth domain which it belongs to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * @tt_endpoint: linked into mu3h_sch_tt's list which it belongs to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * @sch_tt: mu3h_sch_tt linked into
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * @ep_type: endpoint type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * @maxpkt: max packet size of endpoint
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * @ep: address of usb_host_endpoint struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * @allocated: the bandwidth is aready allocated from bus_bw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * @offset: which uframe of the interval that transfer should be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * scheduled first time within the interval
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * @repeat: the time gap between two uframes that transfers are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * scheduled within a interval. in the simple algorithm, only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * assign 0 or 1 to it; 0 means using only one uframe in a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * interval, and 1 means using @num_budget_microframes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * continuous uframes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * @pkts: number of packets to be transferred in the scheduled uframes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * @cs_count: number of CS that host will trigger
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * @burst_mode: burst mode for scheduling. 0: normal burst mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * distribute the bMaxBurst+1 packets for a single burst
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * according to @pkts and @repeat, repeate the burst multiple
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * times; 1: distribute the (bMaxBurst+1)*(Mult+1) packets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * according to @pkts and @repeat. normal mode is used by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * default
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * @bw_budget_table: table to record bandwidth budget per microframe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) struct mu3h_sch_ep_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) u32 esit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) u32 num_budget_microframes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) u32 bw_cost_per_microframe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) struct list_head endpoint;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) struct list_head tt_endpoint;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) struct mu3h_sch_tt *sch_tt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) u32 ep_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) u32 maxpkt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) struct usb_host_endpoint *ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) enum usb_device_speed speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) bool allocated;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * mtk xHCI scheduling information put into reserved DWs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * in ep context
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) u32 offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) u32 repeat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) u32 pkts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) u32 cs_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) u32 burst_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) u32 bw_budget_table[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define MU3C_U3_PORT_MAX 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define MU3C_U2_PORT_MAX 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * struct mu3c_ippc_regs: MTK ssusb ip port control registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * @ip_pw_ctr0~3: ip power and clock control registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * @ip_pw_sts1~2: ip power and clock status registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) * @ip_xhci_cap: ip xHCI capability register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * @u3_ctrl_p[x]: ip usb3 port x control register, only low 4bytes are used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * @u2_ctrl_p[x]: ip usb2 port x control register, only low 4bytes are used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * @u2_phy_pll: usb2 phy pll control register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) struct mu3c_ippc_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) __le32 ip_pw_ctr0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) __le32 ip_pw_ctr1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) __le32 ip_pw_ctr2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) __le32 ip_pw_ctr3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) __le32 ip_pw_sts1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) __le32 ip_pw_sts2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) __le32 reserved0[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) __le32 ip_xhci_cap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) __le32 reserved1[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) __le64 u3_ctrl_p[MU3C_U3_PORT_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) __le64 u2_ctrl_p[MU3C_U2_PORT_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) __le32 reserved2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) __le32 u2_phy_pll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) __le32 reserved3[33]; /* 0x80 ~ 0xff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) struct xhci_hcd_mtk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) struct usb_hcd *hcd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) struct mu3h_sch_bw_info *sch_array;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct list_head bw_ep_chk_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) struct mu3c_ippc_regs __iomem *ippc_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) bool has_ippc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) int num_u2_ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) int num_u3_ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) int u3p_dis_msk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) struct regulator *vusb33;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) struct regulator *vbus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) struct clk *sys_clk; /* sys and mac clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct clk *xhci_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) struct clk *ref_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) struct clk *mcu_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) struct clk *dma_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) struct regmap *pericfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) struct phy **phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) int num_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) bool lpm_support;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) bool u2_lpm_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /* usb remote wakeup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) bool uwk_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) struct regmap *uwk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) u32 uwk_reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) u32 uwk_vers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static inline struct xhci_hcd_mtk *hcd_to_mtk(struct usb_hcd *hcd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) return dev_get_drvdata(hcd->self.controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) int xhci_mtk_sch_init(struct xhci_hcd_mtk *mtk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) void xhci_mtk_sch_exit(struct xhci_hcd_mtk *mtk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) int xhci_mtk_add_ep(struct usb_hcd *hcd, struct usb_device *udev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) struct usb_host_endpoint *ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) int xhci_mtk_drop_ep(struct usb_hcd *hcd, struct usb_device *udev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) struct usb_host_endpoint *ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) int xhci_mtk_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) void xhci_mtk_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #endif /* _XHCI_MTK_H_ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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