^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * xHCI host controller driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2008 Intel Corp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author: Sarah Sharp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Some code borrowed from the Linux EHCI driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <asm/unaligned.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "xhci.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "xhci-trace.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define PORT_WAKE_BITS (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define PORT_RWC_BITS (PORT_CSC | PORT_PEC | PORT_WRC | PORT_OCC | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) PORT_RC | PORT_PLC | PORT_PE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /* USB 3 BOS descriptor and a capability descriptors, combined.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * Fields will be adjusted and added later in xhci_create_usb3_bos_desc()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) static u8 usb_bos_descriptor [] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) USB_DT_BOS_SIZE, /* __u8 bLength, 5 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) USB_DT_BOS, /* __u8 bDescriptorType */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 0x0F, 0x00, /* __le16 wTotalLength, 15 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 0x1, /* __u8 bNumDeviceCaps */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* First device capability, SuperSpeed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) USB_DT_USB_SS_CAP_SIZE, /* __u8 bLength, 10 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) USB_DT_DEVICE_CAPABILITY, /* Device Capability */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) USB_SS_CAP_TYPE, /* bDevCapabilityType, SUPERSPEED_USB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 0x00, /* bmAttributes, LTM off by default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) USB_5GBPS_OPERATION, 0x00, /* wSpeedsSupported, 5Gbps only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 0x03, /* bFunctionalitySupport,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) USB 3.0 speed only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 0x00, /* bU1DevExitLat, set later. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 0x00, 0x00, /* __le16 bU2DevExitLat, set later. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /* Second device capability, SuperSpeedPlus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 0x1c, /* bLength 28, will be adjusted later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) USB_DT_DEVICE_CAPABILITY, /* Device Capability */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) USB_SSP_CAP_TYPE, /* bDevCapabilityType SUPERSPEED_PLUS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 0x00, /* bReserved 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 0x23, 0x00, 0x00, 0x00, /* bmAttributes, SSAC=3 SSIC=1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 0x01, 0x00, /* wFunctionalitySupport */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 0x00, 0x00, /* wReserved 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /* Default Sublink Speed Attributes, overwrite if custom PSI exists */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 0x34, 0x00, 0x05, 0x00, /* 5Gbps, symmetric, rx, ID = 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 0xb4, 0x00, 0x05, 0x00, /* 5Gbps, symmetric, tx, ID = 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 0x35, 0x40, 0x0a, 0x00, /* 10Gbps, SSP, symmetric, rx, ID = 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 0xb5, 0x40, 0x0a, 0x00, /* 10Gbps, SSP, symmetric, tx, ID = 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static int xhci_create_usb3_bos_desc(struct xhci_hcd *xhci, char *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) u16 wLength)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) struct xhci_port_cap *port_cap = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) int i, ssa_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) u32 temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) u16 desc_size, ssp_cap_size, ssa_size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) bool usb3_1 = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) desc_size = USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) ssp_cap_size = sizeof(usb_bos_descriptor) - desc_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /* does xhci support USB 3.1 Enhanced SuperSpeed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) for (i = 0; i < xhci->num_port_caps; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) if (xhci->port_caps[i].maj_rev == 0x03 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) xhci->port_caps[i].min_rev >= 0x01) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) usb3_1 = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) port_cap = &xhci->port_caps[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) if (usb3_1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /* does xhci provide a PSI table for SSA speed attributes? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) if (port_cap->psi_count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /* two SSA entries for each unique PSI ID, RX and TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) ssa_count = port_cap->psi_uid_count * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) ssa_size = ssa_count * sizeof(u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) ssp_cap_size -= 16; /* skip copying the default SSA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) desc_size += ssp_cap_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) memcpy(buf, &usb_bos_descriptor, min(desc_size, wLength));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) if (usb3_1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /* modify bos descriptor bNumDeviceCaps and wTotalLength */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) buf[4] += 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) put_unaligned_le16(desc_size + ssa_size, &buf[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) if (wLength < USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) return wLength;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /* Indicate whether the host has LTM support. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) temp = readl(&xhci->cap_regs->hcc_params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) if (HCC_LTC(temp))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) buf[8] |= USB_LTM_SUPPORT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /* Set the U1 and U2 exit latencies. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) if ((xhci->quirks & XHCI_LPM_SUPPORT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) temp = readl(&xhci->cap_regs->hcs_params3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) buf[12] = HCS_U1_LATENCY(temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) put_unaligned_le16(HCS_U2_LATENCY(temp), &buf[13]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /* If PSI table exists, add the custom speed attributes from it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) if (usb3_1 && port_cap->psi_count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) u32 ssp_cap_base, bm_attrib, psi, psi_mant, psi_exp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) int offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) ssp_cap_base = USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) if (wLength < desc_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) return wLength;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) buf[ssp_cap_base] = ssp_cap_size + ssa_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /* attribute count SSAC bits 4:0 and ID count SSIC bits 8:5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) bm_attrib = (ssa_count - 1) & 0x1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) bm_attrib |= (port_cap->psi_uid_count - 1) << 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) put_unaligned_le32(bm_attrib, &buf[ssp_cap_base + 4]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) if (wLength < desc_size + ssa_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) return wLength;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * Create the Sublink Speed Attributes (SSA) array.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * The xhci PSI field and USB 3.1 SSA fields are very similar,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * but link type bits 7:6 differ for values 01b and 10b.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * xhci has also only one PSI entry for a symmetric link when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * USB 3.1 requires two SSA entries (RX and TX) for every link
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) offset = desc_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) for (i = 0; i < port_cap->psi_count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) psi = port_cap->psi[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) psi &= ~USB_SSP_SUBLINK_SPEED_RSVD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) psi_exp = XHCI_EXT_PORT_PSIE(psi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) psi_mant = XHCI_EXT_PORT_PSIM(psi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /* Shift to Gbps and set SSP Link BIT(14) if 10Gpbs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) for (; psi_exp < 3; psi_exp++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) psi_mant /= 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) if (psi_mant >= 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) psi |= BIT(14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) if ((psi & PLT_MASK) == PLT_SYM) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /* Symmetric, create SSA RX and TX from one PSI entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) put_unaligned_le32(psi, &buf[offset]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) psi |= 1 << 7; /* turn entry to TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) offset += 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) if (offset >= desc_size + ssa_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) return desc_size + ssa_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) } else if ((psi & PLT_MASK) == PLT_ASYM_RX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /* Asymetric RX, flip bits 7:6 for SSA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) psi ^= PLT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) put_unaligned_le32(psi, &buf[offset]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) offset += 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) if (offset >= desc_size + ssa_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) return desc_size + ssa_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /* ssa_size is 0 for other than usb 3.1 hosts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) return desc_size + ssa_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static void xhci_common_hub_descriptor(struct xhci_hcd *xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) struct usb_hub_descriptor *desc, int ports)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) u16 temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) desc->bHubContrCurrent = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) desc->bNbrPorts = ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) temp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /* Bits 1:0 - support per-port power switching, or power always on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) if (HCC_PPC(xhci->hcc_params))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) temp |= HUB_CHAR_INDV_PORT_LPSM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) temp |= HUB_CHAR_NO_LPSM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /* Bit 2 - root hubs are not part of a compound device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) /* Bits 4:3 - individual port over current protection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) temp |= HUB_CHAR_INDV_PORT_OCPM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) /* Bits 6:5 - no TTs in root ports */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) /* Bit 7 - no port indicators */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) desc->wHubCharacteristics = cpu_to_le16(temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) /* Fill in the USB 2.0 roothub descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static void xhci_usb2_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) struct usb_hub_descriptor *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) int ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) u16 temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) __u8 port_removable[(USB_MAXCHILDREN + 1 + 7) / 8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) u32 portsc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) struct xhci_hub *rhub;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) rhub = &xhci->usb2_rhub;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) ports = rhub->num_ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) xhci_common_hub_descriptor(xhci, desc, ports);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) desc->bDescriptorType = USB_DT_HUB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) temp = 1 + (ports / 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) desc->bDescLength = USB_DT_HUB_NONVAR_SIZE + 2 * temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) desc->bPwrOn2PwrGood = 10; /* xhci section 5.4.8 says 20ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) /* The Device Removable bits are reported on a byte granularity.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) * If the port doesn't exist within that byte, the bit is set to 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) memset(port_removable, 0, sizeof(port_removable));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) for (i = 0; i < ports; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) portsc = readl(rhub->ports[i]->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) /* If a device is removable, PORTSC reports a 0, same as in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) * hub descriptor DeviceRemovable bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) if (portsc & PORT_DEV_REMOVE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) /* This math is hairy because bit 0 of DeviceRemovable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) * is reserved, and bit 1 is for port 1, etc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) port_removable[(i + 1) / 8] |= 1 << ((i + 1) % 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) /* ch11.h defines a hub descriptor that has room for USB_MAXCHILDREN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) * ports on it. The USB 2.0 specification says that there are two
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) * variable length fields at the end of the hub descriptor:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) * DeviceRemovable and PortPwrCtrlMask. But since we can have less than
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) * USB_MAXCHILDREN ports, we may need to use the DeviceRemovable array
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) * to set PortPwrCtrlMask bits. PortPwrCtrlMask must always be set to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) * 0xFF, so we initialize the both arrays (DeviceRemovable and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) * PortPwrCtrlMask) to 0xFF. Then we set the DeviceRemovable for each
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) * set of ports that actually exist.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) memset(desc->u.hs.DeviceRemovable, 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) sizeof(desc->u.hs.DeviceRemovable));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) memset(desc->u.hs.PortPwrCtrlMask, 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) sizeof(desc->u.hs.PortPwrCtrlMask));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) for (i = 0; i < (ports + 1 + 7) / 8; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) memset(&desc->u.hs.DeviceRemovable[i], port_removable[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) sizeof(__u8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) /* Fill in the USB 3.0 roothub descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) static void xhci_usb3_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) struct usb_hub_descriptor *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) int ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) u16 port_removable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) u32 portsc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) struct xhci_hub *rhub;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) rhub = &xhci->usb3_rhub;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) ports = rhub->num_ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) xhci_common_hub_descriptor(xhci, desc, ports);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) desc->bDescriptorType = USB_DT_SS_HUB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) desc->bDescLength = USB_DT_SS_HUB_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) desc->bPwrOn2PwrGood = 50; /* usb 3.1 may fail if less than 100ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) /* header decode latency should be zero for roothubs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) * see section 4.23.5.2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) desc->u.ss.bHubHdrDecLat = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) desc->u.ss.wHubDelay = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) port_removable = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) /* bit 0 is reserved, bit 1 is for port 1, etc. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) for (i = 0; i < ports; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) portsc = readl(rhub->ports[i]->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) if (portsc & PORT_DEV_REMOVE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) port_removable |= 1 << (i + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) desc->u.ss.DeviceRemovable = cpu_to_le16(port_removable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) static void xhci_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) struct usb_hub_descriptor *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) if (hcd->speed >= HCD_USB3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) xhci_usb3_hub_descriptor(hcd, xhci, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) xhci_usb2_hub_descriptor(hcd, xhci, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) static unsigned int xhci_port_speed(unsigned int port_status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) if (DEV_LOWSPEED(port_status))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) return USB_PORT_STAT_LOW_SPEED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) if (DEV_HIGHSPEED(port_status))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) return USB_PORT_STAT_HIGH_SPEED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) * FIXME: Yes, we should check for full speed, but the core uses that as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) * a default in portspeed() in usb/core/hub.c (which is the only place
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) * USB_PORT_STAT_*_SPEED is used).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) * These bits are Read Only (RO) and should be saved and written to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) * registers: 0, 3, 10:13, 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) * connect status, over-current status, port speed, and device removable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) * connect status and port speed are also sticky - meaning they're in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) * the AUX well and they aren't changed by a hot, warm, or cold reset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define XHCI_PORT_RO ((1<<0) | (1<<3) | (0xf<<10) | (1<<30))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) * These bits are RW; writing a 0 clears the bit, writing a 1 sets the bit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) * bits 5:8, 9, 14:15, 25:27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) * link state, port power, port indicator state, "wake on" enable state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define XHCI_PORT_RWS ((0xf<<5) | (1<<9) | (0x3<<14) | (0x7<<25))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) * These bits are RW; writing a 1 sets the bit, writing a 0 has no effect:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) * bit 4 (port reset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define XHCI_PORT_RW1S ((1<<4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) * These bits are RW; writing a 1 clears the bit, writing a 0 has no effect:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) * bits 1, 17, 18, 19, 20, 21, 22, 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) * port enable/disable, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) * change bits: connect, PED, warm port reset changed (reserved zero for USB 2.0 ports),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) * over-current, reset, link state, and L1 change
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define XHCI_PORT_RW1CS ((1<<1) | (0x7f<<17))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) * Bit 16 is RW, and writing a '1' to it causes the link state control to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) * latched in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define XHCI_PORT_RW ((1<<16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) * These bits are Reserved Zero (RsvdZ) and zero should be written to them:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) * bits 2, 24, 28:31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define XHCI_PORT_RZ ((1<<2) | (1<<24) | (0xf<<28))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) * Given a port state, this function returns a value that would result in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) * port being in the same state, if the value was written to the port status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) * control register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) * Save Read Only (RO) bits and save read/write bits where
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) * writing a 0 clears the bit and writing a 1 sets the bit (RWS).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) * For all other types (RW1S, RW1CS, RW, and RZ), writing a '0' has no effect.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) u32 xhci_port_state_to_neutral(u32 state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) /* Save read-only status and port state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) return (state & XHCI_PORT_RO) | (state & XHCI_PORT_RWS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) * find slot id based on port number.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) * @port: The one-based port number from one of the two split roothubs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) int xhci_find_slot_id_by_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) u16 port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) int slot_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) enum usb_device_speed speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) slot_id = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) for (i = 0; i < MAX_HC_SLOTS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) if (!xhci->devs[i] || !xhci->devs[i]->udev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) speed = xhci->devs[i]->udev->speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) if (((speed >= USB_SPEED_SUPER) == (hcd->speed >= HCD_USB3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) && xhci->devs[i]->fake_port == port) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) slot_id = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) return slot_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) * Stop device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) * It issues stop endpoint command for EP 0 to 30. And wait the last command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) * to complete.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) * suspend will set to 1, if suspend bit need to set in command.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) static int xhci_stop_device(struct xhci_hcd *xhci, int slot_id, int suspend)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) struct xhci_virt_device *virt_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) struct xhci_command *cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) virt_dev = xhci->devs[slot_id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) if (!virt_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) trace_xhci_stop_device(virt_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) cmd = xhci_alloc_command(xhci, true, GFP_NOIO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) if (!cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) spin_lock_irqsave(&xhci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) for (i = LAST_EP_INDEX; i > 0; i--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) if (virt_dev->eps[i].ring && virt_dev->eps[i].ring->dequeue) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) struct xhci_ep_ctx *ep_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) struct xhci_command *command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->out_ctx, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) /* Check ep is running, required by AMD SNPS 3.1 xHC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) if (GET_EP_CTX_STATE(ep_ctx) != EP_STATE_RUNNING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) command = xhci_alloc_command(xhci, false, GFP_NOWAIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) if (!command) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) spin_unlock_irqrestore(&xhci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) goto cmd_cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) ret = xhci_queue_stop_endpoint(xhci, command, slot_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) i, suspend);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) spin_unlock_irqrestore(&xhci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) xhci_free_command(xhci, command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) goto cmd_cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) ret = xhci_queue_stop_endpoint(xhci, cmd, slot_id, 0, suspend);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) spin_unlock_irqrestore(&xhci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) goto cmd_cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) xhci_ring_cmd_db(xhci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) spin_unlock_irqrestore(&xhci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) /* Wait for last stop endpoint command to finish */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) wait_for_completion(cmd->completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) if (cmd->status == COMP_COMMAND_ABORTED ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) cmd->status == COMP_COMMAND_RING_STOPPED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) xhci_warn(xhci, "Timeout while waiting for stop endpoint command\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) ret = -ETIME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) goto cmd_cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) ret = xhci_vendor_sync_dev_ctx(xhci, slot_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) xhci_warn(xhci, "Sync device context failed, ret=%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) cmd_cleanup:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) xhci_free_command(xhci, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) * Ring device, it rings the all doorbells unconditionally.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) void xhci_ring_device(struct xhci_hcd *xhci, int slot_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) int i, s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) struct xhci_virt_ep *ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) for (i = 0; i < LAST_EP_INDEX + 1; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) ep = &xhci->devs[slot_id]->eps[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) if (ep->ep_state & EP_HAS_STREAMS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) for (s = 1; s < ep->stream_info->num_streams; s++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) xhci_ring_ep_doorbell(xhci, slot_id, i, s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) } else if (ep->ring && ep->ring->dequeue) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) xhci_ring_ep_doorbell(xhci, slot_id, i, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) static void xhci_disable_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) u16 wIndex, __le32 __iomem *addr, u32 port_status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) /* Don't allow the USB core to disable SuperSpeed ports. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) if (hcd->speed >= HCD_USB3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) xhci_dbg(xhci, "Ignoring request to disable "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) "SuperSpeed port.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) if (xhci->quirks & XHCI_BROKEN_PORT_PED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) xhci_dbg(xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) "Broken Port Enabled/Disabled, ignoring port disable request.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) /* Write 1 to disable the port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) writel(port_status | PORT_PE, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) port_status = readl(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) xhci_dbg(xhci, "disable port %d-%d, portsc: 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) hcd->self.busnum, wIndex + 1, port_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) static void xhci_clear_port_change_bit(struct xhci_hcd *xhci, u16 wValue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) u16 wIndex, __le32 __iomem *addr, u32 port_status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) char *port_change_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) switch (wValue) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) case USB_PORT_FEAT_C_RESET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) status = PORT_RC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) port_change_bit = "reset";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) case USB_PORT_FEAT_C_BH_PORT_RESET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) status = PORT_WRC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) port_change_bit = "warm(BH) reset";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) case USB_PORT_FEAT_C_CONNECTION:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) status = PORT_CSC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) port_change_bit = "connect";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) case USB_PORT_FEAT_C_OVER_CURRENT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) status = PORT_OCC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) port_change_bit = "over-current";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) case USB_PORT_FEAT_C_ENABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) status = PORT_PEC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) port_change_bit = "enable/disable";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) case USB_PORT_FEAT_C_SUSPEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) status = PORT_PLC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) port_change_bit = "suspend/resume";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) case USB_PORT_FEAT_C_PORT_LINK_STATE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) status = PORT_PLC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) port_change_bit = "link state";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) case USB_PORT_FEAT_C_PORT_CONFIG_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) status = PORT_CEC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) port_change_bit = "config error";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) /* Should never happen */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) /* Change bits are all write 1 to clear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) writel(port_status | status, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) port_status = readl(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) xhci_dbg(xhci, "clear port%d %s change, portsc: 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) wIndex + 1, port_change_bit, port_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) struct xhci_hub *xhci_get_rhub(struct usb_hcd *hcd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) struct xhci_hcd *xhci = hcd_to_xhci(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) if (hcd->speed >= HCD_USB3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) return &xhci->usb3_rhub;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) return &xhci->usb2_rhub;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) * xhci_set_port_power() must be called with xhci->lock held.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) * It will release and re-aquire the lock while calling ACPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) * method.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) static void xhci_set_port_power(struct xhci_hcd *xhci, struct usb_hcd *hcd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) u16 index, bool on, unsigned long *flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) __must_hold(&xhci->lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) struct xhci_hub *rhub;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) struct xhci_port *port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) u32 temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) rhub = xhci_get_rhub(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) port = rhub->ports[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) temp = readl(port->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) xhci_dbg(xhci, "set port power %d-%d %s, portsc: 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) hcd->self.busnum, index + 1, on ? "ON" : "OFF", temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) temp = xhci_port_state_to_neutral(temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) /* Power on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) writel(temp | PORT_POWER, port->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) readl(port->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) /* Power off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) writel(temp & ~PORT_POWER, port->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) spin_unlock_irqrestore(&xhci->lock, *flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) temp = usb_acpi_power_manageable(hcd->self.root_hub,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) if (temp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) usb_acpi_set_power_state(hcd->self.root_hub,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) index, on);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) spin_lock_irqsave(&xhci->lock, *flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) static void xhci_port_set_test_mode(struct xhci_hcd *xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) u16 test_mode, u16 wIndex)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) u32 temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) struct xhci_port *port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) /* xhci only supports test mode for usb2 ports */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) port = xhci->usb2_rhub.ports[wIndex];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) temp = readl(port->addr + PORTPMSC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) temp |= test_mode << PORT_TEST_MODE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) writel(temp, port->addr + PORTPMSC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) xhci->test_mode = test_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) if (test_mode == USB_TEST_FORCE_ENABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) xhci_start(xhci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) static int xhci_enter_test_mode(struct xhci_hcd *xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) u16 test_mode, u16 wIndex, unsigned long *flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) __must_hold(&xhci->lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) int i, retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) /* Disable all Device Slots */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) xhci_dbg(xhci, "Disable all slots\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) spin_unlock_irqrestore(&xhci->lock, *flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) for (i = 1; i <= HCS_MAX_SLOTS(xhci->hcs_params1); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) if (!xhci->devs[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) retval = xhci_disable_slot(xhci, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) xhci_free_virt_device(xhci, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) if (retval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) xhci_err(xhci, "Failed to disable slot %d, %d. Enter test mode anyway\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) i, retval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) spin_lock_irqsave(&xhci->lock, *flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) /* Put all ports to the Disable state by clear PP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) xhci_dbg(xhci, "Disable all port (PP = 0)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) /* Power off USB3 ports*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) for (i = 0; i < xhci->usb3_rhub.num_ports; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) xhci_set_port_power(xhci, xhci->shared_hcd, i, false, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) /* Power off USB2 ports*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) for (i = 0; i < xhci->usb2_rhub.num_ports; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) xhci_set_port_power(xhci, xhci->main_hcd, i, false, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) /* Stop the controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) xhci_dbg(xhci, "Stop controller\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) retval = xhci_halt(xhci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) if (retval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) /* Disable runtime PM for test mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) pm_runtime_forbid(xhci_to_hcd(xhci)->self.controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) /* Set PORTPMSC.PTC field to enter selected test mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) /* Port is selected by wIndex. port_id = wIndex + 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) xhci_dbg(xhci, "Enter Test Mode: %d, Port_id=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) test_mode, wIndex + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) xhci_port_set_test_mode(xhci, test_mode, wIndex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) static int xhci_exit_test_mode(struct xhci_hcd *xhci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) int retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) if (!xhci->test_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) xhci_err(xhci, "Not in test mode, do nothing.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) if (xhci->test_mode == USB_TEST_FORCE_ENABLE &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) !(xhci->xhc_state & XHCI_STATE_HALTED)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) retval = xhci_halt(xhci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) if (retval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) pm_runtime_allow(xhci_to_hcd(xhci)->self.controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) xhci->test_mode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) return xhci_reset(xhci, XHCI_RESET_SHORT_USEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) void xhci_set_link_state(struct xhci_hcd *xhci, struct xhci_port *port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) u32 link_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) u32 temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) u32 portsc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) portsc = readl(port->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) temp = xhci_port_state_to_neutral(portsc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) temp &= ~PORT_PLS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) temp |= PORT_LINK_STROBE | link_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) writel(temp, port->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) xhci_dbg(xhci, "Set port %d-%d link state, portsc: 0x%x, write 0x%x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) port->rhub->hcd->self.busnum, port->hcd_portnum + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) portsc, temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) static void xhci_set_remote_wake_mask(struct xhci_hcd *xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) struct xhci_port *port, u16 wake_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) u32 temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) temp = readl(port->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) temp = xhci_port_state_to_neutral(temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_CONNECT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) temp |= PORT_WKCONN_E;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) temp &= ~PORT_WKCONN_E;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_DISCONNECT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) temp |= PORT_WKDISC_E;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) temp &= ~PORT_WKDISC_E;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_OVER_CURRENT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) temp |= PORT_WKOC_E;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) temp &= ~PORT_WKOC_E;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) writel(temp, port->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) /* Test and clear port RWC bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) void xhci_test_and_clear_bit(struct xhci_hcd *xhci, struct xhci_port *port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) u32 port_bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) u32 temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) temp = readl(port->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) if (temp & port_bit) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) temp = xhci_port_state_to_neutral(temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) temp |= port_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) writel(temp, port->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) /* Updates Link Status for super Speed port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) static void xhci_hub_report_usb3_link_state(struct xhci_hcd *xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) u32 *status, u32 status_reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) u32 pls = status_reg & PORT_PLS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) /* When the CAS bit is set then warm reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) * should be performed on port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) if (status_reg & PORT_CAS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) /* The CAS bit can be set while the port is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) * in any link state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) * Only roothubs have CAS bit, so we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) * pretend to be in compliance mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) * unless we're already in compliance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) * or the inactive state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) if (pls != USB_SS_PORT_LS_COMP_MOD &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) pls != USB_SS_PORT_LS_SS_INACTIVE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) pls = USB_SS_PORT_LS_COMP_MOD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) /* Return also connection bit -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) * hub state machine resets port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) * when this bit is set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) pls |= USB_PORT_STAT_CONNECTION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) * Resume state is an xHCI internal state. Do not report it to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) * usb core, instead, pretend to be U3, thus usb core knows
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) * it's not ready for transfer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) if (pls == XDEV_RESUME) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) *status |= USB_SS_PORT_LS_U3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) * If CAS bit isn't set but the Port is already at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) * Compliance Mode, fake a connection so the USB core
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) * notices the Compliance state and resets the port.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) * This resolves an issue generated by the SN65LVPE502CP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) * in which sometimes the port enters compliance mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) * caused by a delay on the host-device negotiation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) (pls == USB_SS_PORT_LS_COMP_MOD))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) pls |= USB_PORT_STAT_CONNECTION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) /* update status field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) *status |= pls;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) * Function for Compliance Mode Quirk.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) * This Function verifies if all xhc USB3 ports have entered U0, if so,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) * the compliance mode timer is deleted. A port won't enter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) * compliance mode if it has previously entered U0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) static void xhci_del_comp_mod_timer(struct xhci_hcd *xhci, u32 status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) u16 wIndex)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) u32 all_ports_seen_u0 = ((1 << xhci->usb3_rhub.num_ports) - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) bool port_in_u0 = ((status & PORT_PLS_MASK) == XDEV_U0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) if (!(xhci->quirks & XHCI_COMP_MODE_QUIRK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) if ((xhci->port_status_u0 != all_ports_seen_u0) && port_in_u0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) xhci->port_status_u0 |= 1 << wIndex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) if (xhci->port_status_u0 == all_ports_seen_u0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) del_timer_sync(&xhci->comp_mode_recovery_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) "All USB3 ports have entered U0 already!");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) "Compliance Mode Recovery Timer Deleted.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) static int xhci_handle_usb2_port_link_resume(struct xhci_port *port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) u32 *status, u32 portsc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) unsigned long *flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) struct xhci_bus_state *bus_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) struct xhci_hcd *xhci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) struct usb_hcd *hcd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) int slot_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) u32 wIndex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) hcd = port->rhub->hcd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) bus_state = &port->rhub->bus_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) xhci = hcd_to_xhci(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) wIndex = port->hcd_portnum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) if ((portsc & PORT_RESET) || !(portsc & PORT_PE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) *status = 0xffffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) /* did port event handler already start resume timing? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) if (!bus_state->resume_done[wIndex]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) /* If not, maybe we are in a host initated resume? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) if (test_bit(wIndex, &bus_state->resuming_ports)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) /* Host initated resume doesn't time the resume
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) * signalling using resume_done[].
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) * It manually sets RESUME state, sleeps 20ms
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) * and sets U0 state. This should probably be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) * changed, but not right now.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) /* port resume was discovered now and here,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) * start resume timing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) unsigned long timeout = jiffies +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) msecs_to_jiffies(USB_RESUME_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) set_bit(wIndex, &bus_state->resuming_ports);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) bus_state->resume_done[wIndex] = timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) mod_timer(&hcd->rh_timer, timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) usb_hcd_start_port_resume(&hcd->self, wIndex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) /* Has resume been signalled for USB_RESUME_TIME yet? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) } else if (time_after_eq(jiffies, bus_state->resume_done[wIndex])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) int time_left;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) xhci_dbg(xhci, "resume USB2 port %d-%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) hcd->self.busnum, wIndex + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) bus_state->resume_done[wIndex] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) clear_bit(wIndex, &bus_state->resuming_ports);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) set_bit(wIndex, &bus_state->rexit_ports);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) xhci_test_and_clear_bit(xhci, port, PORT_PLC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) xhci_set_link_state(xhci, port, XDEV_U0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) spin_unlock_irqrestore(&xhci->lock, *flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) time_left = wait_for_completion_timeout(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) &bus_state->rexit_done[wIndex],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) msecs_to_jiffies(XHCI_MAX_REXIT_TIMEOUT_MS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) spin_lock_irqsave(&xhci->lock, *flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) if (time_left) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) slot_id = xhci_find_slot_id_by_port(hcd, xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) wIndex + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) if (!slot_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) xhci_dbg(xhci, "slot_id is zero\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) *status = 0xffffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) xhci_ring_device(xhci, slot_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) int port_status = readl(port->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) xhci_warn(xhci, "Port resume timed out, port %d-%d: 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) hcd->self.busnum, wIndex + 1, port_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) *status |= USB_PORT_STAT_SUSPEND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) clear_bit(wIndex, &bus_state->rexit_ports);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) usb_hcd_end_port_resume(&hcd->self, wIndex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) bus_state->port_c_suspend |= 1 << wIndex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) bus_state->suspended_ports &= ~(1 << wIndex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) * The resume has been signaling for less than
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) * USB_RESUME_TIME. Report the port status as SUSPEND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) * let the usbcore check port status again and clear
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) * resume signaling later.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) *status |= USB_PORT_STAT_SUSPEND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) static u32 xhci_get_ext_port_status(u32 raw_port_status, u32 port_li)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) u32 ext_stat = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) int speed_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) /* only support rx and tx lane counts of 1 in usb3.1 spec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) speed_id = DEV_PORT_SPEED(raw_port_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) ext_stat |= speed_id; /* bits 3:0, RX speed id */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) ext_stat |= speed_id << 4; /* bits 7:4, TX speed id */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) ext_stat |= PORT_RX_LANES(port_li) << 8; /* bits 11:8 Rx lane count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) ext_stat |= PORT_TX_LANES(port_li) << 12; /* bits 15:12 Tx lane count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) return ext_stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) static void xhci_get_usb3_port_status(struct xhci_port *port, u32 *status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) u32 portsc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) struct xhci_bus_state *bus_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) struct xhci_hcd *xhci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) struct usb_hcd *hcd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) u32 link_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) u32 portnum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) bus_state = &port->rhub->bus_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) xhci = hcd_to_xhci(port->rhub->hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) hcd = port->rhub->hcd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) link_state = portsc & PORT_PLS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) portnum = port->hcd_portnum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) /* USB3 specific wPortChange bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) * Port link change with port in resume state should not be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) * reported to usbcore, as this is an internal state to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) * handled by xhci driver. Reporting PLC to usbcore may
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) * cause usbcore clearing PLC first and port change event
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) * irq won't be generated.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) if (portsc & PORT_PLC && (link_state != XDEV_RESUME))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) *status |= USB_PORT_STAT_C_LINK_STATE << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) if (portsc & PORT_WRC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) *status |= USB_PORT_STAT_C_BH_RESET << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) if (portsc & PORT_CEC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) *status |= USB_PORT_STAT_C_CONFIG_ERROR << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) /* USB3 specific wPortStatus bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) if (portsc & PORT_POWER) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) *status |= USB_SS_PORT_STAT_POWER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) /* link state handling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) if (link_state == XDEV_U0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) bus_state->suspended_ports &= ~(1 << portnum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) /* remote wake resume signaling complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) if (bus_state->port_remote_wakeup & (1 << portnum) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) link_state != XDEV_RESUME &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) link_state != XDEV_RECOVERY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) bus_state->port_remote_wakeup &= ~(1 << portnum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) usb_hcd_end_port_resume(&hcd->self, portnum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) xhci_hub_report_usb3_link_state(xhci, status, portsc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) xhci_del_comp_mod_timer(xhci, portsc, portnum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) static void xhci_get_usb2_port_status(struct xhci_port *port, u32 *status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) u32 portsc, unsigned long *flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) struct xhci_bus_state *bus_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) u32 link_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) u32 portnum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) bus_state = &port->rhub->bus_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) link_state = portsc & PORT_PLS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) portnum = port->hcd_portnum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) /* USB2 wPortStatus bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) if (portsc & PORT_POWER) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) *status |= USB_PORT_STAT_POWER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) /* link state is only valid if port is powered */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) if (link_state == XDEV_U3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) *status |= USB_PORT_STAT_SUSPEND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) if (link_state == XDEV_U2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) *status |= USB_PORT_STAT_L1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) if (link_state == XDEV_U0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) if (bus_state->resume_done[portnum])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) usb_hcd_end_port_resume(&port->rhub->hcd->self,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) portnum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) bus_state->resume_done[portnum] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) clear_bit(portnum, &bus_state->resuming_ports);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) if (bus_state->suspended_ports & (1 << portnum)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) bus_state->suspended_ports &= ~(1 << portnum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) bus_state->port_c_suspend |= 1 << portnum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) if (link_state == XDEV_RESUME) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) ret = xhci_handle_usb2_port_link_resume(port, status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) portsc, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) * Converts a raw xHCI port status into the format that external USB 2.0 or USB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) * 3.0 hubs use.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) * Possible side effects:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) * - Mark a port as being done with device resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) * and ring the endpoint doorbells.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) * - Stop the Synopsys redriver Compliance Mode polling.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) * - Drop and reacquire the xHCI lock, in order to wait for port resume.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) static u32 xhci_get_port_status(struct usb_hcd *hcd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) struct xhci_bus_state *bus_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) u16 wIndex, u32 raw_port_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) unsigned long *flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) __releases(&xhci->lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) __acquires(&xhci->lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) u32 status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) struct xhci_hub *rhub;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) struct xhci_port *port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) rhub = xhci_get_rhub(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) port = rhub->ports[wIndex];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) /* common wPortChange bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) if (raw_port_status & PORT_CSC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) status |= USB_PORT_STAT_C_CONNECTION << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) if (raw_port_status & PORT_PEC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) status |= USB_PORT_STAT_C_ENABLE << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) if ((raw_port_status & PORT_OCC))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) status |= USB_PORT_STAT_C_OVERCURRENT << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) if ((raw_port_status & PORT_RC))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) status |= USB_PORT_STAT_C_RESET << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) /* common wPortStatus bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) if (raw_port_status & PORT_CONNECT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) status |= USB_PORT_STAT_CONNECTION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) status |= xhci_port_speed(raw_port_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) if (raw_port_status & PORT_PE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) status |= USB_PORT_STAT_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) if (raw_port_status & PORT_OC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) status |= USB_PORT_STAT_OVERCURRENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) if (raw_port_status & PORT_RESET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) status |= USB_PORT_STAT_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) /* USB2 and USB3 specific bits, including Port Link State */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) if (hcd->speed >= HCD_USB3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) xhci_get_usb3_port_status(port, &status, raw_port_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) xhci_get_usb2_port_status(port, &status, raw_port_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) * Clear stale usb2 resume signalling variables in case port changed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) * state during resume signalling. For example on error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) if ((bus_state->resume_done[wIndex] ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) test_bit(wIndex, &bus_state->resuming_ports)) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) (raw_port_status & PORT_PLS_MASK) != XDEV_U3 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) (raw_port_status & PORT_PLS_MASK) != XDEV_RESUME) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) bus_state->resume_done[wIndex] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) clear_bit(wIndex, &bus_state->resuming_ports);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) usb_hcd_end_port_resume(&hcd->self, wIndex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) if (bus_state->port_c_suspend & (1 << wIndex))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) status |= USB_PORT_STAT_C_SUSPEND << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) u16 wIndex, char *buf, u16 wLength)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) struct xhci_hcd *xhci = hcd_to_xhci(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) int max_ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) u32 temp, status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) int retval = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) int slot_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) struct xhci_bus_state *bus_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) u16 link_state = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) u16 wake_mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) u16 timeout = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) u16 test_mode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) struct xhci_hub *rhub;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) struct xhci_port **ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) rhub = xhci_get_rhub(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) ports = rhub->ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) max_ports = rhub->num_ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) bus_state = &rhub->bus_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) spin_lock_irqsave(&xhci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) switch (typeReq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) case GetHubStatus:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) /* No power source, over-current reported per port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) memset(buf, 0, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) case GetHubDescriptor:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) /* Check to make sure userspace is asking for the USB 3.0 hub
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) * descriptor for the USB 3.0 roothub. If not, we stall the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) * endpoint, like external hubs do.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) if (hcd->speed >= HCD_USB3 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) (wLength < USB_DT_SS_HUB_SIZE ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) wValue != (USB_DT_SS_HUB << 8))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) xhci_dbg(xhci, "Wrong hub descriptor type for "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) "USB 3.0 roothub.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) xhci_hub_descriptor(hcd, xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) (struct usb_hub_descriptor *) buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) case DeviceRequest | USB_REQ_GET_DESCRIPTOR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) if ((wValue & 0xff00) != (USB_DT_BOS << 8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) if (hcd->speed < HCD_USB3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) retval = xhci_create_usb3_bos_desc(xhci, buf, wLength);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) spin_unlock_irqrestore(&xhci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) case GetPortStatus:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) if (!wIndex || wIndex > max_ports)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) wIndex--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) temp = readl(ports[wIndex]->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) if (temp == ~(u32)0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) xhci_hc_died(xhci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) retval = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) trace_xhci_get_port_status(wIndex, temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) status = xhci_get_port_status(hcd, bus_state, wIndex, temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) &flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) if (status == 0xffffffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) xhci_dbg(xhci, "Get port status %d-%d read: 0x%x, return 0x%x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) hcd->self.busnum, wIndex + 1, temp, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) put_unaligned(cpu_to_le32(status), (__le32 *) buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) /* if USB 3.1 extended port status return additional 4 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) if (wValue == 0x02) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) u32 port_li;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) if (hcd->speed < HCD_USB31 || wLength != 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) xhci_err(xhci, "get ext port status invalid parameter\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) retval = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) port_li = readl(ports[wIndex]->addr + PORTLI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) status = xhci_get_ext_port_status(temp, port_li);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) put_unaligned_le32(status, &buf[4]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) case SetPortFeature:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) if (wValue == USB_PORT_FEAT_LINK_STATE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) link_state = (wIndex & 0xff00) >> 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) if (wValue == USB_PORT_FEAT_REMOTE_WAKE_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) wake_mask = wIndex & 0xff00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) if (wValue == USB_PORT_FEAT_TEST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) test_mode = (wIndex & 0xff00) >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) /* The MSB of wIndex is the U1/U2 timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) timeout = (wIndex & 0xff00) >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) wIndex &= 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) if (!wIndex || wIndex > max_ports)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) wIndex--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) temp = readl(ports[wIndex]->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) if (temp == ~(u32)0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) xhci_hc_died(xhci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) retval = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) temp = xhci_port_state_to_neutral(temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) /* FIXME: What new port features do we need to support? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) switch (wValue) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) case USB_PORT_FEAT_SUSPEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) temp = readl(ports[wIndex]->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) if ((temp & PORT_PLS_MASK) != XDEV_U0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) /* Resume the port to U0 first */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) xhci_set_link_state(xhci, ports[wIndex],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) XDEV_U0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) spin_unlock_irqrestore(&xhci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) msleep(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) spin_lock_irqsave(&xhci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) /* In spec software should not attempt to suspend
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) * a port unless the port reports that it is in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) * enabled (PED = ‘1’,PLS < ‘3’) state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) temp = readl(ports[wIndex]->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) if ((temp & PORT_PE) == 0 || (temp & PORT_RESET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) || (temp & PORT_PLS_MASK) >= XDEV_U3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) xhci_warn(xhci, "USB core suspending port %d-%d not in U0/U1/U2\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) hcd->self.busnum, wIndex + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) slot_id = xhci_find_slot_id_by_port(hcd, xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) wIndex + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) if (!slot_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) xhci_warn(xhci, "slot_id is zero\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) /* unlock to execute stop endpoint commands */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) spin_unlock_irqrestore(&xhci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) xhci_stop_device(xhci, slot_id, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) spin_lock_irqsave(&xhci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) xhci_set_link_state(xhci, ports[wIndex], XDEV_U3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) spin_unlock_irqrestore(&xhci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) msleep(10); /* wait device to enter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) spin_lock_irqsave(&xhci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) temp = readl(ports[wIndex]->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) bus_state->suspended_ports |= 1 << wIndex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) case USB_PORT_FEAT_LINK_STATE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) temp = readl(ports[wIndex]->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) /* Disable port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) if (link_state == USB_SS_PORT_LS_SS_DISABLED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) xhci_dbg(xhci, "Disable port %d-%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) hcd->self.busnum, wIndex + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) temp = xhci_port_state_to_neutral(temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) * Clear all change bits, so that we get a new
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) * connection event.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) temp |= PORT_CSC | PORT_PEC | PORT_WRC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) PORT_OCC | PORT_RC | PORT_PLC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) PORT_CEC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) writel(temp | PORT_PE, ports[wIndex]->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) temp = readl(ports[wIndex]->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) /* Put link in RxDetect (enable port) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) if (link_state == USB_SS_PORT_LS_RX_DETECT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) xhci_dbg(xhci, "Enable port %d-%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) hcd->self.busnum, wIndex + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) xhci_set_link_state(xhci, ports[wIndex],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) link_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) temp = readl(ports[wIndex]->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) * For xHCI 1.1 according to section 4.19.1.2.4.1 a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) * root hub port's transition to compliance mode upon
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) * detecting LFPS timeout may be controlled by an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) * Compliance Transition Enabled (CTE) flag (not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) * software visible). This flag is set by writing 0xA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) * to PORTSC PLS field which will allow transition to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) * compliance mode the next time LFPS timeout is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) * encountered. A warm reset will clear it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) * The CTE flag is only supported if the HCCPARAMS2 CTC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) * flag is set, otherwise, the compliance substate is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) * automatically entered as on 1.0 and prior.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) if (link_state == USB_SS_PORT_LS_COMP_MOD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) if (!HCC2_CTC(xhci->hcc_params2)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) xhci_dbg(xhci, "CTC flag is 0, port already supports entering compliance mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) if ((temp & PORT_CONNECT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) xhci_warn(xhci, "Can't set compliance mode when port is connected\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) xhci_dbg(xhci, "Enable compliance mode transition for port %d-%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) hcd->self.busnum, wIndex + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) xhci_set_link_state(xhci, ports[wIndex],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) link_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) temp = readl(ports[wIndex]->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) /* Port must be enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) if (!(temp & PORT_PE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) retval = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) /* Can't set port link state above '3' (U3) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) if (link_state > USB_SS_PORT_LS_U3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) xhci_warn(xhci, "Cannot set port %d-%d link state %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) hcd->self.busnum, wIndex + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) link_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) * set link to U0, steps depend on current link state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) * U3: set link to U0 and wait for u3exit completion.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) * U1/U2: no PLC complete event, only set link to U0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) * Resume/Recovery: device initiated U0, only wait for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) * completion
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) if (link_state == USB_SS_PORT_LS_U0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) u32 pls = temp & PORT_PLS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) bool wait_u0 = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) /* already in U0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) if (pls == XDEV_U0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) if (pls == XDEV_U3 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) pls == XDEV_RESUME ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) pls == XDEV_RECOVERY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) wait_u0 = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) reinit_completion(&bus_state->u3exit_done[wIndex]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) if (pls <= XDEV_U3) /* U1, U2, U3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) xhci_set_link_state(xhci, ports[wIndex],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) USB_SS_PORT_LS_U0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) if (!wait_u0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) if (pls > XDEV_U3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) spin_unlock_irqrestore(&xhci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) if (!wait_for_completion_timeout(&bus_state->u3exit_done[wIndex],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) msecs_to_jiffies(100)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) xhci_dbg(xhci, "missing U0 port change event for port %d-%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) hcd->self.busnum, wIndex + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) spin_lock_irqsave(&xhci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) temp = readl(ports[wIndex]->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) if (link_state == USB_SS_PORT_LS_U3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) int retries = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) slot_id = xhci_find_slot_id_by_port(hcd, xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) wIndex + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) if (slot_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) /* unlock to execute stop endpoint
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) * commands */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) spin_unlock_irqrestore(&xhci->lock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) xhci_stop_device(xhci, slot_id, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) spin_lock_irqsave(&xhci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) xhci_set_link_state(xhci, ports[wIndex], USB_SS_PORT_LS_U3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) spin_unlock_irqrestore(&xhci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) while (retries--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) usleep_range(4000, 8000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) temp = readl(ports[wIndex]->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) if ((temp & PORT_PLS_MASK) == XDEV_U3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) spin_lock_irqsave(&xhci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) temp = readl(ports[wIndex]->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) bus_state->suspended_ports |= 1 << wIndex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) case USB_PORT_FEAT_POWER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) * Turn on ports, even if there isn't per-port switching.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) * HC will report connect events even before this is set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) * However, hub_wq will ignore the roothub events until
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) * the roothub is registered.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) xhci_set_port_power(xhci, hcd, wIndex, true, &flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) case USB_PORT_FEAT_RESET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) temp = (temp | PORT_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) writel(temp, ports[wIndex]->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) temp = readl(ports[wIndex]->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) xhci_dbg(xhci, "set port reset, actual port %d-%d status = 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) hcd->self.busnum, wIndex + 1, temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) case USB_PORT_FEAT_REMOTE_WAKE_MASK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) xhci_set_remote_wake_mask(xhci, ports[wIndex],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) wake_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) temp = readl(ports[wIndex]->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) xhci_dbg(xhci, "set port remote wake mask, actual port %d-%d status = 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) hcd->self.busnum, wIndex + 1, temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) case USB_PORT_FEAT_BH_PORT_RESET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) temp |= PORT_WR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) writel(temp, ports[wIndex]->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) temp = readl(ports[wIndex]->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) case USB_PORT_FEAT_U1_TIMEOUT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) if (hcd->speed < HCD_USB3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) temp = readl(ports[wIndex]->addr + PORTPMSC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) temp &= ~PORT_U1_TIMEOUT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) temp |= PORT_U1_TIMEOUT(timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) writel(temp, ports[wIndex]->addr + PORTPMSC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) case USB_PORT_FEAT_U2_TIMEOUT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) if (hcd->speed < HCD_USB3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) temp = readl(ports[wIndex]->addr + PORTPMSC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) temp &= ~PORT_U2_TIMEOUT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) temp |= PORT_U2_TIMEOUT(timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) writel(temp, ports[wIndex]->addr + PORTPMSC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) case USB_PORT_FEAT_TEST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) /* 4.19.6 Port Test Modes (USB2 Test Mode) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) if (hcd->speed != HCD_USB2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) if (test_mode > USB_TEST_FORCE_ENABLE ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) test_mode < USB_TEST_J)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) retval = xhci_enter_test_mode(xhci, test_mode, wIndex,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) &flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) /* unblock any posted writes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) temp = readl(ports[wIndex]->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) case ClearPortFeature:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) if (!wIndex || wIndex > max_ports)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) wIndex--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) temp = readl(ports[wIndex]->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) if (temp == ~(u32)0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) xhci_hc_died(xhci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) retval = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) /* FIXME: What new port features do we need to support? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) temp = xhci_port_state_to_neutral(temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) switch (wValue) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) case USB_PORT_FEAT_SUSPEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) temp = readl(ports[wIndex]->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) xhci_dbg(xhci, "clear USB_PORT_FEAT_SUSPEND\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) xhci_dbg(xhci, "PORTSC %04x\n", temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) if (temp & PORT_RESET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) if ((temp & PORT_PLS_MASK) == XDEV_U3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) if ((temp & PORT_PE) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) set_bit(wIndex, &bus_state->resuming_ports);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) usb_hcd_start_port_resume(&hcd->self, wIndex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) xhci_set_link_state(xhci, ports[wIndex],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) XDEV_RESUME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) spin_unlock_irqrestore(&xhci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) msleep(USB_RESUME_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) spin_lock_irqsave(&xhci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) xhci_set_link_state(xhci, ports[wIndex],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) XDEV_U0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) clear_bit(wIndex, &bus_state->resuming_ports);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) usb_hcd_end_port_resume(&hcd->self, wIndex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) bus_state->port_c_suspend |= 1 << wIndex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) slot_id = xhci_find_slot_id_by_port(hcd, xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) wIndex + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) if (!slot_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) xhci_dbg(xhci, "slot_id is zero\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) xhci_ring_device(xhci, slot_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) case USB_PORT_FEAT_C_SUSPEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) bus_state->port_c_suspend &= ~(1 << wIndex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) case USB_PORT_FEAT_C_RESET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) case USB_PORT_FEAT_C_BH_PORT_RESET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) case USB_PORT_FEAT_C_CONNECTION:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) case USB_PORT_FEAT_C_OVER_CURRENT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) case USB_PORT_FEAT_C_ENABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) case USB_PORT_FEAT_C_PORT_LINK_STATE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) case USB_PORT_FEAT_C_PORT_CONFIG_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) xhci_clear_port_change_bit(xhci, wValue, wIndex,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) ports[wIndex]->addr, temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) case USB_PORT_FEAT_ENABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) xhci_disable_port(hcd, xhci, wIndex,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) ports[wIndex]->addr, temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) case USB_PORT_FEAT_POWER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) xhci_set_port_power(xhci, hcd, wIndex, false, &flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) case USB_PORT_FEAT_TEST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) retval = xhci_exit_test_mode(xhci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) /* "stall" on error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) retval = -EPIPE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) spin_unlock_irqrestore(&xhci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) * Returns 0 if the status hasn't changed, or the number of bytes in buf.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) * Ports are 0-indexed from the HCD point of view,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) * and 1-indexed from the USB core pointer of view.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) * Note that the status change bits will be cleared as soon as a port status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) * change event is generated, so we use the saved status from that event.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) int xhci_hub_status_data(struct usb_hcd *hcd, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) u32 temp, status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) int i, retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) struct xhci_hcd *xhci = hcd_to_xhci(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) int max_ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) struct xhci_bus_state *bus_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) bool reset_change = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) struct xhci_hub *rhub;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) struct xhci_port **ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) rhub = xhci_get_rhub(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) ports = rhub->ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) max_ports = rhub->num_ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) bus_state = &rhub->bus_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) /* Initial status is no changes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) retval = (max_ports + 8) / 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) memset(buf, 0, retval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) * Inform the usbcore about resume-in-progress by returning
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) * a non-zero value even if there are no status changes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) spin_lock_irqsave(&xhci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) status = bus_state->resuming_ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) mask = PORT_CSC | PORT_PEC | PORT_OCC | PORT_PLC | PORT_WRC | PORT_CEC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) /* For each port, did anything change? If so, set that bit in buf. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) for (i = 0; i < max_ports; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) temp = readl(ports[i]->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) if (temp == ~(u32)0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) xhci_hc_died(xhci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) retval = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) trace_xhci_hub_status_data(i, temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) if ((temp & mask) != 0 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) (bus_state->port_c_suspend & 1 << i) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) (bus_state->resume_done[i] && time_after_eq(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) jiffies, bus_state->resume_done[i]))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) buf[(i + 1) / 8] |= 1 << (i + 1) % 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) status = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) if ((temp & PORT_RC))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) reset_change = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) if (temp & PORT_OC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) status = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) if (!status && !reset_change) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) xhci_dbg(xhci, "%s: stopping usb%d port polling\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) __func__, hcd->self.busnum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) spin_unlock_irqrestore(&xhci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) return status ? retval : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) int xhci_bus_suspend(struct usb_hcd *hcd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) struct xhci_hcd *xhci = hcd_to_xhci(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) int max_ports, port_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) struct xhci_bus_state *bus_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) struct xhci_hub *rhub;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) struct xhci_port **ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) u32 portsc_buf[USB_MAXCHILDREN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) bool wake_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) rhub = xhci_get_rhub(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) ports = rhub->ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) max_ports = rhub->num_ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) bus_state = &rhub->bus_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) wake_enabled = hcd->self.root_hub->do_remote_wakeup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) spin_lock_irqsave(&xhci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) if (wake_enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) if (bus_state->resuming_ports || /* USB2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) bus_state->port_remote_wakeup) { /* USB3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) spin_unlock_irqrestore(&xhci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) xhci_dbg(xhci, "usb%d bus suspend to fail because a port is resuming\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) hcd->self.busnum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) * Prepare ports for suspend, but don't write anything before all ports
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) * are checked and we know bus suspend can proceed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) bus_state->bus_suspended = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) port_index = max_ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) while (port_index--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) u32 t1, t2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) int retries = 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) retry:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) t1 = readl(ports[port_index]->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) t2 = xhci_port_state_to_neutral(t1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) portsc_buf[port_index] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) * Give a USB3 port in link training time to finish, but don't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) * prevent suspend as port might be stuck
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) if ((hcd->speed >= HCD_USB3) && retries-- &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) (t1 & PORT_PLS_MASK) == XDEV_POLLING) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) spin_unlock_irqrestore(&xhci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) msleep(XHCI_PORT_POLLING_LFPS_TIME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) spin_lock_irqsave(&xhci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) xhci_dbg(xhci, "port %d-%d polling in bus suspend, waiting\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) hcd->self.busnum, port_index + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) goto retry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) /* bail out if port detected a over-current condition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) if (t1 & PORT_OC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) bus_state->bus_suspended = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) spin_unlock_irqrestore(&xhci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) xhci_dbg(xhci, "Bus suspend bailout, port over-current detected\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) /* suspend ports in U0, or bail out for new connect changes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) if ((t1 & PORT_PE) && (t1 & PORT_PLS_MASK) == XDEV_U0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) if ((t1 & PORT_CSC) && wake_enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) bus_state->bus_suspended = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) spin_unlock_irqrestore(&xhci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) xhci_dbg(xhci, "Bus suspend bailout, port connect change\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) xhci_dbg(xhci, "port %d-%d not suspended\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) hcd->self.busnum, port_index + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) t2 &= ~PORT_PLS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) t2 |= PORT_LINK_STROBE | XDEV_U3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) set_bit(port_index, &bus_state->bus_suspended);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) } else if ((xhci->quirks & XHCI_U2_BROKEN_SUSPEND) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) (hcd->speed < HCD_USB3) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) (t1 & PORT_PLS_MASK) == XDEV_U3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) * Rockchip SNPS xHC 3.0 set USB 2.0 PHY enter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) * suspend mode from DWC3 core if the suspend
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) * conditions are valid. In this case, it need
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) * to set the bus_suspended bit for USB 2.0, so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) * that in xhci_bus_resume, it can set the xHC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) * link state to XDEV_RESUME and send USB resume
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) * signal to USB 2.0 device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) set_bit(port_index, &bus_state->bus_suspended);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) /* USB core sets remote wake mask for USB 3.0 hubs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) * including the USB 3.0 roothub, but only if CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) * is enabled, so also enable remote wake here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) if (wake_enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) if (t1 & PORT_CONNECT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) t2 |= PORT_WKOC_E | PORT_WKDISC_E;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) t2 &= ~PORT_WKCONN_E;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) t2 |= PORT_WKOC_E | PORT_WKCONN_E;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) t2 &= ~PORT_WKDISC_E;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) if ((xhci->quirks & XHCI_U2_DISABLE_WAKE) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) (hcd->speed < HCD_USB3)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) if (usb_amd_pt_check_port(hcd->self.controller,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) port_index))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) t2 &= ~PORT_WAKE_BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) t2 &= ~PORT_WAKE_BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) t1 = xhci_port_state_to_neutral(t1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) if (t1 != t2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) portsc_buf[port_index] = t2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) /* write port settings, stopping and suspending ports if needed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) port_index = max_ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) while (port_index--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) if (!portsc_buf[port_index])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) if (test_bit(port_index, &bus_state->bus_suspended)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) int slot_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) slot_id = xhci_find_slot_id_by_port(hcd, xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) port_index + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) if (slot_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) spin_unlock_irqrestore(&xhci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) xhci_stop_device(xhci, slot_id, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) spin_lock_irqsave(&xhci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) writel(portsc_buf[port_index], ports[port_index]->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) hcd->state = HC_STATE_SUSPENDED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) bus_state->next_statechange = jiffies + msecs_to_jiffies(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) spin_unlock_irqrestore(&xhci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) if (bus_state->bus_suspended)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) usleep_range(5000, 10000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) EXPORT_SYMBOL_GPL(xhci_bus_suspend);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) * Workaround for missing Cold Attach Status (CAS) if device re-plugged in S3.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) * warm reset a USB3 device stuck in polling or compliance mode after resume.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) * See Intel 100/c230 series PCH specification update Doc #332692-006 Errata #8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) static bool xhci_port_missing_cas_quirk(struct xhci_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) u32 portsc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) portsc = readl(port->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) /* if any of these are set we are not stuck */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) if (portsc & (PORT_CONNECT | PORT_CAS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) if (((portsc & PORT_PLS_MASK) != XDEV_POLLING) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) ((portsc & PORT_PLS_MASK) != XDEV_COMP_MODE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) /* clear wakeup/change bits, and do a warm port reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) portsc &= ~(PORT_RWC_BITS | PORT_CEC | PORT_WAKE_BITS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) portsc |= PORT_WR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) writel(portsc, port->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) /* flush write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) readl(port->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) int xhci_bus_resume(struct usb_hcd *hcd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) struct xhci_hcd *xhci = hcd_to_xhci(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) struct xhci_bus_state *bus_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) int max_ports, port_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) int slot_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) int sret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) u32 next_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) u32 temp, portsc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) struct xhci_hub *rhub;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) struct xhci_port **ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) rhub = xhci_get_rhub(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) ports = rhub->ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) max_ports = rhub->num_ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) bus_state = &rhub->bus_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) if (time_before(jiffies, bus_state->next_statechange))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) msleep(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) spin_lock_irqsave(&xhci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) if (!HCD_HW_ACCESSIBLE(hcd)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) spin_unlock_irqrestore(&xhci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) return -ESHUTDOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) /* delay the irqs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) temp = readl(&xhci->op_regs->command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) temp &= ~CMD_EIE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) writel(temp, &xhci->op_regs->command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) /* bus specific resume for ports we suspended at bus_suspend */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) if (hcd->speed >= HCD_USB3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) next_state = XDEV_U0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) next_state = XDEV_RESUME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) port_index = max_ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) while (port_index--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) portsc = readl(ports[port_index]->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) /* warm reset CAS limited ports stuck in polling/compliance */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) if ((xhci->quirks & XHCI_MISSING_CAS) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) (hcd->speed >= HCD_USB3) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) xhci_port_missing_cas_quirk(ports[port_index])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) xhci_dbg(xhci, "reset stuck port %d-%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) hcd->self.busnum, port_index + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) clear_bit(port_index, &bus_state->bus_suspended);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) /* resume if we suspended the link, and it is still suspended */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) if (test_bit(port_index, &bus_state->bus_suspended))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) switch (portsc & PORT_PLS_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) case XDEV_U3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) portsc = xhci_port_state_to_neutral(portsc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) portsc &= ~PORT_PLS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) portsc |= PORT_LINK_STROBE | next_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) case XDEV_RESUME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) /* resume already initiated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) /* not in a resumeable state, ignore it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) clear_bit(port_index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) &bus_state->bus_suspended);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) /* disable wake for all ports, write new link state if needed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) portsc &= ~(PORT_RWC_BITS | PORT_CEC | PORT_WAKE_BITS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) writel(portsc, ports[port_index]->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) /* USB2 specific resume signaling delay and U0 link state transition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) if (hcd->speed < HCD_USB3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) if (bus_state->bus_suspended) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) spin_unlock_irqrestore(&xhci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) msleep(USB_RESUME_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) spin_lock_irqsave(&xhci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) for_each_set_bit(port_index, &bus_state->bus_suspended,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) BITS_PER_LONG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) /* Clear PLC to poll it later for U0 transition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) xhci_test_and_clear_bit(xhci, ports[port_index],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) PORT_PLC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) xhci_set_link_state(xhci, ports[port_index], XDEV_U0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) /* poll for U0 link state complete, both USB2 and USB3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) for_each_set_bit(port_index, &bus_state->bus_suspended, BITS_PER_LONG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) sret = xhci_handshake(ports[port_index]->addr, PORT_PLC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) PORT_PLC, 10 * 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) if (sret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) xhci_warn(xhci, "port %d-%d resume PLC timeout\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) hcd->self.busnum, port_index + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) xhci_test_and_clear_bit(xhci, ports[port_index], PORT_PLC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) slot_id = xhci_find_slot_id_by_port(hcd, xhci, port_index + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) if (slot_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) xhci_ring_device(xhci, slot_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) (void) readl(&xhci->op_regs->command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) bus_state->next_statechange = jiffies + msecs_to_jiffies(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) /* re-enable irqs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) temp = readl(&xhci->op_regs->command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) temp |= CMD_EIE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) writel(temp, &xhci->op_regs->command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) temp = readl(&xhci->op_regs->command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) spin_unlock_irqrestore(&xhci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) EXPORT_SYMBOL_GPL(xhci_bus_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) unsigned long xhci_get_resuming_ports(struct usb_hcd *hcd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) struct xhci_hub *rhub = xhci_get_rhub(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) /* USB3 port wakeups are reported via usb_wakeup_notification() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) return rhub->bus_state.resuming_ports; /* USB2 ports only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) #endif /* CONFIG_PM */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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