^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * xHCI host controller driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2008 Intel Corp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author: Sarah Sharp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Some code borrowed from the Linux EHCI driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) /* HC should halt within 16 ms, but use 32 ms as some hosts take longer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define XHCI_MAX_HALT_USEC (32 * 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) /* HC not running - set to 1 when run/stop bit is cleared. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define XHCI_STS_HALT (1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) /* HCCPARAMS offset from PCI base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define XHCI_HCC_PARAMS_OFFSET 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) /* HCCPARAMS contains the first extended capability pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define XHCI_HCC_EXT_CAPS(p) (((p)>>16)&0xffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /* Command and Status registers offset from the Operational Registers address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define XHCI_CMD_OFFSET 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define XHCI_STS_OFFSET 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define XHCI_MAX_EXT_CAPS 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /* Capability Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /* bits 7:0 - how long is the Capabilities register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define XHCI_HC_LENGTH(p) (((p)>>00)&0x00ff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /* Extended capability register fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define XHCI_EXT_CAPS_ID(p) (((p)>>0)&0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define XHCI_EXT_CAPS_NEXT(p) (((p)>>8)&0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define XHCI_EXT_CAPS_VAL(p) ((p)>>16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /* Extended capability IDs - ID 0 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define XHCI_EXT_CAPS_LEGACY 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define XHCI_EXT_CAPS_PROTOCOL 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define XHCI_EXT_CAPS_PM 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define XHCI_EXT_CAPS_VIRT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define XHCI_EXT_CAPS_ROUTE 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /* IDs 6-9 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define XHCI_EXT_CAPS_DEBUG 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* Vendor caps */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define XHCI_EXT_CAPS_VENDOR_INTEL 192
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /* USB Legacy Support Capability - section 7.1.1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define XHCI_HC_BIOS_OWNED (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define XHCI_HC_OS_OWNED (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /* USB Legacy Support Capability - section 7.1.1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* Add this offset, plus the value of xECP in HCCPARAMS to the base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define XHCI_LEGACY_SUPPORT_OFFSET (0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /* USB Legacy Support Control and Status Register - section 7.1.2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* Add this offset, plus the value of xECP in HCCPARAMS to the base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define XHCI_LEGACY_CONTROL_OFFSET (0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /* bits 1:3, 5:12, and 17:19 need to be preserved; bits 21:28 should be zero */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define XHCI_LEGACY_DISABLE_SMI ((0x7 << 1) + (0xff << 5) + (0x7 << 17))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define XHCI_LEGACY_SMI_EVENTS (0x7 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /* USB 2.0 xHCI 0.96 L1C capability - section 7.2.2.1.3.2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define XHCI_L1C (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /* USB 2.0 xHCI 1.0 hardware LMP capability - section 7.2.2.1.3.2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define XHCI_HLC (1 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define XHCI_BLC (1 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /* command register values to disable interrupts and halt the HC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /* start/stop HC execution - do not write unless HC is halted*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define XHCI_CMD_RUN (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /* Event Interrupt Enable - get irq when EINT bit is set in USBSTS register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define XHCI_CMD_EIE (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* Host System Error Interrupt Enable - get irq when HSEIE bit set in USBSTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define XHCI_CMD_HSEIE (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* Enable Wrap Event - '1' means xHC generates an event when MFINDEX wraps. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define XHCI_CMD_EWE (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define XHCI_IRQS (XHCI_CMD_EIE | XHCI_CMD_HSEIE | XHCI_CMD_EWE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /* true: Controller Not Ready to accept doorbell or op reg writes after reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define XHCI_STS_CNR (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * Find the offset of the extended capabilities with capability ID id.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * @base PCI MMIO registers base address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * @start address at which to start looking, (0 or HCC_PARAMS to start at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * beginning of list)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * @id Extended capability ID to search for, or 0 for the next
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * capability
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * Returns the offset of the next matching extended capability structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * Some capabilities can occur several times, e.g., the XHCI_EXT_CAPS_PROTOCOL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * and this provides a way to find them all.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) static inline int xhci_find_next_ext_cap(void __iomem *base, u32 start, int id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) u32 next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) u32 offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) offset = start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) if (!start || start == XHCI_HCC_PARAMS_OFFSET) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) val = readl(base + XHCI_HCC_PARAMS_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) if (val == ~0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) offset = XHCI_HCC_EXT_CAPS(val) << 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) if (!offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) val = readl(base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) if (val == ~0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) if (offset != start && (id == 0 || XHCI_EXT_CAPS_ID(val) == id))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) return offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) next = XHCI_EXT_CAPS_NEXT(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) offset += next << 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) } while (next);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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