Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * xhci-dbgcap.h - xHCI debug capability support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2017 Intel Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Author: Lu Baolu <baolu.lu@linux.intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #ifndef __LINUX_XHCI_DBGCAP_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #define __LINUX_XHCI_DBGCAP_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/tty.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/kfifo.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) struct dbc_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 	__le32	capability;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 	__le32	doorbell;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 	__le32	ersts;		/* Event Ring Segment Table Size*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 	__le32	__reserved_0;	/* 0c~0f reserved bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 	__le64	erstba;		/* Event Ring Segment Table Base Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 	__le64	erdp;		/* Event Ring Dequeue Pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 	__le32	control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 	__le32	status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 	__le32	portsc;		/* Port status and control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 	__le32	__reserved_1;	/* 2b~28 reserved bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	__le64	dccp;		/* Debug Capability Context Pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	__le32	devinfo1;	/* Device Descriptor Info Register 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	__le32	devinfo2;	/* Device Descriptor Info Register 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) struct dbc_info_context {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	__le64	string0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	__le64	manufacturer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	__le64	product;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	__le64	serial;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	__le32	length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	__le32	__reserved_0[7];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define DBC_CTRL_DBC_RUN		BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define DBC_CTRL_PORT_ENABLE		BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define DBC_CTRL_HALT_OUT_TR		BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define DBC_CTRL_HALT_IN_TR		BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define DBC_CTRL_DBC_RUN_CHANGE		BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define DBC_CTRL_DBC_ENABLE		BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define DBC_CTRL_MAXBURST(p)		(((p) >> 16) & 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define DBC_DOOR_BELL_TARGET(p)		(((p) & 0xff) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define DBC_MAX_PACKET			1024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define DBC_MAX_STRING_LENGTH		64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define DBC_STRING_MANUFACTURER		"Linux Foundation"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define DBC_STRING_PRODUCT		"Linux USB Debug Target"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define DBC_STRING_SERIAL		"0001"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define	DBC_CONTEXT_SIZE		64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57)  * Port status:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define DBC_PORTSC_CONN_STATUS		BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define DBC_PORTSC_PORT_ENABLED		BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define DBC_PORTSC_CONN_CHANGE		BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define DBC_PORTSC_RESET_CHANGE		BIT(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define DBC_PORTSC_LINK_CHANGE		BIT(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define DBC_PORTSC_CONFIG_CHANGE	BIT(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) struct dbc_str_descs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	char	string0[DBC_MAX_STRING_LENGTH];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	char	manufacturer[DBC_MAX_STRING_LENGTH];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	char	product[DBC_MAX_STRING_LENGTH];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	char	serial[DBC_MAX_STRING_LENGTH];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define DBC_PROTOCOL			1	/* GNU Remote Debug Command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define DBC_VENDOR_ID			0x1d6b	/* Linux Foundation 0x1d6b */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define DBC_PRODUCT_ID			0x0010	/* device 0010 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define DBC_DEVICE_REV			0x0010	/* 0.10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) enum dbc_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	DS_DISABLED = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	DS_INITIALIZED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	DS_ENABLED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	DS_CONNECTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	DS_CONFIGURED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	DS_STALLED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) struct dbc_ep {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	struct xhci_dbc			*dbc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	struct list_head		list_pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	struct xhci_ring		*ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	unsigned int			direction:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define DBC_QUEUE_SIZE			16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define DBC_WRITE_BUF_SIZE		8192
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98)  * Private structure for DbC hardware state:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) struct dbc_port {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	struct tty_port			port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	spinlock_t			port_lock;	/* port access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	struct list_head		read_pool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	struct list_head		read_queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	unsigned int			n_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	struct tasklet_struct		push;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	struct list_head		write_pool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	struct kfifo			write_fifo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	bool				registered;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) struct dbc_driver {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	int (*configure)(struct xhci_dbc *dbc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	void (*disconnect)(struct xhci_dbc *dbc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) struct xhci_dbc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	spinlock_t			lock;		/* device access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	struct device			*dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	struct xhci_hcd			*xhci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	struct dbc_regs __iomem		*regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	struct xhci_ring		*ring_evt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	struct xhci_ring		*ring_in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	struct xhci_ring		*ring_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	struct xhci_erst		erst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	struct xhci_container_ctx	*ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	struct dbc_str_descs		*string;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	dma_addr_t			string_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	size_t				string_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	enum dbc_state			state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	struct delayed_work		event_work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	unsigned			resume_required:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	struct dbc_ep			eps[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	const struct dbc_driver		*driver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	void				*priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct dbc_request {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	void				*buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	unsigned int			length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	dma_addr_t			dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	void				(*complete)(struct xhci_dbc *dbc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 						    struct dbc_request *req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	struct list_head		list_pool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	int				status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	unsigned int			actual;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	struct xhci_dbc			*dbc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	struct list_head		list_pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	dma_addr_t			trb_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	union xhci_trb			*trb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	unsigned			direction:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define dbc_bulkout_ctx(d)		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	((struct xhci_ep_ctx *)((d)->ctx->bytes + DBC_CONTEXT_SIZE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define dbc_bulkin_ctx(d)		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	((struct xhci_ep_ctx *)((d)->ctx->bytes + DBC_CONTEXT_SIZE * 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define dbc_bulkout_enq(d)		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	xhci_trb_virt_to_dma((d)->ring_out->enq_seg, (d)->ring_out->enqueue)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define dbc_bulkin_enq(d)		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	xhci_trb_virt_to_dma((d)->ring_in->enq_seg, (d)->ring_in->enqueue)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define dbc_epctx_info2(t, p, b)	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	cpu_to_le32(EP_TYPE(t) | MAX_PACKET(p) | MAX_BURST(b))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define dbc_ep_dma_direction(d)		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	((d)->direction ? DMA_FROM_DEVICE : DMA_TO_DEVICE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define BULK_OUT			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define BULK_IN				1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define EPID_OUT			2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define EPID_IN				3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) enum evtreturn {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	EVT_ERR	= -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	EVT_DONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	EVT_GSER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	EVT_DISC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static inline struct dbc_ep *get_in_ep(struct xhci_dbc *dbc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	return &dbc->eps[BULK_IN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) static inline struct dbc_ep *get_out_ep(struct xhci_dbc *dbc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	return &dbc->eps[BULK_OUT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #ifdef CONFIG_USB_XHCI_DBGCAP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) int xhci_dbc_init(struct xhci_hcd *xhci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) void xhci_dbc_exit(struct xhci_hcd *xhci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) int xhci_dbc_tty_probe(struct xhci_hcd *xhci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) void xhci_dbc_tty_remove(struct xhci_dbc *dbc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) struct dbc_request *dbc_alloc_request(struct xhci_dbc *dbc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 				      unsigned int direction,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 				      gfp_t flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) void dbc_free_request(struct dbc_request *req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) int dbc_ep_queue(struct dbc_request *req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) int xhci_dbc_suspend(struct xhci_hcd *xhci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) int xhci_dbc_resume(struct xhci_hcd *xhci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #endif /* CONFIG_PM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) static inline int xhci_dbc_init(struct xhci_hcd *xhci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) static inline void xhci_dbc_exit(struct xhci_hcd *xhci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) static inline int xhci_dbc_suspend(struct xhci_hcd *xhci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) static inline int xhci_dbc_resume(struct xhci_hcd *xhci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #endif /* CONFIG_USB_XHCI_DBGCAP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #endif /* __LINUX_XHCI_DBGCAP_H */