^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * UHCI HCD (Host Controller Driver) PCI Bus Glue.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Extracted from uhci-hcd.c:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Maintainer: Alan Stern <stern@rowland.harvard.edu>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * (C) Copyright 1999 Linus Torvalds
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * (C) Copyright 1999-2002 Johannes Erdfelt, johannes@erdfelt.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * (C) Copyright 1999 Randy Dunlap
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * (C) Copyright 1999 Georg Acher, acher@in.tum.de
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * (C) Copyright 1999 Deti Fliegl, deti@fliegl.de
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * (C) Copyright 1999 Thomas Sailer, sailer@ife.ee.ethz.ch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * (C) Copyright 1999 Roman Weissgaerber, weissg@vienna.at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * (C) Copyright 2000 Yggdrasil Computing, Inc. (port of new PCI interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * support from usb-ohci.c by Adam Richter, adam@yggdrasil.com).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * (C) Copyright 1999 Gregory P. Smith (from usb-ohci.c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * (C) Copyright 2004-2007 Alan Stern, stern@rowland.harvard.edu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "pci-quirks.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * Make sure the controller is completely inactive, unable to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * generate interrupts or do DMA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) static void uhci_pci_reset_hc(struct uhci_hcd *uhci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) uhci_reset_hc(to_pci_dev(uhci_dev(uhci)), uhci->io_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * Initialize a controller that was newly discovered or has just been
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * resumed. In either case we can't be sure of its previous state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * Returns: 1 if the controller was reset, 0 otherwise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) static int uhci_pci_check_and_reset_hc(struct uhci_hcd *uhci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) return uhci_check_and_reset_hc(to_pci_dev(uhci_dev(uhci)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) uhci->io_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * Store the basic register settings needed by the controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * This function is called at the end of configure_hc in uhci-hcd.c.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) static void uhci_pci_configure_hc(struct uhci_hcd *uhci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) struct pci_dev *pdev = to_pci_dev(uhci_dev(uhci));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /* Enable PIRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) pci_write_config_word(pdev, USBLEGSUP, USBLEGSUP_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /* Disable platform-specific non-PME# wakeup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) if (pdev->vendor == PCI_VENDOR_ID_INTEL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) pci_write_config_byte(pdev, USBRES_INTEL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) static int uhci_pci_resume_detect_interrupts_are_broken(struct uhci_hcd *uhci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) int port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) switch (to_pci_dev(uhci_dev(uhci))->vendor) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) case PCI_VENDOR_ID_GENESYS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /* Genesys Logic's GL880S controllers don't generate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * resume-detect interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) case PCI_VENDOR_ID_INTEL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* Some of Intel's USB controllers have a bug that causes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * resume-detect interrupts if any port has an over-current
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * condition. To make matters worse, some motherboards
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * hardwire unused USB ports' over-current inputs active!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * To prevent problems, we will not enable resume-detect
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * interrupts if any ports are OC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) for (port = 0; port < uhci->rh_numports; ++port) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) if (inw(uhci->io_addr + USBPORTSC1 + port * 2) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) USBPORTSC_OC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) static int uhci_pci_global_suspend_mode_is_broken(struct uhci_hcd *uhci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) int port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) const char *sys_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) static const char bad_Asus_board[] = "A7V8X";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /* One of Asus's motherboards has a bug which causes it to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * wake up immediately from suspend-to-RAM if any of the ports
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * are connected. In such cases we will not set EGSM.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) sys_info = dmi_get_system_info(DMI_BOARD_NAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) if (sys_info && !strcmp(sys_info, bad_Asus_board)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) for (port = 0; port < uhci->rh_numports; ++port) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) if (inw(uhci->io_addr + USBPORTSC1 + port * 2) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) USBPORTSC_CCS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static int uhci_pci_init(struct usb_hcd *hcd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) struct uhci_hcd *uhci = hcd_to_uhci(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) uhci->io_addr = (unsigned long) hcd->rsrc_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) uhci->rh_numports = uhci_count_ports(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) /* Intel controllers report the OverCurrent bit active on.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) * VIA controllers report it active off, so we'll adjust the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * bit value. (It's not standardized in the UHCI spec.)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) if (to_pci_dev(uhci_dev(uhci))->vendor == PCI_VENDOR_ID_VIA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) uhci->oc_low = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /* HP's server management chip requires a longer port reset delay. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) if (to_pci_dev(uhci_dev(uhci))->vendor == PCI_VENDOR_ID_HP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) uhci->wait_for_hp = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /* Intel controllers use non-PME wakeup signalling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) if (to_pci_dev(uhci_dev(uhci))->vendor == PCI_VENDOR_ID_INTEL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) device_set_wakeup_capable(uhci_dev(uhci), true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /* Set up pointers to PCI-specific functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) uhci->reset_hc = uhci_pci_reset_hc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) uhci->check_and_reset_hc = uhci_pci_check_and_reset_hc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) uhci->configure_hc = uhci_pci_configure_hc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) uhci->resume_detect_interrupts_are_broken =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) uhci_pci_resume_detect_interrupts_are_broken;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) uhci->global_suspend_mode_is_broken =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) uhci_pci_global_suspend_mode_is_broken;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /* Kick BIOS off this hardware and reset if the controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) * isn't already safely quiescent.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) check_and_reset_hc(uhci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) /* Make sure the controller is quiescent and that we're not using it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) * any more. This is mainly for the benefit of programs which, like kexec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) * expect the hardware to be idle: not doing DMA or generating IRQs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) * This routine may be called in a damaged or failing kernel. Hence we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) * do not acquire the spinlock before shutting down the controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static void uhci_shutdown(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) struct usb_hcd *hcd = pci_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) uhci_hc_died(hcd_to_uhci(hcd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static int uhci_pci_resume(struct usb_hcd *hcd, bool hibernated);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static int uhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) struct uhci_hcd *uhci = hcd_to_uhci(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) struct pci_dev *pdev = to_pci_dev(uhci_dev(uhci));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) int rc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) dev_dbg(uhci_dev(uhci), "%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) spin_lock_irq(&uhci->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) if (!HCD_HW_ACCESSIBLE(hcd) || uhci->dead)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) goto done_okay; /* Already suspended or dead */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) /* All PCI host controllers are required to disable IRQ generation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) * at the source, so we must turn off PIRQ.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) pci_write_config_word(pdev, USBLEGSUP, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) /* Enable platform-specific non-PME# wakeup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) if (do_wakeup) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) if (pdev->vendor == PCI_VENDOR_ID_INTEL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) pci_write_config_byte(pdev, USBRES_INTEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) USBPORT1EN | USBPORT2EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) done_okay:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) spin_unlock_irq(&uhci->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) synchronize_irq(hcd->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) /* Check for race with a wakeup request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) if (do_wakeup && HCD_WAKEUP_PENDING(hcd)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) uhci_pci_resume(hcd, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) rc = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) static int uhci_pci_resume(struct usb_hcd *hcd, bool hibernated)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) struct uhci_hcd *uhci = hcd_to_uhci(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) dev_dbg(uhci_dev(uhci), "%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /* Since we aren't in D3 any more, it's safe to set this flag
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) * even if the controller was dead.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) spin_lock_irq(&uhci->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) /* Make sure resume from hibernation re-enumerates everything */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) if (hibernated) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) uhci->reset_hc(uhci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) finish_reset(uhci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) /* The firmware may have changed the controller settings during
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) * a system wakeup. Check it and reconfigure to avoid problems.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) check_and_reset_hc(uhci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) configure_hc(uhci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) /* Tell the core if the controller had to be reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) if (uhci->rh_state == UHCI_RH_RESET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) usb_root_hub_lost_power(hcd->self.root_hub);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) spin_unlock_irq(&uhci->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) /* If interrupts don't work and remote wakeup is enabled then
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) * the suspended root hub needs to be polled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) if (!uhci->RD_enable && hcd->self.root_hub->do_remote_wakeup)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) /* Does the root hub have a port wakeup pending? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) usb_hcd_poll_rh_status(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) static const struct hc_driver uhci_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) .description = hcd_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) .product_desc = "UHCI Host Controller",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) .hcd_priv_size = sizeof(struct uhci_hcd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) /* Generic hardware linkage */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) .irq = uhci_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) .flags = HCD_DMA | HCD_USB11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) /* Basic lifecycle operations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) .reset = uhci_pci_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) .start = uhci_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) .pci_suspend = uhci_pci_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) .pci_resume = uhci_pci_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) .bus_suspend = uhci_rh_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) .bus_resume = uhci_rh_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) .stop = uhci_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) .urb_enqueue = uhci_urb_enqueue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) .urb_dequeue = uhci_urb_dequeue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) .endpoint_disable = uhci_hcd_endpoint_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) .get_frame_number = uhci_hcd_get_frame_number,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) .hub_status_data = uhci_hub_status_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) .hub_control = uhci_hub_control,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) static const struct pci_device_id uhci_pci_ids[] = { {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) /* handle any USB UHCI controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_UHCI, ~0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) }, { /* end: all zeroes */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) MODULE_DEVICE_TABLE(pci, uhci_pci_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) static int uhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) return usb_hcd_pci_probe(dev, id, &uhci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) static struct pci_driver uhci_pci_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) .name = hcd_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) .id_table = uhci_pci_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) .probe = uhci_pci_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) .remove = usb_hcd_pci_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) .shutdown = uhci_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) .pm = &usb_hcd_pci_pm_ops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) MODULE_SOFTDEP("pre: ehci_pci");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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