^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Universal Host Controller Interface driver for USB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Maintainer: Alan Stern <stern@rowland.harvard.edu>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * (C) Copyright 1999 Linus Torvalds
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * (C) Copyright 1999-2002 Johannes Erdfelt, johannes@erdfelt.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * (C) Copyright 1999 Randy Dunlap
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * (C) Copyright 1999 Georg Acher, acher@in.tum.de
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * (C) Copyright 1999 Deti Fliegl, deti@fliegl.de
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * (C) Copyright 1999 Thomas Sailer, sailer@ife.ee.ethz.ch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * (C) Copyright 2004 Alan Stern, stern@rowland.harvard.edu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) static const __u8 root_hub_hub_des[] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 0x09, /* __u8 bLength; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) USB_DT_HUB, /* __u8 bDescriptorType; Hub-descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 0x02, /* __u8 bNbrPorts; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) HUB_CHAR_NO_LPSM | /* __u16 wHubCharacteristics; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) HUB_CHAR_INDV_PORT_OCPM, /* (per-port OC, no power switching) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 0x01, /* __u8 bPwrOn2pwrGood; 2ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 0x00, /* __u8 bHubContrCurrent; 0 mA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 0x00, /* __u8 DeviceRemovable; *** 7 Ports max */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 0xff /* __u8 PortPwrCtrlMask; *** 7 ports max */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define UHCI_RH_MAXCHILD 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /* must write as zeroes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define WZ_BITS (USBPORTSC_RES2 | USBPORTSC_RES3 | USBPORTSC_RES4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /* status change bits: nonzero writes will clear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define RWC_BITS (USBPORTSC_OCC | USBPORTSC_PEC | USBPORTSC_CSC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /* suspend/resume bits: port suspended or port resuming */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define SUSPEND_BITS (USBPORTSC_SUSP | USBPORTSC_RD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /* A port that either is connected or has a changed-bit set will prevent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * us from AUTO_STOPPING.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) static int any_ports_active(struct uhci_hcd *uhci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) int port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) for (port = 0; port < uhci->rh_numports; ++port) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) if ((uhci_readw(uhci, USBPORTSC1 + port * 2) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) (USBPORTSC_CCS | RWC_BITS)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) test_bit(port, &uhci->port_c_suspend))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) static inline int get_hub_status_data(struct uhci_hcd *uhci, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) int port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) int mask = RWC_BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /* Some boards (both VIA and Intel apparently) report bogus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * overcurrent indications, causing massive log spam unless
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * we completely ignore them. This doesn't seem to be a problem
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * with the chipset so much as with the way it is connected on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * the motherboard; if the overcurrent input is left to float
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * then it may constantly register false positives. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) if (ignore_oc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) mask &= ~USBPORTSC_OCC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) *buf = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) for (port = 0; port < uhci->rh_numports; ++port) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) if ((uhci_readw(uhci, USBPORTSC1 + port * 2) & mask) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) test_bit(port, &uhci->port_c_suspend))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) *buf |= (1 << (port + 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) return !!*buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define CLR_RH_PORTSTAT(x) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) status = uhci_readw(uhci, port_addr); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) status &= ~(RWC_BITS|WZ_BITS); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) status &= ~(x); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) status |= RWC_BITS & (x); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) uhci_writew(uhci, status, port_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define SET_RH_PORTSTAT(x) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) status = uhci_readw(uhci, port_addr); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) status |= (x); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) status &= ~(RWC_BITS|WZ_BITS); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) uhci_writew(uhci, status, port_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /* UHCI controllers don't automatically stop resume signalling after 20 msec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * so we have to poll and check timeouts in order to take care of it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) static void uhci_finish_suspend(struct uhci_hcd *uhci, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) unsigned long port_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) if (uhci_readw(uhci, port_addr) & SUSPEND_BITS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) CLR_RH_PORTSTAT(SUSPEND_BITS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) if (test_bit(port, &uhci->resuming_ports))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) set_bit(port, &uhci->port_c_suspend);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /* The controller won't actually turn off the RD bit until
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * it has had a chance to send a low-speed EOP sequence,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) * which is supposed to take 3 bit times (= 2 microseconds).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * Experiments show that some controllers take longer, so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * we'll poll for completion. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) for (i = 0; i < 10; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) if (!(uhci_readw(uhci, port_addr) & SUSPEND_BITS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) clear_bit(port, &uhci->resuming_ports);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) usb_hcd_end_port_resume(&uhci_to_hcd(uhci)->self, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) /* Wait for the UHCI controller in HP's iLO2 server management chip.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) * It can take up to 250 us to finish a reset and set the CSC bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static void wait_for_HP(struct uhci_hcd *uhci, unsigned long port_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) for (i = 10; i < 250; i += 10) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) if (uhci_readw(uhci, port_addr) & USBPORTSC_CSC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /* Log a warning? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static void uhci_check_ports(struct uhci_hcd *uhci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) unsigned int port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) unsigned long port_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) for (port = 0; port < uhci->rh_numports; ++port) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) port_addr = USBPORTSC1 + 2 * port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) status = uhci_readw(uhci, port_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) if (unlikely(status & USBPORTSC_PR)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) if (time_after_eq(jiffies, uhci->ports_timeout)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) CLR_RH_PORTSTAT(USBPORTSC_PR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /* HP's server management chip requires
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) * a longer delay. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) if (uhci->wait_for_hp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) wait_for_HP(uhci, port_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /* If the port was enabled before, turning
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) * reset on caused a port enable change.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) * Turning reset off causes a port connect
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) * status change. Clear these changes. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) CLR_RH_PORTSTAT(USBPORTSC_CSC | USBPORTSC_PEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) SET_RH_PORTSTAT(USBPORTSC_PE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) if (unlikely(status & USBPORTSC_RD)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) if (!test_bit(port, &uhci->resuming_ports)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /* Port received a wakeup request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) set_bit(port, &uhci->resuming_ports);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) uhci->ports_timeout = jiffies +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) msecs_to_jiffies(USB_RESUME_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) usb_hcd_start_port_resume(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) &uhci_to_hcd(uhci)->self, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) /* Make sure we see the port again
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) * after the resuming period is over. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) mod_timer(&uhci_to_hcd(uhci)->rh_timer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) uhci->ports_timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) } else if (time_after_eq(jiffies,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) uhci->ports_timeout)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) uhci_finish_suspend(uhci, port, port_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static int uhci_hub_status_data(struct usb_hcd *hcd, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) struct uhci_hcd *uhci = hcd_to_uhci(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) int status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) spin_lock_irqsave(&uhci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) uhci_scan_schedule(uhci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) if (!HCD_HW_ACCESSIBLE(hcd) || uhci->dead)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) uhci_check_ports(uhci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) status = get_hub_status_data(uhci, buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) switch (uhci->rh_state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) case UHCI_RH_SUSPENDED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) /* if port change, ask to be resumed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) if (status || uhci->resuming_ports) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) status = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) usb_hcd_resume_root_hub(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) case UHCI_RH_AUTO_STOPPED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) /* if port change, auto start */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) if (status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) wakeup_rh(uhci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) case UHCI_RH_RUNNING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /* are any devices attached? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) if (!any_ports_active(uhci)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) uhci->rh_state = UHCI_RH_RUNNING_NODEVS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) uhci->auto_stop_time = jiffies + HZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) case UHCI_RH_RUNNING_NODEVS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) /* auto-stop if nothing connected for 1 second */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) if (any_ports_active(uhci))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) uhci->rh_state = UHCI_RH_RUNNING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) else if (time_after_eq(jiffies, uhci->auto_stop_time) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) !uhci->wait_for_hp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) suspend_rh(uhci, UHCI_RH_AUTO_STOPPED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) spin_unlock_irqrestore(&uhci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) /* size of returned buffer is part of USB spec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) static int uhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) u16 wIndex, char *buf, u16 wLength)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) struct uhci_hcd *uhci = hcd_to_uhci(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) int status, lstatus, retval = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) unsigned int port = wIndex - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) unsigned long port_addr = USBPORTSC1 + 2 * port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) u16 wPortChange, wPortStatus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) if (!HCD_HW_ACCESSIBLE(hcd) || uhci->dead)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) spin_lock_irqsave(&uhci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) switch (typeReq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) case GetHubStatus:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) *(__le32 *)buf = cpu_to_le32(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) retval = 4; /* hub power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) case GetPortStatus:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) if (port >= uhci->rh_numports)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) uhci_check_ports(uhci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) status = uhci_readw(uhci, port_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) /* Intel controllers report the OverCurrent bit active on.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) * VIA controllers report it active off, so we'll adjust the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) * bit value. (It's not standardized in the UHCI spec.)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) if (uhci->oc_low)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) status ^= USBPORTSC_OC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) /* UHCI doesn't support C_RESET (always false) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) wPortChange = lstatus = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) if (status & USBPORTSC_CSC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) wPortChange |= USB_PORT_STAT_C_CONNECTION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) if (status & USBPORTSC_PEC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) wPortChange |= USB_PORT_STAT_C_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) if ((status & USBPORTSC_OCC) && !ignore_oc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) wPortChange |= USB_PORT_STAT_C_OVERCURRENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) if (test_bit(port, &uhci->port_c_suspend)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) wPortChange |= USB_PORT_STAT_C_SUSPEND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) lstatus |= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) if (test_bit(port, &uhci->resuming_ports))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) lstatus |= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) /* UHCI has no power switching (always on) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) wPortStatus = USB_PORT_STAT_POWER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) if (status & USBPORTSC_CCS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) wPortStatus |= USB_PORT_STAT_CONNECTION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) if (status & USBPORTSC_PE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) wPortStatus |= USB_PORT_STAT_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) if (status & SUSPEND_BITS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) wPortStatus |= USB_PORT_STAT_SUSPEND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) if (status & USBPORTSC_OC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) wPortStatus |= USB_PORT_STAT_OVERCURRENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) if (status & USBPORTSC_PR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) wPortStatus |= USB_PORT_STAT_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) if (status & USBPORTSC_LSDA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) wPortStatus |= USB_PORT_STAT_LOW_SPEED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) if (wPortChange)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) dev_dbg(uhci_dev(uhci), "port %d portsc %04x,%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) wIndex, status, lstatus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) *(__le16 *)buf = cpu_to_le16(wPortStatus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) *(__le16 *)(buf + 2) = cpu_to_le16(wPortChange);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) retval = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) case SetHubFeature: /* We don't implement these */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) case ClearHubFeature:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) switch (wValue) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) case C_HUB_OVER_CURRENT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) case C_HUB_LOCAL_POWER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) case SetPortFeature:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) if (port >= uhci->rh_numports)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) switch (wValue) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) case USB_PORT_FEAT_SUSPEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) SET_RH_PORTSTAT(USBPORTSC_SUSP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) case USB_PORT_FEAT_RESET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) SET_RH_PORTSTAT(USBPORTSC_PR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) /* Reset terminates Resume signalling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) uhci_finish_suspend(uhci, port, port_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) /* USB v2.0 7.1.7.5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) uhci->ports_timeout = jiffies +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) msecs_to_jiffies(USB_RESUME_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) case USB_PORT_FEAT_POWER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) /* UHCI has no power switching */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) case ClearPortFeature:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) if (port >= uhci->rh_numports)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) switch (wValue) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) case USB_PORT_FEAT_ENABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) CLR_RH_PORTSTAT(USBPORTSC_PE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) /* Disable terminates Resume signalling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) uhci_finish_suspend(uhci, port, port_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) case USB_PORT_FEAT_C_ENABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) CLR_RH_PORTSTAT(USBPORTSC_PEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) case USB_PORT_FEAT_SUSPEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) if (!(uhci_readw(uhci, port_addr) & USBPORTSC_SUSP)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) /* Make certain the port isn't suspended */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) uhci_finish_suspend(uhci, port, port_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) } else if (!test_and_set_bit(port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) &uhci->resuming_ports)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) SET_RH_PORTSTAT(USBPORTSC_RD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) /* The controller won't allow RD to be set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) * if the port is disabled. When this happens
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) * just skip the Resume signalling.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) if (!(uhci_readw(uhci, port_addr) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) USBPORTSC_RD))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) uhci_finish_suspend(uhci, port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) port_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) /* USB v2.0 7.1.7.7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) uhci->ports_timeout = jiffies +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) msecs_to_jiffies(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) case USB_PORT_FEAT_C_SUSPEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) clear_bit(port, &uhci->port_c_suspend);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) case USB_PORT_FEAT_POWER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) /* UHCI has no power switching */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) case USB_PORT_FEAT_C_CONNECTION:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) CLR_RH_PORTSTAT(USBPORTSC_CSC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) case USB_PORT_FEAT_C_OVER_CURRENT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) CLR_RH_PORTSTAT(USBPORTSC_OCC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) case USB_PORT_FEAT_C_RESET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) /* this driver won't report these */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) case GetHubDescriptor:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) retval = min_t(unsigned int, sizeof(root_hub_hub_des), wLength);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) memcpy(buf, root_hub_hub_des, retval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) if (retval > 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) buf[2] = uhci->rh_numports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) retval = -EPIPE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) spin_unlock_irqrestore(&uhci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags