^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #ifndef __LINUX_UHCI_HCD_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #define __LINUX_UHCI_HCD_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <linux/list.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/usb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define usb_packetid(pipe) (usb_pipein(pipe) ? USB_PID_IN : USB_PID_OUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define PIPE_DEVEP_MASK 0x0007ff00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * Universal Host Controller Interface data structures and defines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) /* Command register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define USBCMD 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define USBCMD_RS 0x0001 /* Run/Stop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define USBCMD_HCRESET 0x0002 /* Host reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define USBCMD_GRESET 0x0004 /* Global reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define USBCMD_EGSM 0x0008 /* Global Suspend Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define USBCMD_FGR 0x0010 /* Force Global Resume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define USBCMD_SWDBG 0x0020 /* SW Debug mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define USBCMD_CF 0x0040 /* Config Flag (sw only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define USBCMD_MAXP 0x0080 /* Max Packet (0 = 32, 1 = 64) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /* Status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define USBSTS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define USBSTS_USBINT 0x0001 /* Interrupt due to IOC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define USBSTS_ERROR 0x0002 /* Interrupt due to error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define USBSTS_RD 0x0004 /* Resume Detect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define USBSTS_HSE 0x0008 /* Host System Error: PCI problems */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define USBSTS_HCPE 0x0010 /* Host Controller Process Error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * the schedule is buggy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define USBSTS_HCH 0x0020 /* HC Halted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /* Interrupt enable register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define USBINTR 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define USBINTR_TIMEOUT 0x0001 /* Timeout/CRC error enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define USBINTR_RESUME 0x0002 /* Resume interrupt enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define USBINTR_IOC 0x0004 /* Interrupt On Complete enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define USBINTR_SP 0x0008 /* Short packet interrupt enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define USBFRNUM 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define USBFLBASEADD 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define USBSOF 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define USBSOF_DEFAULT 64 /* Frame length is exactly 1 ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* USB port status and control registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define USBPORTSC1 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define USBPORTSC2 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define USBPORTSC3 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define USBPORTSC4 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define USBPORTSC_CCS 0x0001 /* Current Connect Status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * ("device present") */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define USBPORTSC_CSC 0x0002 /* Connect Status Change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define USBPORTSC_PE 0x0004 /* Port Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define USBPORTSC_PEC 0x0008 /* Port Enable Change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define USBPORTSC_DPLUS 0x0010 /* D+ high (line status) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define USBPORTSC_DMINUS 0x0020 /* D- high (line status) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define USBPORTSC_RD 0x0040 /* Resume Detect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define USBPORTSC_RES1 0x0080 /* reserved, always 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define USBPORTSC_LSDA 0x0100 /* Low Speed Device Attached */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define USBPORTSC_PR 0x0200 /* Port Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /* OC and OCC from Intel 430TX and later (not UHCI 1.1d spec) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define USBPORTSC_OC 0x0400 /* Over Current condition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define USBPORTSC_OCC 0x0800 /* Over Current Change R/WC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define USBPORTSC_SUSP 0x1000 /* Suspend */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define USBPORTSC_RES2 0x2000 /* reserved, write zeroes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define USBPORTSC_RES3 0x4000 /* reserved, write zeroes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define USBPORTSC_RES4 0x8000 /* reserved, write zeroes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* PCI legacy support register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define USBLEGSUP 0xc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define USBLEGSUP_DEFAULT 0x2000 /* only PIRQ enable set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define USBLEGSUP_RWC 0x8f00 /* the R/WC bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define USBLEGSUP_RO 0x5040 /* R/O and reserved bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /* PCI Intel-specific resume-enable register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define USBRES_INTEL 0xc4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define USBPORT1EN 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define USBPORT2EN 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define UHCI_PTR_BITS(uhci) cpu_to_hc32((uhci), 0x000F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define UHCI_PTR_TERM(uhci) cpu_to_hc32((uhci), 0x0001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define UHCI_PTR_QH(uhci) cpu_to_hc32((uhci), 0x0002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define UHCI_PTR_DEPTH(uhci) cpu_to_hc32((uhci), 0x0004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define UHCI_PTR_BREADTH(uhci) cpu_to_hc32((uhci), 0x0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define UHCI_NUMFRAMES 1024 /* in the frame list [array] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define UHCI_MAX_SOF_NUMBER 2047 /* in an SOF packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define CAN_SCHEDULE_FRAMES 1000 /* how far in the future frames
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * can be scheduled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define MAX_PHASE 32 /* Periodic scheduling length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /* When no queues need Full-Speed Bandwidth Reclamation,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * delay this long before turning FSBR off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define FSBR_OFF_DELAY msecs_to_jiffies(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /* If a queue hasn't advanced after this much time, assume it is stuck */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define QH_WAIT_TIMEOUT msecs_to_jiffies(200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * __hc32 and __hc16 are "Host Controller" types, they may be equivalent to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * __leXX (normally) or __beXX (given UHCI_BIG_ENDIAN_DESC), depending on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * the host controller implementation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * To facilitate the strongest possible byte-order checking from "sparse"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * and so on, we use __leXX unless that's not practical.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #ifdef CONFIG_USB_UHCI_BIG_ENDIAN_DESC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) typedef __u32 __bitwise __hc32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) typedef __u16 __bitwise __hc16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define __hc32 __le32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define __hc16 __le16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) * Queue Headers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * One role of a QH is to hold a queue of TDs for some endpoint. One QH goes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * with each endpoint, and qh->element (updated by the HC) is either:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * - the next unprocessed TD in the endpoint's queue, or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * - UHCI_PTR_TERM (when there's no more traffic for this endpoint).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * The other role of a QH is to serve as a "skeleton" framelist entry, so we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * can easily splice a QH for some endpoint into the schedule at the right
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * place. Then qh->element is UHCI_PTR_TERM.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) * In the schedule, qh->link maintains a list of QHs seen by the HC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * skel1 --> ep1-qh --> ep2-qh --> ... --> skel2 --> ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) * qh->node is the software equivalent of qh->link. The differences
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) * are that the software list is doubly-linked and QHs in the UNLINKING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) * state are on the software list but not the hardware schedule.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) * For bookkeeping purposes we maintain QHs even for Isochronous endpoints,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) * but they never get added to the hardware schedule.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define QH_STATE_IDLE 1 /* QH is not being used */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define QH_STATE_UNLINKING 2 /* QH has been removed from the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) * schedule but the hardware may
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) * still be using it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define QH_STATE_ACTIVE 3 /* QH is on the schedule */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) struct uhci_qh {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /* Hardware fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) __hc32 link; /* Next QH in the schedule */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) __hc32 element; /* Queue element (TD) pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /* Software fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) dma_addr_t dma_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) struct list_head node; /* Node in the list of QHs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) struct usb_host_endpoint *hep; /* Endpoint information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) struct usb_device *udev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) struct list_head queue; /* Queue of urbps for this QH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) struct uhci_td *dummy_td; /* Dummy TD to end the queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) struct uhci_td *post_td; /* Last TD completed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) struct usb_iso_packet_descriptor *iso_packet_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /* Next urb->iso_frame_desc entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) unsigned long advance_jiffies; /* Time of last queue advance */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) unsigned int unlink_frame; /* When the QH was unlinked */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) unsigned int period; /* For Interrupt and Isochronous QHs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) short phase; /* Between 0 and period-1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) short load; /* Periodic time requirement, in us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) unsigned int iso_frame; /* Frame # for iso_packet_desc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) int state; /* QH_STATE_xxx; see above */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) int type; /* Queue type (control, bulk, etc) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) int skel; /* Skeleton queue number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) unsigned int initial_toggle:1; /* Endpoint's current toggle value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) unsigned int needs_fixup:1; /* Must fix the TD toggle values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) unsigned int is_stopped:1; /* Queue was stopped by error/unlink */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) unsigned int wait_expired:1; /* QH_WAIT_TIMEOUT has expired */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) unsigned int bandwidth_reserved:1; /* Periodic bandwidth has
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) * been allocated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) } __attribute__((aligned(16)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) * We need a special accessor for the element pointer because it is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) * subject to asynchronous updates by the controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define qh_element(qh) READ_ONCE((qh)->element)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define LINK_TO_QH(uhci, qh) (UHCI_PTR_QH((uhci)) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) cpu_to_hc32((uhci), (qh)->dma_handle))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) * Transfer Descriptors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) * for TD <status>:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define TD_CTRL_SPD (1 << 29) /* Short Packet Detect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define TD_CTRL_C_ERR_MASK (3 << 27) /* Error Counter bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define TD_CTRL_C_ERR_SHIFT 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define TD_CTRL_LS (1 << 26) /* Low Speed Device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define TD_CTRL_IOS (1 << 25) /* Isochronous Select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define TD_CTRL_IOC (1 << 24) /* Interrupt on Complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define TD_CTRL_ACTIVE (1 << 23) /* TD Active */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define TD_CTRL_STALLED (1 << 22) /* TD Stalled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define TD_CTRL_DBUFERR (1 << 21) /* Data Buffer Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define TD_CTRL_BABBLE (1 << 20) /* Babble Detected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define TD_CTRL_NAK (1 << 19) /* NAK Received */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define TD_CTRL_CRCTIMEO (1 << 18) /* CRC/Time Out Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define TD_CTRL_BITSTUFF (1 << 17) /* Bit Stuff Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define TD_CTRL_ACTLEN_MASK 0x7FF /* actual length, encoded as n - 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define uhci_maxerr(err) ((err) << TD_CTRL_C_ERR_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define uhci_status_bits(ctrl_sts) ((ctrl_sts) & 0xF60000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define uhci_actual_length(ctrl_sts) (((ctrl_sts) + 1) & \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) TD_CTRL_ACTLEN_MASK) /* 1-based */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) * for TD <info>: (a.k.a. Token)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define td_token(uhci, td) hc32_to_cpu((uhci), (td)->token)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define TD_TOKEN_DEVADDR_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define TD_TOKEN_TOGGLE_SHIFT 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define TD_TOKEN_TOGGLE (1 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define TD_TOKEN_EXPLEN_SHIFT 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define TD_TOKEN_EXPLEN_MASK 0x7FF /* expected length, encoded as n-1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define TD_TOKEN_PID_MASK 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define uhci_explen(len) ((((len) - 1) & TD_TOKEN_EXPLEN_MASK) << \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) TD_TOKEN_EXPLEN_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define uhci_expected_length(token) ((((token) >> TD_TOKEN_EXPLEN_SHIFT) + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 1) & TD_TOKEN_EXPLEN_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define uhci_toggle(token) (((token) >> TD_TOKEN_TOGGLE_SHIFT) & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define uhci_endpoint(token) (((token) >> 15) & 0xf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define uhci_devaddr(token) (((token) >> TD_TOKEN_DEVADDR_SHIFT) & 0x7f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define uhci_devep(token) (((token) >> TD_TOKEN_DEVADDR_SHIFT) & 0x7ff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define uhci_packetid(token) ((token) & TD_TOKEN_PID_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define uhci_packetout(token) (uhci_packetid(token) != USB_PID_IN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define uhci_packetin(token) (uhci_packetid(token) == USB_PID_IN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) * The documentation says "4 words for hardware, 4 words for software".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) * That's silly, the hardware doesn't care. The hardware only cares that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) * the hardware words are 16-byte aligned, and we can have any amount of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) * sw space after the TD entry.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) * td->link points to either another TD (not necessarily for the same urb or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) * even the same endpoint), or nothing (PTR_TERM), or a QH.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) struct uhci_td {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) /* Hardware fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) __hc32 link;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) __hc32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) __hc32 token;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) __hc32 buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) /* Software fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) dma_addr_t dma_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) struct list_head list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) int frame; /* for iso: what frame? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) struct list_head fl_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) } __attribute__((aligned(16)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) * We need a special accessor for the control/status word because it is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) * subject to asynchronous updates by the controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define td_status(uhci, td) hc32_to_cpu((uhci), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) READ_ONCE((td)->status))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define LINK_TO_TD(uhci, td) (cpu_to_hc32((uhci), (td)->dma_handle))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) * Skeleton Queue Headers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) * The UHCI driver uses QHs with Interrupt, Control and Bulk URBs for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) * automatic queuing. To make it easy to insert entries into the schedule,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) * we have a skeleton of QHs for each predefined Interrupt latency.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) * Asynchronous QHs (low-speed control, full-speed control, and bulk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) * go onto the period-1 interrupt list, since they all get accessed on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) * every frame.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) * When we want to add a new QH, we add it to the list starting from the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) * appropriate skeleton QH. For instance, the schedule can look like this:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) * skel int128 QH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) * dev 1 interrupt QH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) * dev 5 interrupt QH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) * skel int64 QH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) * skel int32 QH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) * ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) * skel int1 + async QH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) * dev 5 low-speed control QH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) * dev 1 bulk QH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) * dev 2 bulk QH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) * There is a special terminating QH used to keep full-speed bandwidth
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) * reclamation active when no full-speed control or bulk QHs are linked
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) * into the schedule. It has an inactive TD (to work around a PIIX bug,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) * see the Intel errata) and it points back to itself.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) * There's a special skeleton QH for Isochronous QHs which never appears
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) * on the schedule. Isochronous TDs go on the schedule before the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) * the skeleton QHs. The hardware accesses them directly rather than
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) * through their QH, which is used only for bookkeeping purposes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) * While the UHCI spec doesn't forbid the use of QHs for Isochronous,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) * it doesn't use them either. And the spec says that queues never
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) * advance on an error completion status, which makes them totally
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) * unsuitable for Isochronous transfers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) * There's also a special skeleton QH used for QHs which are in the process
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) * of unlinking and so may still be in use by the hardware. It too never
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) * appears on the schedule.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define UHCI_NUM_SKELQH 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define SKEL_UNLINK 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define skel_unlink_qh skelqh[SKEL_UNLINK]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define SKEL_ISO 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define skel_iso_qh skelqh[SKEL_ISO]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) /* int128, int64, ..., int1 = 2, 3, ..., 9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define SKEL_INDEX(exponent) (9 - exponent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define SKEL_ASYNC 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define skel_async_qh skelqh[SKEL_ASYNC]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define SKEL_TERM 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define skel_term_qh skelqh[SKEL_TERM]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) /* The following entries refer to sublists of skel_async_qh */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define SKEL_LS_CONTROL 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define SKEL_FS_CONTROL 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define SKEL_FSBR SKEL_FS_CONTROL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define SKEL_BULK 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) * The UHCI controller and root hub
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) * States for the root hub:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) * To prevent "bouncing" in the presence of electrical noise,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) * when there are no devices attached we delay for 1 second in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) * RUNNING_NODEVS state before switching to the AUTO_STOPPED state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) * (Note that the AUTO_STOPPED state won't be necessary once the hub
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) * driver learns to autosuspend.)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) enum uhci_rh_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) /* In the following states the HC must be halted.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) * These two must come first. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) UHCI_RH_RESET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) UHCI_RH_SUSPENDED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) UHCI_RH_AUTO_STOPPED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) UHCI_RH_RESUMING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) /* In this state the HC changes from running to halted,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) * so it can legally appear either way. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) UHCI_RH_SUSPENDING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) /* In the following states it's an error if the HC is halted.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) * These two must come last. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) UHCI_RH_RUNNING, /* The normal state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) UHCI_RH_RUNNING_NODEVS, /* Running with no devices attached */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) * The full UHCI controller information:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) struct uhci_hcd {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) /* debugfs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) struct dentry *dentry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) /* Grabbed from PCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) unsigned long io_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) /* Used when registers are memory mapped */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) struct dma_pool *qh_pool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) struct dma_pool *td_pool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) struct uhci_td *term_td; /* Terminating TD, see UHCI bug */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) struct uhci_qh *skelqh[UHCI_NUM_SKELQH]; /* Skeleton QHs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) struct uhci_qh *next_qh; /* Next QH to scan */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) dma_addr_t frame_dma_handle; /* Hardware frame list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) __hc32 *frame;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) void **frame_cpu; /* CPU's frame list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) enum uhci_rh_state rh_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) unsigned long auto_stop_time; /* When to AUTO_STOP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) unsigned int frame_number; /* As of last check */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) unsigned int is_stopped;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #define UHCI_IS_STOPPED 9999 /* Larger than a frame # */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) unsigned int last_iso_frame; /* Frame of last scan */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) unsigned int cur_iso_frame; /* Frame for current scan */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) unsigned int scan_in_progress:1; /* Schedule scan is running */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) unsigned int need_rescan:1; /* Redo the schedule scan */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) unsigned int dead:1; /* Controller has died */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) unsigned int RD_enable:1; /* Suspended root hub with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) Resume-Detect interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) unsigned int is_initialized:1; /* Data structure is usable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) unsigned int fsbr_is_on:1; /* FSBR is turned on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) unsigned int fsbr_is_wanted:1; /* Does any URB want FSBR? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) unsigned int fsbr_expiring:1; /* FSBR is timing out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) struct timer_list fsbr_timer; /* For turning off FBSR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) /* Silicon quirks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) unsigned int oc_low:1; /* OverCurrent bit active low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) unsigned int wait_for_hp:1; /* Wait for HP port reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) unsigned int big_endian_mmio:1; /* Big endian registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) unsigned int big_endian_desc:1; /* Big endian descriptors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) unsigned int is_aspeed:1; /* Aspeed impl. workarounds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) /* Support for port suspend/resume/reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) unsigned long port_c_suspend; /* Bit-arrays of ports */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) unsigned long resuming_ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) unsigned long ports_timeout; /* Time to stop signalling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) struct list_head idle_qh_list; /* Where the idle QHs live */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) int rh_numports; /* Number of root-hub ports */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) wait_queue_head_t waitqh; /* endpoint_disable waiters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) int num_waiting; /* Number of waiters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) int total_load; /* Sum of array values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) short load[MAX_PHASE]; /* Periodic allocations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) struct clk *clk; /* (optional) clock source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) /* Reset host controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) void (*reset_hc) (struct uhci_hcd *uhci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) int (*check_and_reset_hc) (struct uhci_hcd *uhci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) /* configure_hc should perform arch specific settings, if needed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) void (*configure_hc) (struct uhci_hcd *uhci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) /* Check for broken resume detect interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) int (*resume_detect_interrupts_are_broken) (struct uhci_hcd *uhci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) /* Check for broken global suspend */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) int (*global_suspend_mode_is_broken) (struct uhci_hcd *uhci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) /* Convert between a usb_hcd pointer and the corresponding uhci_hcd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) static inline struct uhci_hcd *hcd_to_uhci(struct usb_hcd *hcd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) return (struct uhci_hcd *) (hcd->hcd_priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) static inline struct usb_hcd *uhci_to_hcd(struct uhci_hcd *uhci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) return container_of((void *) uhci, struct usb_hcd, hcd_priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) #define uhci_dev(u) (uhci_to_hcd(u)->self.controller)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) /* Utility macro for comparing frame numbers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) #define uhci_frame_before_eq(f1, f2) (0 <= (int) ((f2) - (f1)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) * Private per-URB data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) struct urb_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) struct list_head node; /* Node in the QH's urbp list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) struct urb *urb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) struct uhci_qh *qh; /* QH for this URB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) struct list_head td_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) unsigned fsbr:1; /* URB wants FSBR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) /* Some special IDs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) #define PCI_VENDOR_ID_GENESYS 0x17a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) #define PCI_DEVICE_ID_GL880S_UHCI 0x8083
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) /* Aspeed SoC needs some quirks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) static inline bool uhci_is_aspeed(const struct uhci_hcd *uhci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) return IS_ENABLED(CONFIG_USB_UHCI_ASPEED) && uhci->is_aspeed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) * Functions used to access controller registers. The UCHI spec says that host
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) * controller I/O registers are mapped into PCI I/O space. For non-PCI hosts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) * we use memory mapped registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) #ifndef CONFIG_USB_UHCI_SUPPORT_NON_PCI_HC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) /* Support PCI only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) static inline u32 uhci_readl(const struct uhci_hcd *uhci, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) return inl(uhci->io_addr + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) static inline void uhci_writel(const struct uhci_hcd *uhci, u32 val, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) outl(val, uhci->io_addr + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) static inline u16 uhci_readw(const struct uhci_hcd *uhci, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) return inw(uhci->io_addr + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) static inline void uhci_writew(const struct uhci_hcd *uhci, u16 val, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) outw(val, uhci->io_addr + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) static inline u8 uhci_readb(const struct uhci_hcd *uhci, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) return inb(uhci->io_addr + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) static inline void uhci_writeb(const struct uhci_hcd *uhci, u8 val, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) outb(val, uhci->io_addr + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) /* Support non-PCI host controllers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) #ifdef CONFIG_USB_PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) /* Support PCI and non-PCI host controllers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) #define uhci_has_pci_registers(u) ((u)->io_addr != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) /* Support non-PCI host controllers only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) #define uhci_has_pci_registers(u) 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) #ifdef CONFIG_USB_UHCI_BIG_ENDIAN_MMIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) /* Support (non-PCI) big endian host controllers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) #define uhci_big_endian_mmio(u) ((u)->big_endian_mmio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) #define uhci_big_endian_mmio(u) 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) static inline int uhci_aspeed_reg(unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) case USBCMD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) return 00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) case USBSTS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) return 0x04;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) case USBINTR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) return 0x08;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) case USBFRNUM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) return 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) case USBFLBASEADD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) return 0x0c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) case USBSOF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) return 0x84;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) case USBPORTSC1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) return 0x88;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) case USBPORTSC2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) return 0x8c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) case USBPORTSC3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) return 0x90;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) case USBPORTSC4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) return 0x94;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) pr_warn("UHCI: Unsupported register 0x%02x on Aspeed\n", reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) /* Return an unimplemented register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) return 0x10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) static inline u32 uhci_readl(const struct uhci_hcd *uhci, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) if (uhci_has_pci_registers(uhci))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) return inl(uhci->io_addr + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) else if (uhci_is_aspeed(uhci))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) return readl(uhci->regs + uhci_aspeed_reg(reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) #ifdef CONFIG_USB_UHCI_BIG_ENDIAN_MMIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) else if (uhci_big_endian_mmio(uhci))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) return readl_be(uhci->regs + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) return readl(uhci->regs + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) static inline void uhci_writel(const struct uhci_hcd *uhci, u32 val, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) if (uhci_has_pci_registers(uhci))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) outl(val, uhci->io_addr + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) else if (uhci_is_aspeed(uhci))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) writel(val, uhci->regs + uhci_aspeed_reg(reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) #ifdef CONFIG_USB_UHCI_BIG_ENDIAN_MMIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) else if (uhci_big_endian_mmio(uhci))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) writel_be(val, uhci->regs + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) writel(val, uhci->regs + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) static inline u16 uhci_readw(const struct uhci_hcd *uhci, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) if (uhci_has_pci_registers(uhci))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) return inw(uhci->io_addr + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) else if (uhci_is_aspeed(uhci))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) return readl(uhci->regs + uhci_aspeed_reg(reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) #ifdef CONFIG_USB_UHCI_BIG_ENDIAN_MMIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) else if (uhci_big_endian_mmio(uhci))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) return readw_be(uhci->regs + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) return readw(uhci->regs + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) static inline void uhci_writew(const struct uhci_hcd *uhci, u16 val, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) if (uhci_has_pci_registers(uhci))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) outw(val, uhci->io_addr + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) else if (uhci_is_aspeed(uhci))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) writel(val, uhci->regs + uhci_aspeed_reg(reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) #ifdef CONFIG_USB_UHCI_BIG_ENDIAN_MMIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) else if (uhci_big_endian_mmio(uhci))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) writew_be(val, uhci->regs + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) writew(val, uhci->regs + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) static inline u8 uhci_readb(const struct uhci_hcd *uhci, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) if (uhci_has_pci_registers(uhci))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) return inb(uhci->io_addr + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) else if (uhci_is_aspeed(uhci))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) return readl(uhci->regs + uhci_aspeed_reg(reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) #ifdef CONFIG_USB_UHCI_BIG_ENDIAN_MMIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) else if (uhci_big_endian_mmio(uhci))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) return readb_be(uhci->regs + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) return readb(uhci->regs + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) static inline void uhci_writeb(const struct uhci_hcd *uhci, u8 val, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) if (uhci_has_pci_registers(uhci))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) outb(val, uhci->io_addr + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) else if (uhci_is_aspeed(uhci))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) writel(val, uhci->regs + uhci_aspeed_reg(reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) #ifdef CONFIG_USB_UHCI_BIG_ENDIAN_MMIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) else if (uhci_big_endian_mmio(uhci))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) writeb_be(val, uhci->regs + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) writeb(val, uhci->regs + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) #endif /* CONFIG_USB_UHCI_SUPPORT_NON_PCI_HC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) * The GRLIB GRUSBHC controller can use big endian format for its descriptors.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) * UHCI controllers accessed through PCI work normally (little-endian
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) * everywhere), so we don't bother supporting a BE-only mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) #ifdef CONFIG_USB_UHCI_BIG_ENDIAN_DESC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) #define uhci_big_endian_desc(u) ((u)->big_endian_desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) /* cpu to uhci */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) static inline __hc32 cpu_to_hc32(const struct uhci_hcd *uhci, const u32 x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) return uhci_big_endian_desc(uhci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) ? (__force __hc32)cpu_to_be32(x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) : (__force __hc32)cpu_to_le32(x);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) /* uhci to cpu */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) static inline u32 hc32_to_cpu(const struct uhci_hcd *uhci, const __hc32 x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) return uhci_big_endian_desc(uhci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) ? be32_to_cpu((__force __be32)x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) : le32_to_cpu((__force __le32)x);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) /* cpu to uhci */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) static inline __hc32 cpu_to_hc32(const struct uhci_hcd *uhci, const u32 x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) return cpu_to_le32(x);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) /* uhci to cpu */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) static inline u32 hc32_to_cpu(const struct uhci_hcd *uhci, const __hc32 x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) return le32_to_cpu(x);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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