^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * SL811HS HCD (Host Controller Driver) for USB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2004 Psion Teklogix (for NetBook PRO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2004-2005 David Brownell
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Periodic scheduling is based on Roman's OHCI code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright (C) 1999 Roman Weissgaerber
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * The SL811HS controller handles host side USB (like the SL11H, but with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * another register set and SOF generation) as well as peripheral side USB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * (like the SL811S). This driver version doesn't implement the Gadget API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * for the peripheral role; or OTG (that'd need much external circuitry).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * For documentation, see the SL811HS spec and the "SL811HS Embedded Host"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * document (providing significant pieces missing from that spec); plus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * the SL811S spec if you want peripheral side info.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * Status: Passed basic stress testing, works with hubs, mice, keyboards,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * and usb-storage.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * TODO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * - usb suspend/resume triggered by sl811
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * - various issues noted in the code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * - performance work; use both register banks; ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * - use urb->iso_frame_desc[] with ISO transfers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #undef VERBOSE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #undef PACKET_TRACE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <linux/moduleparam.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #include <linux/timer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #include <linux/list.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #include <linux/usb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #include <linux/usb/sl811.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #include <linux/usb/hcd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #include <linux/prefetch.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #include <linux/debugfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #include <linux/seq_file.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #include <asm/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #include <asm/byteorder.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #include <asm/unaligned.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #include "sl811.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) MODULE_DESCRIPTION("SL811HS USB Host Controller Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) MODULE_ALIAS("platform:sl811-hcd");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define DRIVER_VERSION "19 May 2005"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /* for now, use only one transfer register bank */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #undef USE_B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) // #define QUIRK2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define QUIRK3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) static const char hcd_name[] = "sl811-hcd";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /*-------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) static void port_power(struct sl811 *sl811, int is_on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) struct usb_hcd *hcd = sl811_to_hcd(sl811);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /* hub is inactive unless the port is powered */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) if (is_on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) if (sl811->port1 & USB_PORT_STAT_POWER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) sl811->port1 = USB_PORT_STAT_POWER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) sl811->irq_enable = SL11H_INTMASK_INSRMV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) sl811->port1 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) sl811->irq_enable = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) hcd->state = HC_STATE_HALT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) sl811->ctrl1 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) sl811_write(sl811, SL11H_IRQ_ENABLE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) sl811_write(sl811, SL11H_IRQ_STATUS, ~0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) if (sl811->board && sl811->board->port_power) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /* switch VBUS, at 500mA unless hub power budget gets set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) dev_dbg(hcd->self.controller, "power %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) is_on ? "on" : "off");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) sl811->board->port_power(hcd->self.controller, is_on);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /* reset as thoroughly as we can */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) if (sl811->board && sl811->board->reset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) sl811->board->reset(hcd->self.controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) sl811_write(sl811, SL11H_CTLREG1, SL11H_CTL1MASK_SE0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) mdelay(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) sl811_write(sl811, SL11H_IRQ_ENABLE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) sl811_write(sl811, SL11H_CTLREG1, sl811->ctrl1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) sl811_write(sl811, SL811HS_CTLREG2, SL811HS_CTL2_INIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) sl811_write(sl811, SL11H_IRQ_ENABLE, sl811->irq_enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) // if !is_on, put into lowpower mode now
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /*-------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /* This is a PIO-only HCD. Queueing appends URBs to the endpoint's queue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * and may start I/O. Endpoint queues are scanned during completion irq
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) * handlers (one per packet: ACK, NAK, faults, etc) and urb cancellation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * Using an external DMA engine to copy a packet at a time could work,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * though setup/teardown costs may be too big to make it worthwhile.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /* SETUP starts a new control request. Devices are not allowed to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * STALL or NAK these; they must cancel any pending control requests.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static void setup_packet(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct sl811 *sl811,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) struct sl811h_ep *ep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) struct urb *urb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) u8 bank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) u8 control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) u8 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) u8 len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) void __iomem *data_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) addr = SL811HS_PACKET_BUF(bank == 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) len = sizeof(struct usb_ctrlrequest);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) data_reg = sl811->data_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) sl811_write_buf(sl811, addr, urb->setup_packet, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /* autoincrementing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) sl811_write(sl811, bank + SL11H_BUFADDRREG, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) writeb(len, data_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) writeb(SL_SETUP /* | ep->epnum */, data_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) writeb(usb_pipedevice(urb->pipe), data_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /* always OUT/data0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) sl811_write(sl811, bank + SL11H_HOSTCTLREG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) control | SL11H_HCTLMASK_OUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) ep->length = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) PACKET("SETUP qh%p\n", ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) /* STATUS finishes control requests, often after IN or OUT data packets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static void status_packet(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) struct sl811 *sl811,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) struct sl811h_ep *ep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) struct urb *urb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) u8 bank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) u8 control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) int do_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) void __iomem *data_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) do_out = urb->transfer_buffer_length && usb_pipein(urb->pipe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) data_reg = sl811->data_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) /* autoincrementing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) sl811_write(sl811, bank + SL11H_BUFADDRREG, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) writeb(0, data_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) writeb((do_out ? SL_OUT : SL_IN) /* | ep->epnum */, data_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) writeb(usb_pipedevice(urb->pipe), data_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /* always data1; sometimes IN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) control |= SL11H_HCTLMASK_TOGGLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) if (do_out)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) control |= SL11H_HCTLMASK_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) sl811_write(sl811, bank + SL11H_HOSTCTLREG, control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) ep->length = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) PACKET("STATUS%s/%s qh%p\n", ep->nak_count ? "/retry" : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) do_out ? "out" : "in", ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) /* IN packets can be used with any type of endpoint. here we just
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) * start the transfer, data from the peripheral may arrive later.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) * urb->iso_frame_desc is currently ignored here...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) static void in_packet(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) struct sl811 *sl811,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) struct sl811h_ep *ep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) struct urb *urb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) u8 bank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) u8 control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) u8 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) u8 len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) void __iomem *data_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) /* avoid losing data on overflow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) len = ep->maxpacket;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) addr = SL811HS_PACKET_BUF(bank == 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) if (!(control & SL11H_HCTLMASK_ISOCH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) && usb_gettoggle(urb->dev, ep->epnum, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) control |= SL11H_HCTLMASK_TOGGLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) data_reg = sl811->data_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) /* autoincrementing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) sl811_write(sl811, bank + SL11H_BUFADDRREG, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) writeb(len, data_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) writeb(SL_IN | ep->epnum, data_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) writeb(usb_pipedevice(urb->pipe), data_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) sl811_write(sl811, bank + SL11H_HOSTCTLREG, control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) ep->length = min_t(u32, len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) urb->transfer_buffer_length - urb->actual_length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) PACKET("IN%s/%d qh%p len%d\n", ep->nak_count ? "/retry" : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) !!usb_gettoggle(urb->dev, ep->epnum, 0), ep, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) /* OUT packets can be used with any type of endpoint.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) * urb->iso_frame_desc is currently ignored here...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) static void out_packet(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) struct sl811 *sl811,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) struct sl811h_ep *ep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) struct urb *urb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) u8 bank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) u8 control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) void *buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) u8 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) u8 len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) void __iomem *data_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) buf = urb->transfer_buffer + urb->actual_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) prefetch(buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) len = min_t(u32, ep->maxpacket,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) urb->transfer_buffer_length - urb->actual_length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) if (!(control & SL11H_HCTLMASK_ISOCH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) && usb_gettoggle(urb->dev, ep->epnum, 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) control |= SL11H_HCTLMASK_TOGGLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) addr = SL811HS_PACKET_BUF(bank == 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) data_reg = sl811->data_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) sl811_write_buf(sl811, addr, buf, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) /* autoincrementing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) sl811_write(sl811, bank + SL11H_BUFADDRREG, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) writeb(len, data_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) writeb(SL_OUT | ep->epnum, data_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) writeb(usb_pipedevice(urb->pipe), data_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) sl811_write(sl811, bank + SL11H_HOSTCTLREG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) control | SL11H_HCTLMASK_OUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) ep->length = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) PACKET("OUT%s/%d qh%p len%d\n", ep->nak_count ? "/retry" : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) !!usb_gettoggle(urb->dev, ep->epnum, 1), ep, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) /*-------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) /* caller updates on-chip enables later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) static inline void sofirq_on(struct sl811 *sl811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) if (sl811->irq_enable & SL11H_INTMASK_SOFINTR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) dev_dbg(sl811_to_hcd(sl811)->self.controller, "sof irq on\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) sl811->irq_enable |= SL11H_INTMASK_SOFINTR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) static inline void sofirq_off(struct sl811 *sl811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) if (!(sl811->irq_enable & SL11H_INTMASK_SOFINTR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) dev_dbg(sl811_to_hcd(sl811)->self.controller, "sof irq off\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) sl811->irq_enable &= ~SL11H_INTMASK_SOFINTR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) /*-------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) /* pick the next endpoint for a transaction, and issue it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) * frames start with periodic transfers (after whatever is pending
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) * from the previous frame), and the rest of the time is async
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) * transfers, scheduled round-robin.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) static struct sl811h_ep *start(struct sl811 *sl811, u8 bank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) struct sl811h_ep *ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) struct urb *urb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) int fclock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) u8 control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) /* use endpoint at schedule head */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) if (sl811->next_periodic) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) ep = sl811->next_periodic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) sl811->next_periodic = ep->next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) if (sl811->next_async)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) ep = sl811->next_async;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) else if (!list_empty(&sl811->async))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) ep = container_of(sl811->async.next,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) struct sl811h_ep, schedule);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) /* could set up the first fullspeed periodic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) * transfer for the next frame ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #ifdef USE_B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) if ((bank && sl811->active_b == ep) || sl811->active_a == ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) if (ep->schedule.next == &sl811->async)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) sl811->next_async = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) sl811->next_async = container_of(ep->schedule.next,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) struct sl811h_ep, schedule);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) if (unlikely(list_empty(&ep->hep->urb_list))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) dev_dbg(sl811_to_hcd(sl811)->self.controller,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) "empty %p queue?\n", ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) urb = container_of(ep->hep->urb_list.next, struct urb, urb_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) control = ep->defctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) /* if this frame doesn't have enough time left to transfer this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) * packet, wait till the next frame. too-simple algorithm...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) fclock = sl811_read(sl811, SL11H_SOFTMRREG) << 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) fclock -= 100; /* setup takes not much time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) if (urb->dev->speed == USB_SPEED_LOW) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) if (control & SL11H_HCTLMASK_PREAMBLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) /* also note erratum 1: some hubs won't work */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) fclock -= 800;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) fclock -= ep->maxpacket << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) /* erratum 2: AFTERSOF only works for fullspeed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) if (fclock < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) if (ep->period)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) sl811->stat_overrun++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) sofirq_on(sl811);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) fclock -= 12000 / 19; /* 19 64byte packets/msec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) if (fclock < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) if (ep->period)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) sl811->stat_overrun++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) control |= SL11H_HCTLMASK_AFTERSOF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) /* throttle bulk/control irq noise */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) } else if (ep->nak_count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) control |= SL11H_HCTLMASK_AFTERSOF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) switch (ep->nextpid) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) case USB_PID_IN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) in_packet(sl811, ep, urb, bank, control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) case USB_PID_OUT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) out_packet(sl811, ep, urb, bank, control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) case USB_PID_SETUP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) setup_packet(sl811, ep, urb, bank, control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) case USB_PID_ACK: /* for control status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) status_packet(sl811, ep, urb, bank, control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) dev_dbg(sl811_to_hcd(sl811)->self.controller,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) "bad ep%p pid %02x\n", ep, ep->nextpid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) ep = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) return ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define MIN_JIFFIES ((msecs_to_jiffies(2) > 1) ? msecs_to_jiffies(2) : 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) static inline void start_transfer(struct sl811 *sl811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) if (sl811->port1 & USB_PORT_STAT_SUSPEND)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) if (sl811->active_a == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) sl811->active_a = start(sl811, SL811_EP_A(SL811_HOST_BUF));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) if (sl811->active_a != NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) sl811->jiffies_a = jiffies + MIN_JIFFIES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #ifdef USE_B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) if (sl811->active_b == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) sl811->active_b = start(sl811, SL811_EP_B(SL811_HOST_BUF));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) if (sl811->active_b != NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) sl811->jiffies_b = jiffies + MIN_JIFFIES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) static void finish_request(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) struct sl811 *sl811,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) struct sl811h_ep *ep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) struct urb *urb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) int status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) ) __releases(sl811->lock) __acquires(sl811->lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) unsigned i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) if (usb_pipecontrol(urb->pipe))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) ep->nextpid = USB_PID_SETUP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) usb_hcd_unlink_urb_from_ep(sl811_to_hcd(sl811), urb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) spin_unlock(&sl811->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) usb_hcd_giveback_urb(sl811_to_hcd(sl811), urb, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) spin_lock(&sl811->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) /* leave active endpoints in the schedule */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) if (!list_empty(&ep->hep->urb_list))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) /* async deschedule? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) if (!list_empty(&ep->schedule)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) list_del_init(&ep->schedule);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) if (ep == sl811->next_async)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) sl811->next_async = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) /* periodic deschedule */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) dev_dbg(sl811_to_hcd(sl811)->self.controller,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) "deschedule qh%d/%p branch %d\n", ep->period, ep, ep->branch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) for (i = ep->branch; i < PERIODIC_SIZE; i += ep->period) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) struct sl811h_ep *temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) struct sl811h_ep **prev = &sl811->periodic[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) while (*prev && ((temp = *prev) != ep))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) prev = &temp->next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) if (*prev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) *prev = ep->next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) sl811->load[i] -= ep->load;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) ep->branch = PERIODIC_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) sl811->periodic_count--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) sl811_to_hcd(sl811)->self.bandwidth_allocated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) -= ep->load / ep->period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) if (ep == sl811->next_periodic)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) sl811->next_periodic = ep->next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) /* we might turn SOFs back on again for the async schedule */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) if (sl811->periodic_count == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) sofirq_off(sl811);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) done(struct sl811 *sl811, struct sl811h_ep *ep, u8 bank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) u8 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) struct urb *urb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) int urbstat = -EINPROGRESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) if (unlikely(!ep))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) status = sl811_read(sl811, bank + SL11H_PKTSTATREG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) urb = container_of(ep->hep->urb_list.next, struct urb, urb_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) /* we can safely ignore NAKs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) if (status & SL11H_STATMASK_NAK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) // PACKET("...NAK_%02x qh%p\n", bank, ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) if (!ep->period)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) ep->nak_count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) ep->error_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) /* ACK advances transfer, toggle, and maybe queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) } else if (status & SL11H_STATMASK_ACK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) struct usb_device *udev = urb->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) int len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) unsigned char *buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) /* urb->iso_frame_desc is currently ignored here... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) ep->nak_count = ep->error_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) switch (ep->nextpid) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) case USB_PID_OUT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) // PACKET("...ACK/out_%02x qh%p\n", bank, ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) urb->actual_length += ep->length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) usb_dotoggle(udev, ep->epnum, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) if (urb->actual_length
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) == urb->transfer_buffer_length) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) if (usb_pipecontrol(urb->pipe))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) ep->nextpid = USB_PID_ACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) /* some bulk protocols terminate OUT transfers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) * by a short packet, using ZLPs not padding.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) else if (ep->length < ep->maxpacket
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) || !(urb->transfer_flags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) & URB_ZERO_PACKET))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) urbstat = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) case USB_PID_IN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) // PACKET("...ACK/in_%02x qh%p\n", bank, ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) buf = urb->transfer_buffer + urb->actual_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) prefetchw(buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) len = ep->maxpacket - sl811_read(sl811,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) bank + SL11H_XFERCNTREG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) if (len > ep->length) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) len = ep->length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) urbstat = -EOVERFLOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) urb->actual_length += len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) sl811_read_buf(sl811, SL811HS_PACKET_BUF(bank == 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) buf, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) usb_dotoggle(udev, ep->epnum, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) if (urbstat == -EINPROGRESS &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) (len < ep->maxpacket ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) urb->actual_length ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) urb->transfer_buffer_length)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) if (usb_pipecontrol(urb->pipe))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) ep->nextpid = USB_PID_ACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) urbstat = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) case USB_PID_SETUP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) // PACKET("...ACK/setup_%02x qh%p\n", bank, ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) if (urb->transfer_buffer_length == urb->actual_length)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) ep->nextpid = USB_PID_ACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) else if (usb_pipeout(urb->pipe)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) usb_settoggle(udev, 0, 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) ep->nextpid = USB_PID_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) usb_settoggle(udev, 0, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) ep->nextpid = USB_PID_IN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) case USB_PID_ACK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) // PACKET("...ACK/status_%02x qh%p\n", bank, ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) urbstat = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) /* STALL stops all transfers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) } else if (status & SL11H_STATMASK_STALL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) PACKET("...STALL_%02x qh%p\n", bank, ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) ep->nak_count = ep->error_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) urbstat = -EPIPE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) /* error? retry, until "3 strikes" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) } else if (++ep->error_count >= 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) if (status & SL11H_STATMASK_TMOUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) urbstat = -ETIME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) else if (status & SL11H_STATMASK_OVF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) urbstat = -EOVERFLOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) urbstat = -EPROTO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) ep->error_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) PACKET("...3STRIKES_%02x %02x qh%p stat %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) bank, status, ep, urbstat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) if (urbstat != -EINPROGRESS || urb->unlinked)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) finish_request(sl811, ep, urb, urbstat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) static inline u8 checkdone(struct sl811 *sl811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) u8 ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) u8 irqstat = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) if (sl811->active_a && time_before_eq(sl811->jiffies_a, jiffies)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) ctl = sl811_read(sl811, SL811_EP_A(SL11H_HOSTCTLREG));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) if (ctl & SL11H_HCTLMASK_ARM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) sl811_write(sl811, SL811_EP_A(SL11H_HOSTCTLREG), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) dev_dbg(sl811_to_hcd(sl811)->self.controller,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) "%s DONE_A: ctrl %02x sts %02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) (ctl & SL11H_HCTLMASK_ARM) ? "timeout" : "lost",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) ctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) sl811_read(sl811, SL811_EP_A(SL11H_PKTSTATREG)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) irqstat |= SL11H_INTMASK_DONE_A;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) #ifdef USE_B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) if (sl811->active_b && time_before_eq(sl811->jiffies_b, jiffies)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) ctl = sl811_read(sl811, SL811_EP_B(SL11H_HOSTCTLREG));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) if (ctl & SL11H_HCTLMASK_ARM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) sl811_write(sl811, SL811_EP_B(SL11H_HOSTCTLREG), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) dev_dbg(sl811_to_hcd(sl811)->self.controller,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) "%s DONE_B: ctrl %02x sts %02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) (ctl & SL11H_HCTLMASK_ARM) ? "timeout" : "lost",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) ctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) sl811_read(sl811, SL811_EP_B(SL11H_PKTSTATREG)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) irqstat |= SL11H_INTMASK_DONE_A;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) return irqstat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) static irqreturn_t sl811h_irq(struct usb_hcd *hcd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) struct sl811 *sl811 = hcd_to_sl811(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) u8 irqstat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) irqreturn_t ret = IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) unsigned retries = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) spin_lock(&sl811->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) retry:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) irqstat = sl811_read(sl811, SL11H_IRQ_STATUS) & ~SL11H_INTMASK_DP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) if (irqstat) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) sl811_write(sl811, SL11H_IRQ_STATUS, irqstat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) irqstat &= sl811->irq_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) #ifdef QUIRK2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) /* this may no longer be necessary ... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) if (irqstat == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) irqstat = checkdone(sl811);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) if (irqstat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) sl811->stat_lost++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) /* USB packets, not necessarily handled in the order they're
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) * issued ... that's fine if they're different endpoints.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) if (irqstat & SL11H_INTMASK_DONE_A) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) done(sl811, sl811->active_a, SL811_EP_A(SL811_HOST_BUF));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) sl811->active_a = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) sl811->stat_a++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) #ifdef USE_B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) if (irqstat & SL11H_INTMASK_DONE_B) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) done(sl811, sl811->active_b, SL811_EP_B(SL811_HOST_BUF));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) sl811->active_b = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) sl811->stat_b++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) if (irqstat & SL11H_INTMASK_SOFINTR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) unsigned index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) index = sl811->frame++ % (PERIODIC_SIZE - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) sl811->stat_sof++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) /* be graceful about almost-inevitable periodic schedule
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) * overruns: continue the previous frame's transfers iff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) * this one has nothing scheduled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) if (sl811->next_periodic) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) // dev_err(hcd->self.controller, "overrun to slot %d\n", index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) sl811->stat_overrun++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) if (sl811->periodic[index])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) sl811->next_periodic = sl811->periodic[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) /* hub_wq manages debouncing and wakeup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) if (irqstat & SL11H_INTMASK_INSRMV) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) sl811->stat_insrmv++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) /* most stats are reset for each VBUS session */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) sl811->stat_wake = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) sl811->stat_sof = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) sl811->stat_a = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) sl811->stat_b = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) sl811->stat_lost = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) sl811->ctrl1 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) sl811_write(sl811, SL11H_CTLREG1, sl811->ctrl1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) sl811->irq_enable = SL11H_INTMASK_INSRMV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) sl811_write(sl811, SL11H_IRQ_ENABLE, sl811->irq_enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) /* usbcore nukes other pending transactions on disconnect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) if (sl811->active_a) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) sl811_write(sl811, SL811_EP_A(SL11H_HOSTCTLREG), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) finish_request(sl811, sl811->active_a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) container_of(sl811->active_a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) ->hep->urb_list.next,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) struct urb, urb_list),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) -ESHUTDOWN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) sl811->active_a = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) #ifdef USE_B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) if (sl811->active_b) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) sl811_write(sl811, SL811_EP_B(SL11H_HOSTCTLREG), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) finish_request(sl811, sl811->active_b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) container_of(sl811->active_b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) ->hep->urb_list.next,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) struct urb, urb_list),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) NULL, -ESHUTDOWN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) sl811->active_b = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) /* port status seems weird until after reset, so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) * force the reset and make hub_wq clean up later.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) if (irqstat & SL11H_INTMASK_RD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) sl811->port1 &= ~USB_PORT_STAT_CONNECTION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) sl811->port1 |= USB_PORT_STAT_CONNECTION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) sl811->port1 |= USB_PORT_STAT_C_CONNECTION << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) } else if (irqstat & SL11H_INTMASK_RD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) if (sl811->port1 & USB_PORT_STAT_SUSPEND) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) dev_dbg(hcd->self.controller, "wakeup\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) sl811->port1 |= USB_PORT_STAT_C_SUSPEND << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) sl811->stat_wake++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) irqstat &= ~SL11H_INTMASK_RD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) if (irqstat) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) if (sl811->port1 & USB_PORT_STAT_ENABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) start_transfer(sl811);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) ret = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) if (retries--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) goto retry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) if (sl811->periodic_count == 0 && list_empty(&sl811->async))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) sofirq_off(sl811);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) sl811_write(sl811, SL11H_IRQ_ENABLE, sl811->irq_enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) spin_unlock(&sl811->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) /*-------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) /* usb 1.1 says max 90% of a frame is available for periodic transfers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) * this driver doesn't promise that much since it's got to handle an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) * IRQ per packet; irq handling latencies also use up that time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) * NOTE: the periodic schedule is a sparse tree, with the load for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) * each branch minimized. see fig 3.5 in the OHCI spec for example.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) #define MAX_PERIODIC_LOAD 500 /* out of 1000 usec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) static int balance(struct sl811 *sl811, u16 period, u16 load)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) int i, branch = -ENOSPC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) /* search for the least loaded schedule branch of that period
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) * which has enough bandwidth left unreserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) for (i = 0; i < period ; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) if (branch < 0 || sl811->load[branch] > sl811->load[i]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) int j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) for (j = i; j < PERIODIC_SIZE; j += period) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) if ((sl811->load[j] + load)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) > MAX_PERIODIC_LOAD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) if (j < PERIODIC_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) branch = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) return branch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) /*-------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) static int sl811h_urb_enqueue(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) struct usb_hcd *hcd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) struct urb *urb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) gfp_t mem_flags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) struct sl811 *sl811 = hcd_to_sl811(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) struct usb_device *udev = urb->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) unsigned int pipe = urb->pipe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) int is_out = !usb_pipein(pipe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) int type = usb_pipetype(pipe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) int epnum = usb_pipeendpoint(pipe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) struct sl811h_ep *ep = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) int retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) struct usb_host_endpoint *hep = urb->ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) #ifndef CONFIG_USB_SL811_HCD_ISO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) if (type == PIPE_ISOCHRONOUS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) return -ENOSPC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) /* avoid all allocations within spinlocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) if (!hep->hcpriv) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) ep = kzalloc(sizeof *ep, mem_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) if (ep == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) spin_lock_irqsave(&sl811->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) /* don't submit to a dead or disabled port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) if (!(sl811->port1 & USB_PORT_STAT_ENABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) || !HC_IS_RUNNING(hcd->state)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) retval = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) kfree(ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) goto fail_not_linked;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) retval = usb_hcd_link_urb_to_ep(hcd, urb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) if (retval) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) kfree(ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) goto fail_not_linked;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) if (hep->hcpriv) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) kfree(ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) ep = hep->hcpriv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) } else if (!ep) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) retval = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) INIT_LIST_HEAD(&ep->schedule);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) ep->udev = udev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) ep->epnum = epnum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) ep->maxpacket = usb_maxpacket(udev, urb->pipe, is_out);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) ep->defctrl = SL11H_HCTLMASK_ARM | SL11H_HCTLMASK_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) usb_settoggle(udev, epnum, is_out, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) if (type == PIPE_CONTROL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) ep->nextpid = USB_PID_SETUP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) else if (is_out)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) ep->nextpid = USB_PID_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) ep->nextpid = USB_PID_IN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) if (ep->maxpacket > H_MAXPACKET) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) /* iso packets up to 240 bytes could work... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) dev_dbg(hcd->self.controller,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) "dev %d ep%d maxpacket %d\n", udev->devnum,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) epnum, ep->maxpacket);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) retval = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) kfree(ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) if (udev->speed == USB_SPEED_LOW) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) /* send preamble for external hub? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) if (!(sl811->ctrl1 & SL11H_CTL1MASK_LSPD))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) ep->defctrl |= SL11H_HCTLMASK_PREAMBLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) case PIPE_ISOCHRONOUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) case PIPE_INTERRUPT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) if (urb->interval > PERIODIC_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) urb->interval = PERIODIC_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) ep->period = urb->interval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) ep->branch = PERIODIC_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) if (type == PIPE_ISOCHRONOUS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) ep->defctrl |= SL11H_HCTLMASK_ISOCH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) ep->load = usb_calc_bus_time(udev->speed, !is_out,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) (type == PIPE_ISOCHRONOUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) usb_maxpacket(udev, pipe, is_out))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) ep->hep = hep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) hep->hcpriv = ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) /* maybe put endpoint into schedule */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) case PIPE_CONTROL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) case PIPE_BULK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) if (list_empty(&ep->schedule))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) list_add_tail(&ep->schedule, &sl811->async);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) case PIPE_ISOCHRONOUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) case PIPE_INTERRUPT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) urb->interval = ep->period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) if (ep->branch < PERIODIC_SIZE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) /* NOTE: the phase is correct here, but the value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) * needs offsetting by the transfer queue depth.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) * All current drivers ignore start_frame, so this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) * is unlikely to ever matter...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) urb->start_frame = (sl811->frame & (PERIODIC_SIZE - 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) + ep->branch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) retval = balance(sl811, ep->period, ep->load);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) if (retval < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) ep->branch = retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) retval = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) urb->start_frame = (sl811->frame & (PERIODIC_SIZE - 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) + ep->branch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) /* sort each schedule branch by period (slow before fast)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) * to share the faster parts of the tree without needing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) * dummy/placeholder nodes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) dev_dbg(hcd->self.controller, "schedule qh%d/%p branch %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) ep->period, ep, ep->branch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) for (i = ep->branch; i < PERIODIC_SIZE; i += ep->period) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) struct sl811h_ep **prev = &sl811->periodic[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) struct sl811h_ep *here = *prev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) while (here && ep != here) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) if (ep->period > here->period)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) prev = &here->next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) here = *prev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) if (ep != here) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) ep->next = here;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) *prev = ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) sl811->load[i] += ep->load;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) sl811->periodic_count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) hcd->self.bandwidth_allocated += ep->load / ep->period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) sofirq_on(sl811);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) urb->hcpriv = hep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) start_transfer(sl811);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) sl811_write(sl811, SL11H_IRQ_ENABLE, sl811->irq_enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) if (retval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) usb_hcd_unlink_urb_from_ep(hcd, urb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) fail_not_linked:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) spin_unlock_irqrestore(&sl811->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) static int sl811h_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) struct sl811 *sl811 = hcd_to_sl811(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) struct usb_host_endpoint *hep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) struct sl811h_ep *ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) int retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) spin_lock_irqsave(&sl811->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) retval = usb_hcd_check_unlink_urb(hcd, urb, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) if (retval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) hep = urb->hcpriv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) ep = hep->hcpriv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) if (ep) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) /* finish right away if this urb can't be active ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) * note that some drivers wrongly expect delays
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) if (ep->hep->urb_list.next != &urb->urb_list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) /* not front of queue? never active */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) /* for active transfers, we expect an IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) } else if (sl811->active_a == ep) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) if (time_before_eq(sl811->jiffies_a, jiffies)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) /* happens a lot with lowspeed?? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) dev_dbg(hcd->self.controller,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) "giveup on DONE_A: ctrl %02x sts %02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) sl811_read(sl811,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) SL811_EP_A(SL11H_HOSTCTLREG)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) sl811_read(sl811,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) SL811_EP_A(SL11H_PKTSTATREG)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) sl811_write(sl811, SL811_EP_A(SL11H_HOSTCTLREG),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) sl811->active_a = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) urb = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) #ifdef USE_B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) } else if (sl811->active_b == ep) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) if (time_before_eq(sl811->jiffies_a, jiffies)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) /* happens a lot with lowspeed?? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) dev_dbg(hcd->self.controller,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) "giveup on DONE_B: ctrl %02x sts %02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) sl811_read(sl811,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) SL811_EP_B(SL11H_HOSTCTLREG)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) sl811_read(sl811,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) SL811_EP_B(SL11H_PKTSTATREG)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) sl811_write(sl811, SL811_EP_B(SL11H_HOSTCTLREG),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) sl811->active_b = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) urb = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) /* front of queue for inactive endpoint */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) if (urb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) finish_request(sl811, ep, urb, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) dev_dbg(sl811_to_hcd(sl811)->self.controller,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) "dequeue, urb %p active %s; wait4irq\n", urb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) (sl811->active_a == ep) ? "A" : "B");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) retval = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) spin_unlock_irqrestore(&sl811->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) sl811h_endpoint_disable(struct usb_hcd *hcd, struct usb_host_endpoint *hep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) struct sl811h_ep *ep = hep->hcpriv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) if (!ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) /* assume we'd just wait for the irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) if (!list_empty(&hep->urb_list))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) msleep(3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) if (!list_empty(&hep->urb_list))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) dev_warn(hcd->self.controller, "ep %p not empty?\n", ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) kfree(ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) hep->hcpriv = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) sl811h_get_frame(struct usb_hcd *hcd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) struct sl811 *sl811 = hcd_to_sl811(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) /* wrong except while periodic transfers are scheduled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) * never matches the on-the-wire frame;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) * subject to overruns.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) return sl811->frame;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) /*-------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) /* the virtual root hub timer IRQ checks for hub status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) sl811h_hub_status_data(struct usb_hcd *hcd, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) struct sl811 *sl811 = hcd_to_sl811(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) #ifdef QUIRK3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) /* non-SMP HACK: use root hub timer as i/o watchdog
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) * this seems essential when SOF IRQs aren't in use...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) if (!timer_pending(&sl811->timer)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) if (sl811h_irq( /* ~0, */ hcd) != IRQ_NONE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) sl811->stat_lost++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) if (!(sl811->port1 & (0xffff << 16)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) /* tell hub_wq port 1 changed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) *buf = (1 << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) sl811h_hub_descriptor (
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) struct sl811 *sl811,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) struct usb_hub_descriptor *desc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) u16 temp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) desc->bDescriptorType = USB_DT_HUB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) desc->bHubContrCurrent = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) desc->bNbrPorts = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) desc->bDescLength = 9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) /* per-port power switching (gang of one!), or none */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) desc->bPwrOn2PwrGood = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) if (sl811->board && sl811->board->port_power) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) desc->bPwrOn2PwrGood = sl811->board->potpg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) if (!desc->bPwrOn2PwrGood)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) desc->bPwrOn2PwrGood = 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) temp = HUB_CHAR_INDV_PORT_LPSM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) temp = HUB_CHAR_NO_LPSM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) /* no overcurrent errors detection/handling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) temp |= HUB_CHAR_NO_OCPM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) desc->wHubCharacteristics = cpu_to_le16(temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) /* ports removable, and legacy PortPwrCtrlMask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) desc->u.hs.DeviceRemovable[0] = 0 << 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) desc->u.hs.DeviceRemovable[1] = ~0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) sl811h_timer(struct timer_list *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) struct sl811 *sl811 = from_timer(sl811, t, timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) u8 irqstat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) u8 signaling = sl811->ctrl1 & SL11H_CTL1MASK_FORCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) const u32 mask = USB_PORT_STAT_CONNECTION
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) | USB_PORT_STAT_ENABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) | USB_PORT_STAT_LOW_SPEED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) spin_lock_irqsave(&sl811->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) /* stop special signaling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) sl811->ctrl1 &= ~SL11H_CTL1MASK_FORCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) sl811_write(sl811, SL11H_CTLREG1, sl811->ctrl1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) udelay(3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) irqstat = sl811_read(sl811, SL11H_IRQ_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) switch (signaling) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) case SL11H_CTL1MASK_SE0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) dev_dbg(sl811_to_hcd(sl811)->self.controller, "end reset\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) sl811->port1 = (USB_PORT_STAT_C_RESET << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) | USB_PORT_STAT_POWER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) sl811->ctrl1 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) /* don't wrongly ack RD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) if (irqstat & SL11H_INTMASK_INSRMV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) irqstat &= ~SL11H_INTMASK_RD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) case SL11H_CTL1MASK_K:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) dev_dbg(sl811_to_hcd(sl811)->self.controller, "end resume\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) sl811->port1 &= ~USB_PORT_STAT_SUSPEND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) dev_dbg(sl811_to_hcd(sl811)->self.controller,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) "odd timer signaling: %02x\n", signaling);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) sl811_write(sl811, SL11H_IRQ_STATUS, irqstat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) if (irqstat & SL11H_INTMASK_RD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) /* usbcore nukes all pending transactions on disconnect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) if (sl811->port1 & USB_PORT_STAT_CONNECTION)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) sl811->port1 |= (USB_PORT_STAT_C_CONNECTION << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) | (USB_PORT_STAT_C_ENABLE << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) sl811->port1 &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) sl811->irq_enable = SL11H_INTMASK_INSRMV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) sl811->port1 |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) if (irqstat & SL11H_INTMASK_DP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) sl811->port1 &= ~USB_PORT_STAT_LOW_SPEED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) sl811->irq_enable = SL11H_INTMASK_INSRMV | SL11H_INTMASK_RD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) if (sl811->port1 & USB_PORT_STAT_CONNECTION) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) u8 ctrl2 = SL811HS_CTL2_INIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) sl811->irq_enable |= SL11H_INTMASK_DONE_A;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) #ifdef USE_B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) sl811->irq_enable |= SL11H_INTMASK_DONE_B;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) if (sl811->port1 & USB_PORT_STAT_LOW_SPEED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) sl811->ctrl1 |= SL11H_CTL1MASK_LSPD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) ctrl2 |= SL811HS_CTL2MASK_DSWAP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) /* start SOFs flowing, kickstarting with A registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) sl811->ctrl1 |= SL11H_CTL1MASK_SOF_ENA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) sl811_write(sl811, SL11H_SOFLOWREG, 0xe0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) sl811_write(sl811, SL811HS_CTLREG2, ctrl2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) /* autoincrementing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) sl811_write(sl811, SL811_EP_A(SL11H_BUFLNTHREG), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) writeb(SL_SOF, sl811->data_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) writeb(0, sl811->data_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) sl811_write(sl811, SL811_EP_A(SL11H_HOSTCTLREG),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) SL11H_HCTLMASK_ARM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) /* hub_wq provides debounce delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) sl811->ctrl1 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) sl811_write(sl811, SL11H_CTLREG1, sl811->ctrl1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) /* reenable irqs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) sl811_write(sl811, SL11H_IRQ_ENABLE, sl811->irq_enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) spin_unlock_irqrestore(&sl811->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) sl811h_hub_control(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) struct usb_hcd *hcd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) u16 typeReq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) u16 wValue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) u16 wIndex,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) char *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) u16 wLength
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) struct sl811 *sl811 = hcd_to_sl811(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) int retval = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) spin_lock_irqsave(&sl811->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) switch (typeReq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) case ClearHubFeature:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) case SetHubFeature:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) switch (wValue) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) case C_HUB_OVER_CURRENT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) case C_HUB_LOCAL_POWER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) case ClearPortFeature:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) if (wIndex != 1 || wLength != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) switch (wValue) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) case USB_PORT_FEAT_ENABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) sl811->port1 &= USB_PORT_STAT_POWER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) sl811->ctrl1 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) sl811_write(sl811, SL11H_CTLREG1, sl811->ctrl1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) sl811->irq_enable = SL11H_INTMASK_INSRMV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) sl811_write(sl811, SL11H_IRQ_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) sl811->irq_enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) case USB_PORT_FEAT_SUSPEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) if (!(sl811->port1 & USB_PORT_STAT_SUSPEND))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) /* 20 msec of resume/K signaling, other irqs blocked */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) dev_dbg(hcd->self.controller, "start resume...\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) sl811->irq_enable = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) sl811_write(sl811, SL11H_IRQ_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) sl811->irq_enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) sl811->ctrl1 |= SL11H_CTL1MASK_K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) sl811_write(sl811, SL11H_CTLREG1, sl811->ctrl1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) mod_timer(&sl811->timer, jiffies
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) + msecs_to_jiffies(USB_RESUME_TIMEOUT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) case USB_PORT_FEAT_POWER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) port_power(sl811, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) case USB_PORT_FEAT_C_ENABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) case USB_PORT_FEAT_C_SUSPEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) case USB_PORT_FEAT_C_CONNECTION:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) case USB_PORT_FEAT_C_OVER_CURRENT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) case USB_PORT_FEAT_C_RESET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) sl811->port1 &= ~(1 << wValue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) case GetHubDescriptor:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) sl811h_hub_descriptor(sl811, (struct usb_hub_descriptor *) buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) case GetHubStatus:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) put_unaligned_le32(0, buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) case GetPortStatus:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) if (wIndex != 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) put_unaligned_le32(sl811->port1, buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) if (__is_defined(VERBOSE) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) *(u16*)(buf+2)) /* only if wPortChange is interesting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) dev_dbg(hcd->self.controller, "GetPortStatus %08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) sl811->port1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) case SetPortFeature:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) if (wIndex != 1 || wLength != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) switch (wValue) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) case USB_PORT_FEAT_SUSPEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) if (sl811->port1 & USB_PORT_STAT_RESET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) if (!(sl811->port1 & USB_PORT_STAT_ENABLE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) dev_dbg(hcd->self.controller,"suspend...\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) sl811->ctrl1 &= ~SL11H_CTL1MASK_SOF_ENA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) sl811_write(sl811, SL11H_CTLREG1, sl811->ctrl1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) case USB_PORT_FEAT_POWER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) port_power(sl811, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) case USB_PORT_FEAT_RESET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) if (sl811->port1 & USB_PORT_STAT_SUSPEND)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) if (!(sl811->port1 & USB_PORT_STAT_POWER))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) /* 50 msec of reset/SE0 signaling, irqs blocked */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) sl811->irq_enable = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) sl811_write(sl811, SL11H_IRQ_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) sl811->irq_enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) sl811->ctrl1 = SL11H_CTL1MASK_SE0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) sl811_write(sl811, SL11H_CTLREG1, sl811->ctrl1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) sl811->port1 |= USB_PORT_STAT_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) mod_timer(&sl811->timer, jiffies
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) + msecs_to_jiffies(50));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) sl811->port1 |= 1 << wValue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) /* "protocol stall" on error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) retval = -EPIPE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) spin_unlock_irqrestore(&sl811->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) sl811h_bus_suspend(struct usb_hcd *hcd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) // SOFs off
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) dev_dbg(hcd->self.controller, "%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) sl811h_bus_resume(struct usb_hcd *hcd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) // SOFs on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) dev_dbg(hcd->self.controller, "%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) #define sl811h_bus_suspend NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) #define sl811h_bus_resume NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) /*-------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) static void dump_irq(struct seq_file *s, char *label, u8 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) seq_printf(s, "%s %02x%s%s%s%s%s%s\n", label, mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) (mask & SL11H_INTMASK_DONE_A) ? " done_a" : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) (mask & SL11H_INTMASK_DONE_B) ? " done_b" : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) (mask & SL11H_INTMASK_SOFINTR) ? " sof" : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) (mask & SL11H_INTMASK_INSRMV) ? " ins/rmv" : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) (mask & SL11H_INTMASK_RD) ? " rd" : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) (mask & SL11H_INTMASK_DP) ? " dp" : "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) static int sl811h_debug_show(struct seq_file *s, void *unused)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) struct sl811 *sl811 = s->private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) struct sl811h_ep *ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) unsigned i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) seq_printf(s, "%s\n%s version %s\nportstatus[1] = %08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) sl811_to_hcd(sl811)->product_desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) hcd_name, DRIVER_VERSION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) sl811->port1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) seq_printf(s, "insert/remove: %ld\n", sl811->stat_insrmv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) seq_printf(s, "current session: done_a %ld done_b %ld "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) "wake %ld sof %ld overrun %ld lost %ld\n\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) sl811->stat_a, sl811->stat_b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) sl811->stat_wake, sl811->stat_sof,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) sl811->stat_overrun, sl811->stat_lost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) spin_lock_irq(&sl811->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) if (sl811->ctrl1 & SL11H_CTL1MASK_SUSPEND)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) seq_printf(s, "(suspended)\n\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) u8 t = sl811_read(sl811, SL11H_CTLREG1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) seq_printf(s, "ctrl1 %02x%s%s%s%s\n", t,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) (t & SL11H_CTL1MASK_SOF_ENA) ? " sofgen" : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) ({char *s; switch (t & SL11H_CTL1MASK_FORCE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) case SL11H_CTL1MASK_NORMAL: s = ""; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) case SL11H_CTL1MASK_SE0: s = " se0/reset"; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) case SL11H_CTL1MASK_K: s = " k/resume"; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) default: s = "j"; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) } s; }),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) (t & SL11H_CTL1MASK_LSPD) ? " lowspeed" : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) (t & SL11H_CTL1MASK_SUSPEND) ? " suspend" : "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) dump_irq(s, "irq_enable",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) sl811_read(sl811, SL11H_IRQ_ENABLE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) dump_irq(s, "irq_status",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) sl811_read(sl811, SL11H_IRQ_STATUS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) seq_printf(s, "frame clocks remaining: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) sl811_read(sl811, SL11H_SOFTMRREG) << 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) seq_printf(s, "A: qh%p ctl %02x sts %02x\n", sl811->active_a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) sl811_read(sl811, SL811_EP_A(SL11H_HOSTCTLREG)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) sl811_read(sl811, SL811_EP_A(SL11H_PKTSTATREG)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) seq_printf(s, "B: qh%p ctl %02x sts %02x\n", sl811->active_b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) sl811_read(sl811, SL811_EP_B(SL11H_HOSTCTLREG)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) sl811_read(sl811, SL811_EP_B(SL11H_PKTSTATREG)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) seq_printf(s, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) list_for_each_entry (ep, &sl811->async, schedule) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) struct urb *urb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) seq_printf(s, "%s%sqh%p, ep%d%s, maxpacket %d"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) " nak %d err %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) (ep == sl811->active_a) ? "(A) " : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) (ep == sl811->active_b) ? "(B) " : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) ep, ep->epnum,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) ({ char *s; switch (ep->nextpid) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) case USB_PID_IN: s = "in"; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) case USB_PID_OUT: s = "out"; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) case USB_PID_SETUP: s = "setup"; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) case USB_PID_ACK: s = "status"; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) default: s = "?"; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) } s;}),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) ep->maxpacket,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) ep->nak_count, ep->error_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) list_for_each_entry (urb, &ep->hep->urb_list, urb_list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) seq_printf(s, " urb%p, %d/%d\n", urb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) urb->actual_length,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) urb->transfer_buffer_length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) if (!list_empty(&sl811->async))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) seq_printf(s, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) seq_printf(s, "periodic size= %d\n", PERIODIC_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) for (i = 0; i < PERIODIC_SIZE; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) ep = sl811->periodic[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) if (!ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) seq_printf(s, "%2d [%3d]:\n", i, sl811->load[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) /* DUMB: prints shared entries multiple times */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) seq_printf(s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) " %s%sqh%d/%p (%sdev%d ep%d%s max %d) "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) "err %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) (ep == sl811->active_a) ? "(A) " : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) (ep == sl811->active_b) ? "(B) " : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) ep->period, ep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) (ep->udev->speed == USB_SPEED_FULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) ? "" : "ls ",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) ep->udev->devnum, ep->epnum,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) (ep->epnum == 0) ? ""
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) : ((ep->nextpid == USB_PID_IN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) ? "in"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) : "out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) ep->maxpacket, ep->error_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) ep = ep->next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) } while (ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) spin_unlock_irq(&sl811->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) seq_printf(s, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) DEFINE_SHOW_ATTRIBUTE(sl811h_debug);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) /* expect just one sl811 per system */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) static void create_debug_file(struct sl811 *sl811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) sl811->debug_file = debugfs_create_file("sl811h", S_IRUGO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) usb_debug_root, sl811,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) &sl811h_debug_fops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) static void remove_debug_file(struct sl811 *sl811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) debugfs_remove(sl811->debug_file);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) /*-------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) sl811h_stop(struct usb_hcd *hcd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) struct sl811 *sl811 = hcd_to_sl811(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) del_timer_sync(&hcd->rh_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) spin_lock_irqsave(&sl811->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) port_power(sl811, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) spin_unlock_irqrestore(&sl811->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) sl811h_start(struct usb_hcd *hcd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) struct sl811 *sl811 = hcd_to_sl811(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) /* chip has been reset, VBUS power is off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) hcd->state = HC_STATE_RUNNING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) if (sl811->board) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) if (!device_can_wakeup(hcd->self.controller))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) device_init_wakeup(hcd->self.controller,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) sl811->board->can_wakeup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) hcd->power_budget = sl811->board->power * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) /* enable power and interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) port_power(sl811, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) /*-------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) static const struct hc_driver sl811h_hc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) .description = hcd_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) .hcd_priv_size = sizeof(struct sl811),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) * generic hardware linkage
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) .irq = sl811h_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) .flags = HCD_USB11 | HCD_MEMORY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) /* Basic lifecycle operations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) .start = sl811h_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) .stop = sl811h_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) * managing i/o requests and associated device resources
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) .urb_enqueue = sl811h_urb_enqueue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) .urb_dequeue = sl811h_urb_dequeue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) .endpoint_disable = sl811h_endpoint_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) * periodic schedule support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) .get_frame_number = sl811h_get_frame,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) * root hub support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) .hub_status_data = sl811h_hub_status_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) .hub_control = sl811h_hub_control,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) .bus_suspend = sl811h_bus_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) .bus_resume = sl811h_bus_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) /*-------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) sl811h_remove(struct platform_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) struct usb_hcd *hcd = platform_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) struct sl811 *sl811 = hcd_to_sl811(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) remove_debug_file(sl811);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) usb_remove_hcd(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) /* some platforms may use IORESOURCE_IO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) res = platform_get_resource(dev, IORESOURCE_MEM, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) if (res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) iounmap(sl811->data_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) res = platform_get_resource(dev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) if (res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) iounmap(sl811->addr_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) usb_put_hcd(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) sl811h_probe(struct platform_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) struct usb_hcd *hcd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) struct sl811 *sl811;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) struct resource *addr, *data, *ires;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) void __iomem *addr_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) void __iomem *data_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) int retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) u8 tmp, ioaddr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) unsigned long irqflags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) if (usb_disabled())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) /* basic sanity checks first. board-specific init logic should
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) * have initialized these three resources and probably board
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) * specific platform_data. we don't probe for IRQs, and do only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) * minimal sanity checking.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) ires = platform_get_resource(dev, IORESOURCE_IRQ, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) if (dev->num_resources < 3 || !ires)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) irq = ires->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) irqflags = ires->flags & IRQF_TRIGGER_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) /* the chip may be wired for either kind of addressing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) addr = platform_get_resource(dev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) data = platform_get_resource(dev, IORESOURCE_MEM, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) retval = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) if (!addr || !data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) addr = platform_get_resource(dev, IORESOURCE_IO, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) data = platform_get_resource(dev, IORESOURCE_IO, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) if (!addr || !data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) ioaddr = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) * NOTE: 64-bit resource->start is getting truncated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) * to avoid compiler warning, assuming that ->start
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) * is always 32-bit for this case
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) addr_reg = (void __iomem *) (unsigned long) addr->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) data_reg = (void __iomem *) (unsigned long) data->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) addr_reg = ioremap(addr->start, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) if (addr_reg == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) retval = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) goto err2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) data_reg = ioremap(data->start, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) if (data_reg == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) retval = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) goto err4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) /* allocate and initialize hcd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) hcd = usb_create_hcd(&sl811h_hc_driver, &dev->dev, dev_name(&dev->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) if (!hcd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) retval = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) goto err5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) hcd->rsrc_start = addr->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) sl811 = hcd_to_sl811(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) spin_lock_init(&sl811->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) INIT_LIST_HEAD(&sl811->async);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) sl811->board = dev_get_platdata(&dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) timer_setup(&sl811->timer, sl811h_timer, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) sl811->addr_reg = addr_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) sl811->data_reg = data_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) spin_lock_irq(&sl811->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) port_power(sl811, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) spin_unlock_irq(&sl811->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) msleep(200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) tmp = sl811_read(sl811, SL11H_HWREVREG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) switch (tmp >> 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) hcd->product_desc = "SL811HS v1.2";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) hcd->product_desc = "SL811HS v1.5";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) /* reject case 0, SL11S is less functional */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) dev_dbg(&dev->dev, "chiprev %02x\n", tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) retval = -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) goto err6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) /* The chip's IRQ is level triggered, active high. A requirement
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) * for platform device setup is to cope with things like signal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) * inverters (e.g. CF is active low) or working only with edge
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) * triggers (e.g. most ARM CPUs). Initial driver stress testing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) * was on a system with single edge triggering, so most sorts of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) * triggering arrangement should work.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) * Use resource IRQ flags if set by platform device setup.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) irqflags |= IRQF_SHARED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) retval = usb_add_hcd(hcd, irq, irqflags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) if (retval != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) goto err6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) device_wakeup_enable(hcd->self.controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) create_debug_file(sl811);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) err6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) usb_put_hcd(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) err5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) if (!ioaddr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) iounmap(data_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) err4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) if (!ioaddr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) iounmap(addr_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) err2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) dev_dbg(&dev->dev, "init error, %d\n", retval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) /* for this device there's no useful distinction between the controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) * and its root hub.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) sl811h_suspend(struct platform_device *dev, pm_message_t state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) struct usb_hcd *hcd = platform_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) struct sl811 *sl811 = hcd_to_sl811(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) int retval = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) switch (state.event) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) case PM_EVENT_FREEZE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) retval = sl811h_bus_suspend(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) case PM_EVENT_SUSPEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) case PM_EVENT_HIBERNATE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) case PM_EVENT_PRETHAW: /* explicitly discard hw state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) port_power(sl811, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) sl811h_resume(struct platform_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) struct usb_hcd *hcd = platform_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) struct sl811 *sl811 = hcd_to_sl811(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) /* with no "check to see if VBUS is still powered" board hook,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) * let's assume it'd only be powered to enable remote wakeup.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) if (!sl811->port1 || !device_can_wakeup(&hcd->self.root_hub->dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) sl811->port1 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) port_power(sl811, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) usb_root_hub_lost_power(hcd->self.root_hub);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) return sl811h_bus_resume(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) #define sl811h_suspend NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) #define sl811h_resume NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) /* this driver is exported so sl811_cs can depend on it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) struct platform_driver sl811h_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) .probe = sl811h_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) .remove = sl811h_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) .suspend = sl811h_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) .resume = sl811h_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) .name = hcd_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) EXPORT_SYMBOL(sl811h_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) module_platform_driver(sl811h_driver);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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