Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * R8A66597 HCD (Host Controller Driver)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2006-2007 Renesas Solutions Corp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Portions Copyright (C) 2004 Psion Teklogix (for NetBook PRO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Portions Copyright (C) 2004-2005 David Brownell
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * Portions Copyright (C) 1999 Roman Weissgaerber
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  * Author : Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #ifndef __R8A66597_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #define __R8A66597_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/usb/r8a66597.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define R8A66597_MAX_NUM_PIPE		10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define R8A66597_BUF_BSIZE		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define R8A66597_MAX_DEVICE		10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define R8A66597_MAX_ROOT_HUB		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define R8A66597_MAX_SAMPLING		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define R8A66597_RH_POLL_TIME		10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define R8A66597_MAX_DMA_CHANNEL	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define R8A66597_PIPE_NO_DMA		R8A66597_MAX_DMA_CHANNEL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define check_bulk_or_isoc(pipenum)	((pipenum >= 1 && pipenum <= 5))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define check_interrupt(pipenum)	((pipenum >= 6 && pipenum <= 9))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define make_devsel(addr)		(addr << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) struct r8a66597_pipe_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	unsigned long timer_interval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	u16 pipenum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	u16 address;	/* R8A66597 HCD usb address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	u16 epnum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	u16 maxpacket;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	u16 type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	u16 bufnum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	u16 buf_bsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	u16 interval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	u16 dir_in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) struct r8a66597_pipe {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	struct r8a66597_pipe_info info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	unsigned long fifoaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	unsigned long fifosel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	unsigned long fifoctr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	unsigned long pipectr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	unsigned long pipetre;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	unsigned long pipetrn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) struct r8a66597_td {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	struct r8a66597_pipe *pipe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	struct urb *urb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	struct list_head queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	u16 type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	u16 pipenum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	int iso_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	u16 address;		/* R8A66597's USB address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	u16 maxpacket;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	unsigned zero_packet:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	unsigned short_packet:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	unsigned set_address:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) struct r8a66597_device {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	u16	address;	/* R8A66597's USB address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	u16	hub_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	u16	root_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	unsigned short ep_in_toggle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	unsigned short ep_out_toggle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	unsigned char pipe_cnt[R8A66597_MAX_NUM_PIPE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	unsigned char dma_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	enum usb_device_state state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	struct usb_device *udev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	int usb_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	struct list_head device_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) struct r8a66597_root_hub {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	u32 port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	u16 old_syssts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	int scount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	struct r8a66597_device	*dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) struct r8a66597;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) struct r8a66597_timers {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	struct timer_list td;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	struct timer_list interval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	struct r8a66597 *r8a66597;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) struct r8a66597 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	void __iomem *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	struct r8a66597_platdata	*pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	struct r8a66597_device		device0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	struct r8a66597_root_hub	root_hub[R8A66597_MAX_ROOT_HUB];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	struct list_head		pipe_queue[R8A66597_MAX_NUM_PIPE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	struct timer_list rh_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	struct r8a66597_timers timers[R8A66597_MAX_NUM_PIPE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	unsigned short address_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	unsigned short timeout_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	unsigned short interval_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	unsigned char pipe_cnt[R8A66597_MAX_NUM_PIPE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	unsigned char dma_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	unsigned int max_root_hub;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	struct list_head child_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	unsigned long child_connect_map[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	unsigned bus_suspended:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	unsigned irq_sense_low:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static inline struct r8a66597 *hcd_to_r8a66597(struct usb_hcd *hcd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	return (struct r8a66597 *)(hcd->hcd_priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) static inline struct usb_hcd *r8a66597_to_hcd(struct r8a66597 *r8a66597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	return container_of((void *)r8a66597, struct usb_hcd, hcd_priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static inline struct r8a66597_td *r8a66597_get_td(struct r8a66597 *r8a66597,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 						  u16 pipenum)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	if (unlikely(list_empty(&r8a66597->pipe_queue[pipenum])))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 		return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	return list_entry(r8a66597->pipe_queue[pipenum].next,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 			  struct r8a66597_td, queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static inline struct urb *r8a66597_get_urb(struct r8a66597 *r8a66597,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 					   u16 pipenum)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	struct r8a66597_td *td;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	td = r8a66597_get_td(r8a66597, pipenum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	return (td ? td->urb : NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static inline u16 r8a66597_read(struct r8a66597 *r8a66597, unsigned long offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	return ioread16(r8a66597->reg + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static inline void r8a66597_read_fifo(struct r8a66597 *r8a66597,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 				      unsigned long offset, u16 *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 				      int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	void __iomem *fifoaddr = r8a66597->reg + offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	unsigned long count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	if (r8a66597->pdata->on_chip) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 		count = len / 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 		ioread32_rep(fifoaddr, buf, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 		if (len & 0x00000003) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 			unsigned long tmp = ioread32(fifoaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 			memcpy((unsigned char *)buf + count * 4, &tmp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 			       len & 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		len = (len + 1) / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 		ioread16_rep(fifoaddr, buf, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) static inline void r8a66597_write(struct r8a66597 *r8a66597, u16 val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 				  unsigned long offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	iowrite16(val, r8a66597->reg + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) static inline void r8a66597_mdfy(struct r8a66597 *r8a66597,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 				 u16 val, u16 pat, unsigned long offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	u16 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	tmp = r8a66597_read(r8a66597, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	tmp = tmp & (~pat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	tmp = tmp | val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	r8a66597_write(r8a66597, tmp, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define r8a66597_bclr(r8a66597, val, offset)	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 			r8a66597_mdfy(r8a66597, 0, val, offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define r8a66597_bset(r8a66597, val, offset)	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 			r8a66597_mdfy(r8a66597, val, 0, offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static inline void r8a66597_write_fifo(struct r8a66597 *r8a66597,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 				       struct r8a66597_pipe *pipe, u16 *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 				       int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	void __iomem *fifoaddr = r8a66597->reg + pipe->fifoaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	unsigned long count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	unsigned char *pb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	if (r8a66597->pdata->on_chip) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 		count = len / 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 		iowrite32_rep(fifoaddr, buf, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 		if (len & 0x00000003) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 			pb = (unsigned char *)buf + count * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 			for (i = 0; i < (len & 0x00000003); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 				if (r8a66597_read(r8a66597, CFIFOSEL) & BIGEND)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 					iowrite8(pb[i], fifoaddr + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 				else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 					iowrite8(pb[i], fifoaddr + 3 - i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 		int odd = len & 0x0001;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 		len = len / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 		iowrite16_rep(fifoaddr, buf, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 		if (unlikely(odd)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 			buf = &buf[len];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 			if (r8a66597->pdata->wr0_shorted_to_wr1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 				r8a66597_bclr(r8a66597, MBW_16, pipe->fifosel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 			iowrite8((unsigned char)*buf, fifoaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 			if (r8a66597->pdata->wr0_shorted_to_wr1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 				r8a66597_bset(r8a66597, MBW_16, pipe->fifosel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) static inline unsigned long get_syscfg_reg(int port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	return port == 0 ? SYSCFG0 : SYSCFG1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) static inline unsigned long get_syssts_reg(int port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	return port == 0 ? SYSSTS0 : SYSSTS1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) static inline unsigned long get_dvstctr_reg(int port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	return port == 0 ? DVSTCTR0 : DVSTCTR1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) static inline unsigned long get_dmacfg_reg(int port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	return port == 0 ? DMA0CFG : DMA1CFG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) static inline unsigned long get_intenb_reg(int port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	return port == 0 ? INTENB1 : INTENB2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) static inline unsigned long get_intsts_reg(int port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	return port == 0 ? INTSTS1 : INTSTS2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) static inline u16 get_rh_usb_speed(struct r8a66597 *r8a66597, int port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	unsigned long dvstctr_reg = get_dvstctr_reg(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	return r8a66597_read(r8a66597, dvstctr_reg) & RHST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) static inline void r8a66597_port_power(struct r8a66597 *r8a66597, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 				       int power)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	unsigned long dvstctr_reg = get_dvstctr_reg(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	if (r8a66597->pdata->port_power) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 		r8a66597->pdata->port_power(port, power);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 		if (power)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 			r8a66597_bset(r8a66597, VBOUT, dvstctr_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 			r8a66597_bclr(r8a66597, VBOUT, dvstctr_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) static inline u16 get_xtal_from_pdata(struct r8a66597_platdata *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	u16 clock = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	switch (pdata->xtal) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	case R8A66597_PLATDATA_XTAL_12MHZ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 		clock = XTAL12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	case R8A66597_PLATDATA_XTAL_24MHZ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 		clock = XTAL24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	case R8A66597_PLATDATA_XTAL_48MHZ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 		clock = XTAL48;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 		printk(KERN_ERR "r8a66597: platdata clock is wrong.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	return clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define get_pipectr_addr(pipenum)	(PIPE1CTR + (pipenum - 1) * 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define get_pipetre_addr(pipenum)	(PIPE1TRE + (pipenum - 1) * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define get_pipetrn_addr(pipenum)	(PIPE1TRN + (pipenum - 1) * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define get_devadd_addr(address)	(DEVADD0 + address * 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define enable_irq_ready(r8a66597, pipenum)	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	enable_pipe_irq(r8a66597, pipenum, BRDYENB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define disable_irq_ready(r8a66597, pipenum)	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	disable_pipe_irq(r8a66597, pipenum, BRDYENB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define enable_irq_empty(r8a66597, pipenum)	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	enable_pipe_irq(r8a66597, pipenum, BEMPENB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define disable_irq_empty(r8a66597, pipenum)	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	disable_pipe_irq(r8a66597, pipenum, BEMPENB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define enable_irq_nrdy(r8a66597, pipenum)	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	enable_pipe_irq(r8a66597, pipenum, NRDYENB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define disable_irq_nrdy(r8a66597, pipenum)	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	disable_pipe_irq(r8a66597, pipenum, NRDYENB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #endif	/* __R8A66597_H__ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)