^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * This file contains code to reset and initialize USB host controllers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Some of it includes work-arounds for PCI hardware and BIOS quirks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * It may need to run early during booting -- before USB would normally
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * initialize -- to ensure that Linux doesn't use any legacy modes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (c) 1999 Martin Mares <mj@ucw.cz>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * (and others)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/acpi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/dmi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/iopoll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "pci-quirks.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include "xhci-ext-caps.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define UHCI_USBLEGSUP 0xc0 /* legacy support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define UHCI_USBCMD 0 /* command register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define UHCI_USBINTR 4 /* interrupt register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define UHCI_USBLEGSUP_RWC 0x8f00 /* the R/WC bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define UHCI_USBLEGSUP_RO 0x5040 /* R/O and reserved bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define UHCI_USBCMD_RUN 0x0001 /* RUN/STOP bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define UHCI_USBCMD_HCRESET 0x0002 /* Host Controller reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define UHCI_USBCMD_EGSM 0x0008 /* Global Suspend Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define UHCI_USBCMD_CONFIGURE 0x0040 /* Config Flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define UHCI_USBINTR_RESUME 0x0002 /* Resume interrupt enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define OHCI_CONTROL 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define OHCI_CMDSTATUS 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define OHCI_INTRSTATUS 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define OHCI_INTRENABLE 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define OHCI_INTRDISABLE 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define OHCI_FMINTERVAL 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define OHCI_HCFS (3 << 6) /* hc functional state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define OHCI_HCR (1 << 0) /* host controller reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define OHCI_OCR (1 << 3) /* ownership change request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define OHCI_CTRL_RWC (1 << 9) /* remote wakeup connected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define OHCI_CTRL_IR (1 << 8) /* interrupt routing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define OHCI_INTR_OC (1 << 30) /* ownership change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define EHCI_HCC_PARAMS 0x08 /* extended capabilities */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define EHCI_USBCMD 0 /* command register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define EHCI_USBCMD_RUN (1 << 0) /* RUN/STOP bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define EHCI_USBSTS 4 /* status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define EHCI_USBSTS_HALTED (1 << 12) /* HCHalted bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define EHCI_USBINTR 8 /* interrupt register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define EHCI_CONFIGFLAG 0x40 /* configured flag register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define EHCI_USBLEGSUP 0 /* legacy support register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define EHCI_USBLEGSUP_BIOS (1 << 16) /* BIOS semaphore */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define EHCI_USBLEGSUP_OS (1 << 24) /* OS semaphore */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define EHCI_USBLEGCTLSTS 4 /* legacy control/status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define EHCI_USBLEGCTLSTS_SOOE (1 << 13) /* SMI on ownership change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /* AMD quirk use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define AB_REG_BAR_LOW 0xe0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define AB_REG_BAR_HIGH 0xe1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define AB_REG_BAR_SB700 0xf0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define AB_INDX(addr) ((addr) + 0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define AB_DATA(addr) ((addr) + 0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define AX_INDXC 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define AX_DATAC 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define PT_ADDR_INDX 0xE8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define PT_READ_INDX 0xE4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define PT_SIG_1_ADDR 0xA520
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define PT_SIG_2_ADDR 0xA521
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define PT_SIG_3_ADDR 0xA522
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define PT_SIG_4_ADDR 0xA523
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define PT_SIG_1_DATA 0x78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define PT_SIG_2_DATA 0x56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define PT_SIG_3_DATA 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define PT_SIG_4_DATA 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define PT4_P1_REG 0xB521
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define PT4_P2_REG 0xB522
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define PT2_P1_REG 0xD520
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define PT2_P2_REG 0xD521
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define PT1_P1_REG 0xD522
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define PT1_P2_REG 0xD523
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define NB_PCIE_INDX_ADDR 0xe0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define NB_PCIE_INDX_DATA 0xe4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define PCIE_P_CNTL 0x10040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define BIF_NB 0x10002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define NB_PIF0_PWRDOWN_0 0x01100012
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define NB_PIF0_PWRDOWN_1 0x01100013
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define USB_INTEL_XUSB2PR 0xD0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define USB_INTEL_USB2PRM 0xD4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define USB_INTEL_USB3_PSSEN 0xD8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define USB_INTEL_USB3PRM 0xDC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /* ASMEDIA quirk use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define ASMT_DATA_WRITE0_REG 0xF8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define ASMT_DATA_WRITE1_REG 0xFC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define ASMT_CONTROL_REG 0xE0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define ASMT_CONTROL_WRITE_BIT 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define ASMT_WRITEREG_CMD 0x10423
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define ASMT_FLOWCTL_ADDR 0xFA30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define ASMT_FLOWCTL_DATA 0xBA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define ASMT_PSEUDO_DATA 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * amd_chipset_gen values represent AMD different chipset generations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) enum amd_chipset_gen {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) NOT_AMD_CHIPSET = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) AMD_CHIPSET_SB600,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) AMD_CHIPSET_SB700,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) AMD_CHIPSET_SB800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) AMD_CHIPSET_HUDSON2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) AMD_CHIPSET_BOLTON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) AMD_CHIPSET_YANGTZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) AMD_CHIPSET_TAISHAN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) AMD_CHIPSET_UNKNOWN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) struct amd_chipset_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) enum amd_chipset_gen gen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) u8 rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static struct amd_chipset_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) struct pci_dev *nb_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) struct pci_dev *smbus_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) int nb_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct amd_chipset_type sb_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) int isoc_reqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) int probe_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) bool need_pll_quirk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) } amd_chipset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static DEFINE_SPINLOCK(amd_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) * amd_chipset_sb_type_init - initialize amd chipset southbridge type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) * AMD FCH/SB generation and revision is identified by SMBus controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) * vendor, device and revision IDs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) * Returns: 1 if it is an AMD chipset, 0 otherwise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static int amd_chipset_sb_type_init(struct amd_chipset_info *pinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) u8 rev = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) pinfo->sb_type.gen = AMD_CHIPSET_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) pinfo->smbus_dev = pci_get_device(PCI_VENDOR_ID_ATI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) PCI_DEVICE_ID_ATI_SBX00_SMBUS, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) if (pinfo->smbus_dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) rev = pinfo->smbus_dev->revision;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) if (rev >= 0x10 && rev <= 0x1f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) pinfo->sb_type.gen = AMD_CHIPSET_SB600;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) else if (rev >= 0x30 && rev <= 0x3f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) pinfo->sb_type.gen = AMD_CHIPSET_SB700;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) else if (rev >= 0x40 && rev <= 0x4f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) pinfo->sb_type.gen = AMD_CHIPSET_SB800;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) pinfo->smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) PCI_DEVICE_ID_AMD_HUDSON2_SMBUS, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) if (pinfo->smbus_dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) rev = pinfo->smbus_dev->revision;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) if (rev >= 0x11 && rev <= 0x14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) pinfo->sb_type.gen = AMD_CHIPSET_HUDSON2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) else if (rev >= 0x15 && rev <= 0x18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) pinfo->sb_type.gen = AMD_CHIPSET_BOLTON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) else if (rev >= 0x39 && rev <= 0x3a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) pinfo->sb_type.gen = AMD_CHIPSET_YANGTZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) pinfo->smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 0x145c, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) if (pinfo->smbus_dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) rev = pinfo->smbus_dev->revision;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) pinfo->sb_type.gen = AMD_CHIPSET_TAISHAN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) pinfo->sb_type.gen = NOT_AMD_CHIPSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) pinfo->sb_type.rev = rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) void sb800_prefetch(struct device *dev, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) u16 misc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) struct pci_dev *pdev = to_pci_dev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) pci_read_config_word(pdev, 0x50, &misc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) if (on == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) pci_write_config_word(pdev, 0x50, misc & 0xfcff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) pci_write_config_word(pdev, 0x50, misc | 0x0300);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) EXPORT_SYMBOL_GPL(sb800_prefetch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static void usb_amd_find_chipset_info(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) struct amd_chipset_info info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) info.need_pll_quirk = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) spin_lock_irqsave(&amd_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) /* probe only once */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) if (amd_chipset.probe_count > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) amd_chipset.probe_count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) spin_unlock_irqrestore(&amd_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) memset(&info, 0, sizeof(info));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) spin_unlock_irqrestore(&amd_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) if (!amd_chipset_sb_type_init(&info)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) goto commit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) switch (info.sb_type.gen) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) case AMD_CHIPSET_SB700:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) info.need_pll_quirk = info.sb_type.rev <= 0x3B;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) case AMD_CHIPSET_SB800:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) case AMD_CHIPSET_HUDSON2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) case AMD_CHIPSET_BOLTON:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) info.need_pll_quirk = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) info.need_pll_quirk = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) if (!info.need_pll_quirk) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) if (info.smbus_dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) pci_dev_put(info.smbus_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) info.smbus_dev = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) goto commit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) info.nb_dev = pci_get_device(PCI_VENDOR_ID_AMD, 0x9601, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) if (info.nb_dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) info.nb_type = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) info.nb_dev = pci_get_device(PCI_VENDOR_ID_AMD, 0x1510, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) if (info.nb_dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) info.nb_type = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) info.nb_dev = pci_get_device(PCI_VENDOR_ID_AMD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 0x9600, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) if (info.nb_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) info.nb_type = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) printk(KERN_DEBUG "QUIRK: Enable AMD PLL fix\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) commit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) spin_lock_irqsave(&amd_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) if (amd_chipset.probe_count > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) /* race - someone else was faster - drop devices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) /* Mark that we where here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) amd_chipset.probe_count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) spin_unlock_irqrestore(&amd_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) pci_dev_put(info.nb_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) pci_dev_put(info.smbus_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) /* no race - commit the result */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) info.probe_count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) amd_chipset = info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) spin_unlock_irqrestore(&amd_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) int usb_hcd_amd_remote_wakeup_quirk(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) /* Make sure amd chipset type has already been initialized */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) usb_amd_find_chipset_info();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) if (amd_chipset.sb_type.gen == AMD_CHIPSET_YANGTZE ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) amd_chipset.sb_type.gen == AMD_CHIPSET_TAISHAN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) dev_dbg(&pdev->dev, "QUIRK: Enable AMD remote wakeup fix\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) EXPORT_SYMBOL_GPL(usb_hcd_amd_remote_wakeup_quirk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) bool usb_amd_hang_symptom_quirk(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) u8 rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) usb_amd_find_chipset_info();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) rev = amd_chipset.sb_type.rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) /* SB600 and old version of SB700 have hang symptom bug */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) return amd_chipset.sb_type.gen == AMD_CHIPSET_SB600 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) (amd_chipset.sb_type.gen == AMD_CHIPSET_SB700 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) rev >= 0x3a && rev <= 0x3b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) EXPORT_SYMBOL_GPL(usb_amd_hang_symptom_quirk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) bool usb_amd_prefetch_quirk(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) usb_amd_find_chipset_info();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) /* SB800 needs pre-fetch fix */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) return amd_chipset.sb_type.gen == AMD_CHIPSET_SB800;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) EXPORT_SYMBOL_GPL(usb_amd_prefetch_quirk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) bool usb_amd_quirk_pll_check(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) usb_amd_find_chipset_info();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) return amd_chipset.need_pll_quirk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) EXPORT_SYMBOL_GPL(usb_amd_quirk_pll_check);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) * The hardware normally enables the A-link power management feature, which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) * lets the system lower the power consumption in idle states.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) * This USB quirk prevents the link going into that lower power state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) * during isochronous transfers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) * Without this quirk, isochronous stream on OHCI/EHCI/xHCI controllers of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) * some AMD platforms may stutter or have breaks occasionally.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) static void usb_amd_quirk_pll(int disable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) u32 addr, addr_low, addr_high, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) u32 bit = disable ? 0 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) spin_lock_irqsave(&amd_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) if (disable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) amd_chipset.isoc_reqs++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) if (amd_chipset.isoc_reqs > 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) spin_unlock_irqrestore(&amd_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) amd_chipset.isoc_reqs--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) if (amd_chipset.isoc_reqs > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) spin_unlock_irqrestore(&amd_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) if (amd_chipset.sb_type.gen == AMD_CHIPSET_SB800 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) amd_chipset.sb_type.gen == AMD_CHIPSET_HUDSON2 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) amd_chipset.sb_type.gen == AMD_CHIPSET_BOLTON) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) outb_p(AB_REG_BAR_LOW, 0xcd6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) addr_low = inb_p(0xcd7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) outb_p(AB_REG_BAR_HIGH, 0xcd6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) addr_high = inb_p(0xcd7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) addr = addr_high << 8 | addr_low;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) outl_p(0x30, AB_INDX(addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) outl_p(0x40, AB_DATA(addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) outl_p(0x34, AB_INDX(addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) val = inl_p(AB_DATA(addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) } else if (amd_chipset.sb_type.gen == AMD_CHIPSET_SB700 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) amd_chipset.sb_type.rev <= 0x3b) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) pci_read_config_dword(amd_chipset.smbus_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) AB_REG_BAR_SB700, &addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) outl(AX_INDXC, AB_INDX(addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) outl(0x40, AB_DATA(addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) outl(AX_DATAC, AB_INDX(addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) val = inl(AB_DATA(addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) spin_unlock_irqrestore(&amd_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) if (disable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) val &= ~0x08;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) val |= (1 << 4) | (1 << 9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) val |= 0x08;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) val &= ~((1 << 4) | (1 << 9));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) outl_p(val, AB_DATA(addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) if (!amd_chipset.nb_dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) spin_unlock_irqrestore(&amd_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) if (amd_chipset.nb_type == 1 || amd_chipset.nb_type == 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) addr = PCIE_P_CNTL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) pci_write_config_dword(amd_chipset.nb_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) NB_PCIE_INDX_ADDR, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) pci_read_config_dword(amd_chipset.nb_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) NB_PCIE_INDX_DATA, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) val &= ~(1 | (1 << 3) | (1 << 4) | (1 << 9) | (1 << 12));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) val |= bit | (bit << 3) | (bit << 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) val |= ((!bit) << 4) | ((!bit) << 9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) pci_write_config_dword(amd_chipset.nb_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) NB_PCIE_INDX_DATA, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) addr = BIF_NB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) pci_write_config_dword(amd_chipset.nb_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) NB_PCIE_INDX_ADDR, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) pci_read_config_dword(amd_chipset.nb_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) NB_PCIE_INDX_DATA, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) val &= ~(1 << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) val |= bit << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) pci_write_config_dword(amd_chipset.nb_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) NB_PCIE_INDX_DATA, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) } else if (amd_chipset.nb_type == 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) addr = NB_PIF0_PWRDOWN_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) pci_write_config_dword(amd_chipset.nb_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) NB_PCIE_INDX_ADDR, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) pci_read_config_dword(amd_chipset.nb_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) NB_PCIE_INDX_DATA, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) if (disable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) val &= ~(0x3f << 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) val |= 0x3f << 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) pci_write_config_dword(amd_chipset.nb_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) NB_PCIE_INDX_DATA, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) addr = NB_PIF0_PWRDOWN_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) pci_write_config_dword(amd_chipset.nb_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) NB_PCIE_INDX_ADDR, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) pci_read_config_dword(amd_chipset.nb_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) NB_PCIE_INDX_DATA, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) if (disable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) val &= ~(0x3f << 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) val |= 0x3f << 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) pci_write_config_dword(amd_chipset.nb_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) NB_PCIE_INDX_DATA, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) spin_unlock_irqrestore(&amd_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) void usb_amd_quirk_pll_disable(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) usb_amd_quirk_pll(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) EXPORT_SYMBOL_GPL(usb_amd_quirk_pll_disable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) static int usb_asmedia_wait_write(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) unsigned long retry_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) unsigned char value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) for (retry_count = 1000; retry_count > 0; --retry_count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) pci_read_config_byte(pdev, ASMT_CONTROL_REG, &value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) if (value == 0xff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) dev_err(&pdev->dev, "%s: check_ready ERROR", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) if ((value & ASMT_CONTROL_WRITE_BIT) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) udelay(50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) dev_warn(&pdev->dev, "%s: check_write_ready timeout", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) void usb_asmedia_modifyflowcontrol(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) if (usb_asmedia_wait_write(pdev) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) /* send command and address to device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) pci_write_config_dword(pdev, ASMT_DATA_WRITE0_REG, ASMT_WRITEREG_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) pci_write_config_dword(pdev, ASMT_DATA_WRITE1_REG, ASMT_FLOWCTL_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) pci_write_config_byte(pdev, ASMT_CONTROL_REG, ASMT_CONTROL_WRITE_BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) if (usb_asmedia_wait_write(pdev) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) /* send data to device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) pci_write_config_dword(pdev, ASMT_DATA_WRITE0_REG, ASMT_FLOWCTL_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) pci_write_config_dword(pdev, ASMT_DATA_WRITE1_REG, ASMT_PSEUDO_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) pci_write_config_byte(pdev, ASMT_CONTROL_REG, ASMT_CONTROL_WRITE_BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) EXPORT_SYMBOL_GPL(usb_asmedia_modifyflowcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) void usb_amd_quirk_pll_enable(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) usb_amd_quirk_pll(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) EXPORT_SYMBOL_GPL(usb_amd_quirk_pll_enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) void usb_amd_dev_put(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) struct pci_dev *nb, *smbus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) spin_lock_irqsave(&amd_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) amd_chipset.probe_count--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) if (amd_chipset.probe_count > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) spin_unlock_irqrestore(&amd_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) /* save them to pci_dev_put outside of spinlock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) nb = amd_chipset.nb_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) smbus = amd_chipset.smbus_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) amd_chipset.nb_dev = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) amd_chipset.smbus_dev = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) amd_chipset.nb_type = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) memset(&amd_chipset.sb_type, 0, sizeof(amd_chipset.sb_type));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) amd_chipset.isoc_reqs = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) amd_chipset.need_pll_quirk = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) spin_unlock_irqrestore(&amd_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) pci_dev_put(nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) pci_dev_put(smbus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) EXPORT_SYMBOL_GPL(usb_amd_dev_put);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) * Check if port is disabled in BIOS on AMD Promontory host.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) * BIOS Disabled ports may wake on connect/disconnect and need
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) * driver workaround to keep them disabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) * Returns true if port is marked disabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) bool usb_amd_pt_check_port(struct device *device, int port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) unsigned char value, port_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) struct pci_dev *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) u16 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) pdev = to_pci_dev(device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) pci_write_config_word(pdev, PT_ADDR_INDX, PT_SIG_1_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) pci_read_config_byte(pdev, PT_READ_INDX, &value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) if (value != PT_SIG_1_DATA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) pci_write_config_word(pdev, PT_ADDR_INDX, PT_SIG_2_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) pci_read_config_byte(pdev, PT_READ_INDX, &value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) if (value != PT_SIG_2_DATA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) pci_write_config_word(pdev, PT_ADDR_INDX, PT_SIG_3_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) pci_read_config_byte(pdev, PT_READ_INDX, &value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) if (value != PT_SIG_3_DATA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) pci_write_config_word(pdev, PT_ADDR_INDX, PT_SIG_4_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) pci_read_config_byte(pdev, PT_READ_INDX, &value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) if (value != PT_SIG_4_DATA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) /* Check disabled port setting, if bit is set port is enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) switch (pdev->device) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) case 0x43b9:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) case 0x43ba:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) * device is AMD_PROMONTORYA_4(0x43b9) or PROMONTORYA_3(0x43ba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) * PT4_P1_REG bits[7..1] represents USB2.0 ports 6 to 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) * PT4_P2_REG bits[6..0] represents ports 13 to 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) if (port > 6) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) reg = PT4_P2_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) port_shift = port - 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) reg = PT4_P1_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) port_shift = port + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) case 0x43bb:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) * device is AMD_PROMONTORYA_2(0x43bb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) * PT2_P1_REG bits[7..5] represents USB2.0 ports 2 to 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) * PT2_P2_REG bits[5..0] represents ports 9 to 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) if (port > 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) reg = PT2_P2_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) port_shift = port - 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) reg = PT2_P1_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) port_shift = port + 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) case 0x43bc:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) * device is AMD_PROMONTORYA_1(0x43bc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) * PT1_P1_REG[7..4] represents USB2.0 ports 3 to 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) * PT1_P2_REG[5..0] represents ports 9 to 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) if (port > 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) reg = PT1_P2_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) port_shift = port - 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) reg = PT1_P1_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) port_shift = port + 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) pci_write_config_word(pdev, PT_ADDR_INDX, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) pci_read_config_byte(pdev, PT_READ_INDX, &value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) return !(value & BIT(port_shift));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) EXPORT_SYMBOL_GPL(usb_amd_pt_check_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) * Make sure the controller is completely inactive, unable to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) * generate interrupts or do DMA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) void uhci_reset_hc(struct pci_dev *pdev, unsigned long base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) /* Turn off PIRQ enable and SMI enable. (This also turns off the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) * BIOS's USB Legacy Support.) Turn off all the R/WC bits too.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) pci_write_config_word(pdev, UHCI_USBLEGSUP, UHCI_USBLEGSUP_RWC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) /* Reset the HC - this will force us to get a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) * new notification of any already connected
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) * ports due to the virtual disconnect that it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) * implies.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) outw(UHCI_USBCMD_HCRESET, base + UHCI_USBCMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) udelay(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) if (inw(base + UHCI_USBCMD) & UHCI_USBCMD_HCRESET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) dev_warn(&pdev->dev, "HCRESET not completed yet!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) /* Just to be safe, disable interrupt requests and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) * make sure the controller is stopped.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) outw(0, base + UHCI_USBINTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) outw(0, base + UHCI_USBCMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) EXPORT_SYMBOL_GPL(uhci_reset_hc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) * Initialize a controller that was newly discovered or has just been
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) * resumed. In either case we can't be sure of its previous state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) * Returns: 1 if the controller was reset, 0 otherwise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) int uhci_check_and_reset_hc(struct pci_dev *pdev, unsigned long base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) u16 legsup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) unsigned int cmd, intr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) * When restarting a suspended controller, we expect all the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) * settings to be the same as we left them:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) * PIRQ and SMI disabled, no R/W bits set in USBLEGSUP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) * Controller is stopped and configured with EGSM set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) * No interrupts enabled except possibly Resume Detect.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) * If any of these conditions are violated we do a complete reset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) pci_read_config_word(pdev, UHCI_USBLEGSUP, &legsup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) if (legsup & ~(UHCI_USBLEGSUP_RO | UHCI_USBLEGSUP_RWC)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) dev_dbg(&pdev->dev, "%s: legsup = 0x%04x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) __func__, legsup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) goto reset_needed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) cmd = inw(base + UHCI_USBCMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) if ((cmd & UHCI_USBCMD_RUN) || !(cmd & UHCI_USBCMD_CONFIGURE) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) !(cmd & UHCI_USBCMD_EGSM)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) dev_dbg(&pdev->dev, "%s: cmd = 0x%04x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) __func__, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) goto reset_needed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) intr = inw(base + UHCI_USBINTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) if (intr & (~UHCI_USBINTR_RESUME)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) dev_dbg(&pdev->dev, "%s: intr = 0x%04x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) __func__, intr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) goto reset_needed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) reset_needed:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) dev_dbg(&pdev->dev, "Performing full reset\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) uhci_reset_hc(pdev, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) EXPORT_SYMBOL_GPL(uhci_check_and_reset_hc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) static inline int io_type_enabled(struct pci_dev *pdev, unsigned int mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) u16 cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) return !pci_read_config_word(pdev, PCI_COMMAND, &cmd) && (cmd & mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) #define pio_enabled(dev) io_type_enabled(dev, PCI_COMMAND_IO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) #define mmio_enabled(dev) io_type_enabled(dev, PCI_COMMAND_MEMORY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) static void quirk_usb_handoff_uhci(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) unsigned long base = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) if (!pio_enabled(pdev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) for (i = 0; i < PCI_STD_NUM_BARS; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) if ((pci_resource_flags(pdev, i) & IORESOURCE_IO)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) base = pci_resource_start(pdev, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) if (base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) uhci_check_and_reset_hc(pdev, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) static int mmio_resource_enabled(struct pci_dev *pdev, int idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) return pci_resource_start(pdev, idx) && mmio_enabled(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) static void quirk_usb_handoff_ohci(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) u32 control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) u32 fminterval = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) bool no_fminterval = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) int cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) if (!mmio_resource_enabled(pdev, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) base = pci_ioremap_bar(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) if (base == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) * ULi M5237 OHCI controller locks the whole system when accessing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) * the OHCI_FMINTERVAL offset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) if (pdev->vendor == PCI_VENDOR_ID_AL && pdev->device == 0x5237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) no_fminterval = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) control = readl(base + OHCI_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) /* On PA-RISC, PDC can leave IR set incorrectly; ignore it there. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) #ifdef __hppa__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) #define OHCI_CTRL_MASK (OHCI_CTRL_RWC | OHCI_CTRL_IR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) #define OHCI_CTRL_MASK OHCI_CTRL_RWC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) if (control & OHCI_CTRL_IR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) int wait_time = 500; /* arbitrary; 5 seconds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) writel(OHCI_INTR_OC, base + OHCI_INTRENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) writel(OHCI_OCR, base + OHCI_CMDSTATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) while (wait_time > 0 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) readl(base + OHCI_CONTROL) & OHCI_CTRL_IR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) wait_time -= 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) msleep(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) if (wait_time <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) dev_warn(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) "OHCI: BIOS handoff failed (BIOS bug?) %08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) readl(base + OHCI_CONTROL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) /* disable interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) writel((u32) ~0, base + OHCI_INTRDISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) /* Go into the USB_RESET state, preserving RWC (and possibly IR) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) writel(control & OHCI_CTRL_MASK, base + OHCI_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) readl(base + OHCI_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) /* software reset of the controller, preserving HcFmInterval */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) if (!no_fminterval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) fminterval = readl(base + OHCI_FMINTERVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) writel(OHCI_HCR, base + OHCI_CMDSTATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) /* reset requires max 10 us delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) for (cnt = 30; cnt > 0; --cnt) { /* ... allow extra time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) if ((readl(base + OHCI_CMDSTATUS) & OHCI_HCR) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) if (!no_fminterval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) writel(fminterval, base + OHCI_FMINTERVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) /* Now the controller is safely in SUSPEND and nothing can wake it up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) iounmap(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) static const struct dmi_system_id ehci_dmi_nohandoff_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) /* Pegatron Lucid (ExoPC) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) .matches = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) DMI_MATCH(DMI_BOARD_NAME, "EXOPG06411"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) DMI_MATCH(DMI_BIOS_VERSION, "Lucid-CE-133"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) /* Pegatron Lucid (Ordissimo AIRIS) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) .matches = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) DMI_MATCH(DMI_BOARD_NAME, "M11JB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) DMI_MATCH(DMI_BIOS_VERSION, "Lucid-"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) /* Pegatron Lucid (Ordissimo) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) .matches = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) DMI_MATCH(DMI_BOARD_NAME, "Ordissimo"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) DMI_MATCH(DMI_BIOS_VERSION, "Lucid-"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) /* HASEE E200 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) .matches = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) DMI_MATCH(DMI_BOARD_VENDOR, "HASEE"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) DMI_MATCH(DMI_BOARD_NAME, "E210"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) DMI_MATCH(DMI_BIOS_VERSION, "6.00"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) static void ehci_bios_handoff(struct pci_dev *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) void __iomem *op_reg_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) u32 cap, u8 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) int try_handoff = 1, tried_handoff = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) * The Pegatron Lucid tablet sporadically waits for 98 seconds trying
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) * the handoff on its unused controller. Skip it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) * The HASEE E200 hangs when the semaphore is set (bugzilla #77021).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) if (pdev->vendor == 0x8086 && (pdev->device == 0x283a ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) pdev->device == 0x27cc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) if (dmi_check_system(ehci_dmi_nohandoff_table))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) try_handoff = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) if (try_handoff && (cap & EHCI_USBLEGSUP_BIOS)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) dev_dbg(&pdev->dev, "EHCI: BIOS handoff\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) /* aleksey_gorelov@phoenix.com reports that some systems need SMI forced on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) * but that seems dubious in general (the BIOS left it off intentionally)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) * and is known to prevent some systems from booting. so we won't do this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) * unless maybe we can determine when we're on a system that needs SMI forced.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) /* BIOS workaround (?): be sure the pre-Linux code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) * receives the SMI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) pci_read_config_dword(pdev, offset + EHCI_USBLEGCTLSTS, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) pci_write_config_dword(pdev, offset + EHCI_USBLEGCTLSTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) val | EHCI_USBLEGCTLSTS_SOOE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) /* some systems get upset if this semaphore is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) * set for any other reason than forcing a BIOS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) * handoff..
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) pci_write_config_byte(pdev, offset + 3, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) /* if boot firmware now owns EHCI, spin till it hands it over. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) if (try_handoff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) int msec = 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) while ((cap & EHCI_USBLEGSUP_BIOS) && (msec > 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) tried_handoff = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) msleep(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) msec -= 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) pci_read_config_dword(pdev, offset, &cap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) if (cap & EHCI_USBLEGSUP_BIOS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) /* well, possibly buggy BIOS... try to shut it down,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) * and hope nothing goes too wrong
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) if (try_handoff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) dev_warn(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) "EHCI: BIOS handoff failed (BIOS bug?) %08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) cap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) pci_write_config_byte(pdev, offset + 2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) /* just in case, always disable EHCI SMIs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) pci_write_config_dword(pdev, offset + EHCI_USBLEGCTLSTS, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) /* If the BIOS ever owned the controller then we can't expect
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) * any power sessions to remain intact.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) if (tried_handoff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) writel(0, op_reg_base + EHCI_CONFIGFLAG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) static void quirk_usb_disable_ehci(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) void __iomem *base, *op_reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) u32 hcc_params, cap, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) u8 offset, cap_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) int wait_time, count = 256/4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) if (!mmio_resource_enabled(pdev, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) base = pci_ioremap_bar(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) if (base == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) cap_length = readb(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) op_reg_base = base + cap_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) /* EHCI 0.96 and later may have "extended capabilities"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) * spec section 5.1 explains the bios handoff, e.g. for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) * booting from USB disk or using a usb keyboard
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) hcc_params = readl(base + EHCI_HCC_PARAMS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) offset = (hcc_params >> 8) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) while (offset && --count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) pci_read_config_dword(pdev, offset, &cap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) switch (cap & 0xff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) ehci_bios_handoff(pdev, op_reg_base, cap, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) case 0: /* Illegal reserved cap, set cap=0 so we exit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) cap = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) dev_warn(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) "EHCI: unrecognized capability %02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) cap & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) offset = (cap >> 8) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) if (!count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) dev_printk(KERN_DEBUG, &pdev->dev, "EHCI: capability loop?\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) * halt EHCI & disable its interrupts in any case
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) val = readl(op_reg_base + EHCI_USBSTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) if ((val & EHCI_USBSTS_HALTED) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) val = readl(op_reg_base + EHCI_USBCMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) val &= ~EHCI_USBCMD_RUN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) writel(val, op_reg_base + EHCI_USBCMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) wait_time = 2000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) writel(0x3f, op_reg_base + EHCI_USBSTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) wait_time -= 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) val = readl(op_reg_base + EHCI_USBSTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) if ((val == ~(u32)0) || (val & EHCI_USBSTS_HALTED)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) } while (wait_time > 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) writel(0, op_reg_base + EHCI_USBINTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) writel(0x3f, op_reg_base + EHCI_USBSTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) iounmap(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) * handshake - spin reading a register until handshake completes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) * @ptr: address of hc register to be read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) * @mask: bits to look at in result of read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) * @done: value of those bits when handshake succeeds
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) * @wait_usec: timeout in microseconds
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) * @delay_usec: delay in microseconds to wait between polling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) * Polls a register every delay_usec microseconds.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) * Returns 0 when the mask bits have the value done.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) * Returns -ETIMEDOUT if this condition is not true after
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) * wait_usec microseconds have passed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) static int handshake(void __iomem *ptr, u32 mask, u32 done,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) int wait_usec, int delay_usec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) u32 result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) return readl_poll_timeout_atomic(ptr, result,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) ((result & mask) == done),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) delay_usec, wait_usec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) * Intel's Panther Point chipset has two host controllers (EHCI and xHCI) that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) * share some number of ports. These ports can be switched between either
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) * controller. Not all of the ports under the EHCI host controller may be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) * switchable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) * The ports should be switched over to xHCI before PCI probes for any device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) * start. This avoids active devices under EHCI being disconnected during the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) * port switchover, which could cause loss of data on USB storage devices, or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) * failed boot when the root file system is on a USB mass storage device and is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) * enumerated under EHCI first.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) * We write into the xHC's PCI configuration space in some Intel-specific
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) * registers to switch the ports over. The USB 3.0 terminations and the USB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) * 2.0 data wires are switched separately. We want to enable the SuperSpeed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) * terminations before switching the USB 2.0 wires over, so that USB 3.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) * devices connect at SuperSpeed, rather than at USB 2.0 speeds.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) void usb_enable_intel_xhci_ports(struct pci_dev *xhci_pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) u32 ports_available;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) bool ehci_found = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) struct pci_dev *companion = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) /* Sony VAIO t-series with subsystem device ID 90a8 is not capable of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) * switching ports from EHCI to xHCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) if (xhci_pdev->subsystem_vendor == PCI_VENDOR_ID_SONY &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) xhci_pdev->subsystem_device == 0x90a8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) /* make sure an intel EHCI controller exists */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) for_each_pci_dev(companion) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) if (companion->class == PCI_CLASS_SERIAL_USB_EHCI &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) companion->vendor == PCI_VENDOR_ID_INTEL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) ehci_found = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) if (!ehci_found)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) /* Don't switchover the ports if the user hasn't compiled the xHCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) * driver. Otherwise they will see "dead" USB ports that don't power
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) * the devices.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) if (!IS_ENABLED(CONFIG_USB_XHCI_HCD)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) dev_warn(&xhci_pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) "CONFIG_USB_XHCI_HCD is turned off, defaulting to EHCI.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) dev_warn(&xhci_pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) "USB 3.0 devices will work at USB 2.0 speeds.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) usb_disable_xhci_ports(xhci_pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) /* Read USB3PRM, the USB 3.0 Port Routing Mask Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) * Indicate the ports that can be changed from OS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) pci_read_config_dword(xhci_pdev, USB_INTEL_USB3PRM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) &ports_available);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) dev_dbg(&xhci_pdev->dev, "Configurable ports to enable SuperSpeed: 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) ports_available);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) /* Write USB3_PSSEN, the USB 3.0 Port SuperSpeed Enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) * Register, to turn on SuperSpeed terminations for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) * switchable ports.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) pci_write_config_dword(xhci_pdev, USB_INTEL_USB3_PSSEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) ports_available);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) pci_read_config_dword(xhci_pdev, USB_INTEL_USB3_PSSEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) &ports_available);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) dev_dbg(&xhci_pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) "USB 3.0 ports that are now enabled under xHCI: 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) ports_available);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) /* Read XUSB2PRM, xHCI USB 2.0 Port Routing Mask Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) * Indicate the USB 2.0 ports to be controlled by the xHCI host.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) pci_read_config_dword(xhci_pdev, USB_INTEL_USB2PRM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) &ports_available);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) dev_dbg(&xhci_pdev->dev, "Configurable USB 2.0 ports to hand over to xCHI: 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) ports_available);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) /* Write XUSB2PR, the xHC USB 2.0 Port Routing Register, to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) * switch the USB 2.0 power and data lines over to the xHCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) * host.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) pci_write_config_dword(xhci_pdev, USB_INTEL_XUSB2PR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) ports_available);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) pci_read_config_dword(xhci_pdev, USB_INTEL_XUSB2PR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) &ports_available);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) dev_dbg(&xhci_pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) "USB 2.0 ports that are now switched over to xHCI: 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) ports_available);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) EXPORT_SYMBOL_GPL(usb_enable_intel_xhci_ports);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) void usb_disable_xhci_ports(struct pci_dev *xhci_pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) pci_write_config_dword(xhci_pdev, USB_INTEL_USB3_PSSEN, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) pci_write_config_dword(xhci_pdev, USB_INTEL_XUSB2PR, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) EXPORT_SYMBOL_GPL(usb_disable_xhci_ports);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) * PCI Quirks for xHCI.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) * Takes care of the handoff between the Pre-OS (i.e. BIOS) and the OS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) * It signals to the BIOS that the OS wants control of the host controller,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) * and then waits 1 second for the BIOS to hand over control.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) * If we timeout, assume the BIOS is broken and take control anyway.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) static void quirk_usb_handoff_xhci(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) int ext_cap_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) void __iomem *op_reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) int timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) int len = pci_resource_len(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) if (!mmio_resource_enabled(pdev, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) base = ioremap(pci_resource_start(pdev, 0), len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) if (base == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) * Find the Legacy Support Capability register -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) * this is optional for xHCI host controllers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) ext_cap_offset = xhci_find_next_ext_cap(base, 0, XHCI_EXT_CAPS_LEGACY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) if (!ext_cap_offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) goto hc_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) if ((ext_cap_offset + sizeof(val)) > len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) /* We're reading garbage from the controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) dev_warn(&pdev->dev, "xHCI controller failing to respond");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) goto iounmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) val = readl(base + ext_cap_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) /* Auto handoff never worked for these devices. Force it and continue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) if ((pdev->vendor == PCI_VENDOR_ID_TI && pdev->device == 0x8241) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) (pdev->vendor == PCI_VENDOR_ID_RENESAS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) && pdev->device == 0x0014)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) val = (val | XHCI_HC_OS_OWNED) & ~XHCI_HC_BIOS_OWNED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) writel(val, base + ext_cap_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) /* If the BIOS owns the HC, signal that the OS wants it, and wait */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) if (val & XHCI_HC_BIOS_OWNED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) writel(val | XHCI_HC_OS_OWNED, base + ext_cap_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) /* Wait for 1 second with 10 microsecond polling interval */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) timeout = handshake(base + ext_cap_offset, XHCI_HC_BIOS_OWNED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) 0, 1000000, 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) /* Assume a buggy BIOS and take HC ownership anyway */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) if (timeout) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) dev_warn(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) "xHCI BIOS handoff failed (BIOS bug ?) %08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) writel(val & ~XHCI_HC_BIOS_OWNED, base + ext_cap_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) val = readl(base + ext_cap_offset + XHCI_LEGACY_CONTROL_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) /* Mask off (turn off) any enabled SMIs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) val &= XHCI_LEGACY_DISABLE_SMI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) /* Mask all SMI events bits, RW1C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) val |= XHCI_LEGACY_SMI_EVENTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) /* Disable any BIOS SMIs and clear all SMI events*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) writel(val, base + ext_cap_offset + XHCI_LEGACY_CONTROL_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) hc_init:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) if (pdev->vendor == PCI_VENDOR_ID_INTEL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) usb_enable_intel_xhci_ports(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) op_reg_base = base + XHCI_HC_LENGTH(readl(base));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) /* Wait for the host controller to be ready before writing any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) * operational or runtime registers. Wait 5 seconds and no more.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) timeout = handshake(op_reg_base + XHCI_STS_OFFSET, XHCI_STS_CNR, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) 5000000, 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) /* Assume a buggy HC and start HC initialization anyway */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) if (timeout) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) val = readl(op_reg_base + XHCI_STS_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) dev_warn(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) "xHCI HW not ready after 5 sec (HC bug?) status = 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) /* Send the halt and disable interrupts command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) val = readl(op_reg_base + XHCI_CMD_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) val &= ~(XHCI_CMD_RUN | XHCI_IRQS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) writel(val, op_reg_base + XHCI_CMD_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) /* Wait for the HC to halt - poll every 125 usec (one microframe). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) timeout = handshake(op_reg_base + XHCI_STS_OFFSET, XHCI_STS_HALT, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) XHCI_MAX_HALT_USEC, 125);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) if (timeout) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) val = readl(op_reg_base + XHCI_STS_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) dev_warn(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) "xHCI HW did not halt within %d usec status = 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) XHCI_MAX_HALT_USEC, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) iounmap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) iounmap(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) static void quirk_usb_early_handoff(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) struct device_node *parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) bool is_rpi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) /* Skip Netlogic mips SoC's internal PCI USB controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) * This device does not need/support EHCI/OHCI handoff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) if (pdev->vendor == 0x184e) /* vendor Netlogic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) * Bypass the Raspberry Pi 4 controller xHCI controller, things are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) * taken care of by the board's co-processor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) if (pdev->vendor == PCI_VENDOR_ID_VIA && pdev->device == 0x3483) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) parent = of_get_parent(pdev->bus->dev.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) is_rpi = of_device_is_compatible(parent, "brcm,bcm2711-pcie");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) of_node_put(parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) if (is_rpi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) if (pdev->class != PCI_CLASS_SERIAL_USB_UHCI &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) pdev->class != PCI_CLASS_SERIAL_USB_OHCI &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) pdev->class != PCI_CLASS_SERIAL_USB_EHCI &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) pdev->class != PCI_CLASS_SERIAL_USB_XHCI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) if (pci_enable_device(pdev) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) dev_warn(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) "Can't enable PCI device, BIOS handoff failed.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) if (pdev->class == PCI_CLASS_SERIAL_USB_UHCI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) quirk_usb_handoff_uhci(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) else if (pdev->class == PCI_CLASS_SERIAL_USB_OHCI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) quirk_usb_handoff_ohci(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) else if (pdev->class == PCI_CLASS_SERIAL_USB_EHCI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) quirk_usb_disable_ehci(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) else if (pdev->class == PCI_CLASS_SERIAL_USB_XHCI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) quirk_usb_handoff_xhci(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) pci_disable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) PCI_CLASS_SERIAL_USB, 8, quirk_usb_early_handoff);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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