^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * OHCI HCD(Host Controller Driver) for USB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *(C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *(C) Copyright 2000-2002 David Brownell <dbrownell@users.sourceforge.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *(C) Copyright 2002 Hewlett-Packard Company
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Bus glue for Toshiba Mobile IO(TMIO) Controller's OHCI core
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * (C) Copyright 2005 Chris Humbert <mahadri-usb@drigon.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * (C) Copyright 2007, 2008 Dmitry Baryshkov <dbaryshkov@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * This is known to work with the following variants:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * TC6393XB revision 3 (32kB SRAM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * The TMIO's OHCI core DMAs through a small internal buffer that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * is directly addressable by the CPU.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * Written from sparse documentation from Toshiba and Sharp's driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * for the 2.4 kernel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * usb-ohci-tc6393.c(C) Copyright 2004 Lineo Solutions, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /*#include <linux/fs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/mount.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/pagemap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/namei.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/sched.h>*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/mfd/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/mfd/tmio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /*-------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * USB Host Controller Configuration Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define CCR_REVID 0x08 /* b Revision ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define CCR_BASE 0x10 /* l USB Control Register Base Address Low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define CCR_ILME 0x40 /* b Internal Local Memory Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define CCR_PM 0x4c /* w Power Management */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define CCR_INTC 0x50 /* b INT Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define CCR_LMW1L 0x54 /* w Local Memory Window 1 LMADRS Low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define CCR_LMW1H 0x56 /* w Local Memory Window 1 LMADRS High */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define CCR_LMW1BL 0x58 /* w Local Memory Window 1 Base Address Low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define CCR_LMW1BH 0x5A /* w Local Memory Window 1 Base Address High */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define CCR_LMW2L 0x5C /* w Local Memory Window 2 LMADRS Low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define CCR_LMW2H 0x5E /* w Local Memory Window 2 LMADRS High */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define CCR_LMW2BL 0x60 /* w Local Memory Window 2 Base Address Low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define CCR_LMW2BH 0x62 /* w Local Memory Window 2 Base Address High */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define CCR_MISC 0xFC /* b MISC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define CCR_PM_GKEN 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define CCR_PM_CKRNEN 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define CCR_PM_USBPW1 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define CCR_PM_USBPW2 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define CCR_PM_USBPW3 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define CCR_PM_PMEE 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define CCR_PM_PMES 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /*-------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) struct tmio_hcd {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) void __iomem *ccr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) spinlock_t lock; /* protects RMW cycles */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define hcd_to_tmio(hcd) ((struct tmio_hcd *)(hcd_to_ohci(hcd) + 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /*-------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) static void tmio_write_pm(struct platform_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct usb_hcd *hcd = platform_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct tmio_hcd *tmio = hcd_to_tmio(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) u16 pm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) spin_lock_irqsave(&tmio->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) pm = CCR_PM_GKEN | CCR_PM_CKRNEN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) CCR_PM_PMEE | CCR_PM_PMES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) tmio_iowrite16(pm, tmio->ccr + CCR_PM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) spin_unlock_irqrestore(&tmio->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static void tmio_stop_hc(struct platform_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) struct usb_hcd *hcd = platform_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) struct ohci_hcd *ohci = hcd_to_ohci(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) struct tmio_hcd *tmio = hcd_to_tmio(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) u16 pm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) pm = CCR_PM_GKEN | CCR_PM_CKRNEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) switch (ohci->num_ports) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) dev_err(&dev->dev, "Unsupported amount of ports: %d\n", ohci->num_ports);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) pm |= CCR_PM_USBPW3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) pm |= CCR_PM_USBPW2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) pm |= CCR_PM_USBPW1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) tmio_iowrite8(0, tmio->ccr + CCR_INTC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) tmio_iowrite8(0, tmio->ccr + CCR_ILME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) tmio_iowrite16(0, tmio->ccr + CCR_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) tmio_iowrite16(0, tmio->ccr + CCR_BASE + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) tmio_iowrite16(pm, tmio->ccr + CCR_PM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static void tmio_start_hc(struct platform_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) struct usb_hcd *hcd = platform_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) struct tmio_hcd *tmio = hcd_to_tmio(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) unsigned long base = hcd->rsrc_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) tmio_write_pm(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) tmio_iowrite16(base, tmio->ccr + CCR_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) tmio_iowrite16(base >> 16, tmio->ccr + CCR_BASE + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) tmio_iowrite8(1, tmio->ccr + CCR_ILME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) tmio_iowrite8(2, tmio->ccr + CCR_INTC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) dev_info(&dev->dev, "revision %d @ 0x%08llx, irq %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) tmio_ioread8(tmio->ccr + CCR_REVID),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) (u64) hcd->rsrc_start, hcd->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static int ohci_tmio_start(struct usb_hcd *hcd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) struct ohci_hcd *ohci = hcd_to_ohci(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) if ((ret = ohci_init(ohci)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) if ((ret = ohci_run(ohci)) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) dev_err(hcd->self.controller, "can't start %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) hcd->self.bus_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) ohci_stop(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static const struct hc_driver ohci_tmio_hc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .description = hcd_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .product_desc = "TMIO OHCI USB Host Controller",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .hcd_priv_size = sizeof(struct ohci_hcd) + sizeof (struct tmio_hcd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /* generic hardware linkage */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .irq = ohci_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) .flags = HCD_USB11 | HCD_MEMORY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /* basic lifecycle operations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) .start = ohci_tmio_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .stop = ohci_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) .shutdown = ohci_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) /* managing i/o requests and associated device resources */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) .urb_enqueue = ohci_urb_enqueue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) .urb_dequeue = ohci_urb_dequeue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) .endpoint_disable = ohci_endpoint_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /* scheduling support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) .get_frame_number = ohci_get_frame,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) /* root hub support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) .hub_status_data = ohci_hub_status_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) .hub_control = ohci_hub_control,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) .bus_suspend = ohci_bus_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) .bus_resume = ohci_bus_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) .start_port_reset = ohci_start_port_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) /*-------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) static struct platform_driver ohci_hcd_tmio_driver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) static int ohci_hcd_tmio_drv_probe(struct platform_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) const struct mfd_cell *cell = mfd_get_cell(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) struct resource *regs = platform_get_resource(dev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) struct resource *config = platform_get_resource(dev, IORESOURCE_MEM, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) struct resource *sram = platform_get_resource(dev, IORESOURCE_MEM, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) int irq = platform_get_irq(dev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) struct tmio_hcd *tmio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) struct ohci_hcd *ohci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) struct usb_hcd *hcd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) if (usb_disabled())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) if (!cell || !regs || !config || !sram)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) if (irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) hcd = usb_create_hcd(&ohci_tmio_hc_driver, &dev->dev, dev_name(&dev->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) if (!hcd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) goto err_usb_create_hcd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) hcd->rsrc_start = regs->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) hcd->rsrc_len = resource_size(regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) tmio = hcd_to_tmio(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) spin_lock_init(&tmio->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) tmio->ccr = ioremap(config->start, resource_size(config));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) if (!tmio->ccr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) goto err_ioremap_ccr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) if (!hcd->regs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) goto err_ioremap_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) if (cell->enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) ret = cell->enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) goto err_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) tmio_start_hc(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) ohci = hcd_to_ohci(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) ohci_hcd_init(ohci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) ret = usb_hcd_setup_local_mem(hcd, sram->start, sram->start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) resource_size(sram));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) goto err_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) ret = usb_add_hcd(hcd, irq, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) goto err_add_hcd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) device_wakeup_enable(hcd->self.controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) if (ret == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) usb_remove_hcd(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) err_add_hcd:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) tmio_stop_hc(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) if (cell->disable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) cell->disable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) err_enable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) iounmap(hcd->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) err_ioremap_regs:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) iounmap(tmio->ccr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) err_ioremap_ccr:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) usb_put_hcd(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) err_usb_create_hcd:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) static int ohci_hcd_tmio_drv_remove(struct platform_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) struct usb_hcd *hcd = platform_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) struct tmio_hcd *tmio = hcd_to_tmio(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) const struct mfd_cell *cell = mfd_get_cell(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) usb_remove_hcd(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) tmio_stop_hc(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) if (cell->disable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) cell->disable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) iounmap(hcd->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) iounmap(tmio->ccr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) usb_put_hcd(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) static int ohci_hcd_tmio_drv_suspend(struct platform_device *dev, pm_message_t state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) const struct mfd_cell *cell = mfd_get_cell(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) struct usb_hcd *hcd = platform_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) struct ohci_hcd *ohci = hcd_to_ohci(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) struct tmio_hcd *tmio = hcd_to_tmio(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) u8 misc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) if (time_before(jiffies, ohci->next_statechange))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) msleep(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) ohci->next_statechange = jiffies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) spin_lock_irqsave(&tmio->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) misc = tmio_ioread8(tmio->ccr + CCR_MISC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) misc |= 1 << 3; /* USSUSP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) tmio_iowrite8(misc, tmio->ccr + CCR_MISC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) spin_unlock_irqrestore(&tmio->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) if (cell->suspend) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) ret = cell->suspend(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) static int ohci_hcd_tmio_drv_resume(struct platform_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) const struct mfd_cell *cell = mfd_get_cell(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) struct usb_hcd *hcd = platform_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) struct ohci_hcd *ohci = hcd_to_ohci(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) struct tmio_hcd *tmio = hcd_to_tmio(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) u8 misc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) if (time_before(jiffies, ohci->next_statechange))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) msleep(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) ohci->next_statechange = jiffies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) if (cell->resume) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) ret = cell->resume(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) tmio_start_hc(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) spin_lock_irqsave(&tmio->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) misc = tmio_ioread8(tmio->ccr + CCR_MISC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) misc &= ~(1 << 3); /* USSUSP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) tmio_iowrite8(misc, tmio->ccr + CCR_MISC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) spin_unlock_irqrestore(&tmio->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) ohci_resume(hcd, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define ohci_hcd_tmio_drv_suspend NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define ohci_hcd_tmio_drv_resume NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) static struct platform_driver ohci_hcd_tmio_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) .probe = ohci_hcd_tmio_drv_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) .remove = ohci_hcd_tmio_drv_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) .shutdown = usb_hcd_platform_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) .suspend = ohci_hcd_tmio_drv_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) .resume = ohci_hcd_tmio_drv_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) .name = "tmio-ohci",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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