^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-1.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * OHCI HCD (Host Controller Driver) for USB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * (C) Copyright 2000-2002 David Brownell <dbrownell@users.sourceforge.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * (C) Copyright 2002 Hewlett-Packard Company
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Bus Glue for pxa27x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Written by Christopher Hoover <ch@hpl.hp.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Based on fragments of previous driver by Russell King et al.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * Modified for LH7A404 from ohci-sa1111.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * by Durgesh Pattamatta <pattamattad@sharpsec.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * Modified for pxa27x from ohci-lh7a404.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * by Nick Bane <nick@cecomputing.co.uk> 26-8-2004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * This file is licenced under the GPL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/of_gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/platform_data/usb-ohci-pxa27x.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/platform_data/usb-pxa3xx-ulpi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <linux/signal.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <linux/usb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <linux/usb/hcd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <linux/usb/otg.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include <mach/hardware.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #include "ohci.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define DRIVER_DESC "OHCI PXA27x/PXA3x driver"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * UHC: USB Host Controller (OHCI-like) register definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define UHCREV (0x0000) /* UHC HCI Spec Revision */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define UHCHCON (0x0004) /* UHC Host Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define UHCCOMS (0x0008) /* UHC Command Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define UHCINTS (0x000C) /* UHC Interrupt Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define UHCINTE (0x0010) /* UHC Interrupt Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define UHCINTD (0x0014) /* UHC Interrupt Disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define UHCHCCA (0x0018) /* UHC Host Controller Comm. Area */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define UHCPCED (0x001C) /* UHC Period Current Endpt Descr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define UHCCHED (0x0020) /* UHC Control Head Endpt Descr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define UHCCCED (0x0024) /* UHC Control Current Endpt Descr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define UHCBHED (0x0028) /* UHC Bulk Head Endpt Descr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define UHCBCED (0x002C) /* UHC Bulk Current Endpt Descr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define UHCDHEAD (0x0030) /* UHC Done Head */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define UHCFMI (0x0034) /* UHC Frame Interval */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define UHCFMR (0x0038) /* UHC Frame Remaining */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define UHCFMN (0x003C) /* UHC Frame Number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define UHCPERS (0x0040) /* UHC Periodic Start */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define UHCLS (0x0044) /* UHC Low Speed Threshold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define UHCRHDA (0x0048) /* UHC Root Hub Descriptor A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define UHCRHDA_NOCP (1 << 12) /* No over current protection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define UHCRHDA_OCPM (1 << 11) /* Over Current Protection Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define UHCRHDA_POTPGT(x) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) (((x) & 0xff) << 24) /* Power On To Power Good Time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define UHCRHDB (0x004C) /* UHC Root Hub Descriptor B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define UHCRHS (0x0050) /* UHC Root Hub Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define UHCRHPS1 (0x0054) /* UHC Root Hub Port 1 Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define UHCRHPS2 (0x0058) /* UHC Root Hub Port 2 Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define UHCRHPS3 (0x005C) /* UHC Root Hub Port 3 Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define UHCSTAT (0x0060) /* UHC Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define UHCSTAT_UPS3 (1 << 16) /* USB Power Sense Port3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define UHCSTAT_SBMAI (1 << 15) /* System Bus Master Abort Interrupt*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define UHCSTAT_SBTAI (1 << 14) /* System Bus Target Abort Interrupt*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define UHCSTAT_UPRI (1 << 13) /* USB Port Resume Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define UHCSTAT_UPS2 (1 << 12) /* USB Power Sense Port 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define UHCSTAT_UPS1 (1 << 11) /* USB Power Sense Port 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define UHCSTAT_HTA (1 << 10) /* HCI Target Abort */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define UHCSTAT_HBA (1 << 8) /* HCI Buffer Active */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define UHCSTAT_RWUE (1 << 7) /* HCI Remote Wake Up Event */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define UHCHR (0x0064) /* UHC Reset Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define UHCHR_SSEP3 (1 << 11) /* Sleep Standby Enable for Port3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define UHCHR_SSEP2 (1 << 10) /* Sleep Standby Enable for Port2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define UHCHR_SSEP1 (1 << 9) /* Sleep Standby Enable for Port1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define UHCHR_PCPL (1 << 7) /* Power control polarity low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define UHCHR_PSPL (1 << 6) /* Power sense polarity low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define UHCHR_SSE (1 << 5) /* Sleep Standby Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define UHCHR_UIT (1 << 4) /* USB Interrupt Test */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define UHCHR_SSDC (1 << 3) /* Simulation Scale Down Clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define UHCHR_CGR (1 << 2) /* Clock Generation Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define UHCHR_FHR (1 << 1) /* Force Host Controller Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define UHCHR_FSBIR (1 << 0) /* Force System Bus Iface Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define UHCHIE (0x0068) /* UHC Interrupt Enable Register*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define UHCHIE_UPS3IE (1 << 14) /* Power Sense Port3 IntEn */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define UHCHIE_UPRIE (1 << 13) /* Port Resume IntEn */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define UHCHIE_UPS2IE (1 << 12) /* Power Sense Port2 IntEn */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define UHCHIE_UPS1IE (1 << 11) /* Power Sense Port1 IntEn */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define UHCHIE_TAIE (1 << 10) /* HCI Interface Transfer Abort
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) Interrupt Enable*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define UHCHIE_HBAIE (1 << 8) /* HCI Buffer Active IntEn */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define UHCHIE_RWIE (1 << 7) /* Remote Wake-up IntEn */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define UHCHIT (0x006C) /* UHC Interrupt Test register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define PXA_UHC_MAX_PORTNUM 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static const char hcd_name[] = "ohci-pxa27x";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static struct hc_driver __read_mostly ohci_pxa27x_hc_driver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) struct pxa27x_ohci {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) void __iomem *mmio_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) struct regulator *vbus[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) bool vbus_enabled[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define to_pxa27x_ohci(hcd) (struct pxa27x_ohci *)(hcd_to_ohci(hcd)->priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) PMM_NPS_MODE -- PMM Non-power switching mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) Ports are powered continuously.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) PMM_GLOBAL_MODE -- PMM global switching mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) All ports are powered at the same time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) PMM_PERPORT_MODE -- PMM per port switching mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) Ports are powered individually.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static int pxa27x_ohci_select_pmm(struct pxa27x_ohci *pxa_ohci, int mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) uint32_t uhcrhda = __raw_readl(pxa_ohci->mmio_base + UHCRHDA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) uint32_t uhcrhdb = __raw_readl(pxa_ohci->mmio_base + UHCRHDB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) switch (mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) case PMM_NPS_MODE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) uhcrhda |= RH_A_NPS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) case PMM_GLOBAL_MODE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) uhcrhda &= ~(RH_A_NPS | RH_A_PSM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) case PMM_PERPORT_MODE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) uhcrhda &= ~(RH_A_NPS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) uhcrhda |= RH_A_PSM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /* Set port power control mask bits, only 3 ports. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) uhcrhdb |= (0x7<<17);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) printk( KERN_ERR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) "Invalid mode %d, set to non-power switch mode.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) mode );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) uhcrhda |= RH_A_NPS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) __raw_writel(uhcrhda, pxa_ohci->mmio_base + UHCRHDA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) __raw_writel(uhcrhdb, pxa_ohci->mmio_base + UHCRHDB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) static int pxa27x_ohci_set_vbus_power(struct pxa27x_ohci *pxa_ohci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) unsigned int port, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) struct regulator *vbus = pxa_ohci->vbus[port];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) if (IS_ERR_OR_NULL(vbus))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) if (enable && !pxa_ohci->vbus_enabled[port])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) ret = regulator_enable(vbus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) else if (!enable && pxa_ohci->vbus_enabled[port])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) ret = regulator_disable(vbus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) pxa_ohci->vbus_enabled[port] = enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) static int pxa27x_ohci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) u16 wIndex, char *buf, u16 wLength)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) struct pxa27x_ohci *pxa_ohci = to_pxa27x_ohci(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) switch (typeReq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) case SetPortFeature:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) case ClearPortFeature:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) if (!wIndex || wIndex > 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) return -EPIPE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) if (wValue != USB_PORT_FEAT_POWER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) ret = pxa27x_ohci_set_vbus_power(pxa_ohci, wIndex - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) typeReq == SetPortFeature);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) return ohci_hub_control(hcd, typeReq, wValue, wIndex, buf, wLength);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) /*-------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) static inline void pxa27x_setup_hc(struct pxa27x_ohci *pxa_ohci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) struct pxaohci_platform_data *inf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) uint32_t uhchr = __raw_readl(pxa_ohci->mmio_base + UHCHR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) uint32_t uhcrhda = __raw_readl(pxa_ohci->mmio_base + UHCRHDA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) if (inf->flags & ENABLE_PORT1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) uhchr &= ~UHCHR_SSEP1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) if (inf->flags & ENABLE_PORT2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) uhchr &= ~UHCHR_SSEP2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) if (inf->flags & ENABLE_PORT3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) uhchr &= ~UHCHR_SSEP3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) if (inf->flags & POWER_CONTROL_LOW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) uhchr |= UHCHR_PCPL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) if (inf->flags & POWER_SENSE_LOW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) uhchr |= UHCHR_PSPL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) if (inf->flags & NO_OC_PROTECTION)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) uhcrhda |= UHCRHDA_NOCP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) uhcrhda &= ~UHCRHDA_NOCP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) if (inf->flags & OC_MODE_PERPORT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) uhcrhda |= UHCRHDA_OCPM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) uhcrhda &= ~UHCRHDA_OCPM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) if (inf->power_on_delay) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) uhcrhda &= ~UHCRHDA_POTPGT(0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) uhcrhda |= UHCRHDA_POTPGT(inf->power_on_delay / 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) __raw_writel(uhchr, pxa_ohci->mmio_base + UHCHR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) __raw_writel(uhcrhda, pxa_ohci->mmio_base + UHCRHDA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) static inline void pxa27x_reset_hc(struct pxa27x_ohci *pxa_ohci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) uint32_t uhchr = __raw_readl(pxa_ohci->mmio_base + UHCHR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) __raw_writel(uhchr | UHCHR_FHR, pxa_ohci->mmio_base + UHCHR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) udelay(11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) __raw_writel(uhchr & ~UHCHR_FHR, pxa_ohci->mmio_base + UHCHR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #ifdef CONFIG_PXA27x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) extern void pxa27x_clear_otgph(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define pxa27x_clear_otgph() do {} while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) static int pxa27x_start_hc(struct pxa27x_ohci *pxa_ohci, struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) int retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) struct pxaohci_platform_data *inf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) uint32_t uhchr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) struct usb_hcd *hcd = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) inf = dev_get_platdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) retval = clk_prepare_enable(pxa_ohci->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) if (retval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) pxa27x_reset_hc(pxa_ohci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) uhchr = __raw_readl(pxa_ohci->mmio_base + UHCHR) | UHCHR_FSBIR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) __raw_writel(uhchr, pxa_ohci->mmio_base + UHCHR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) while (__raw_readl(pxa_ohci->mmio_base + UHCHR) & UHCHR_FSBIR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) pxa27x_setup_hc(pxa_ohci, inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) if (inf->init)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) retval = inf->init(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) if (retval < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) clk_disable_unprepare(pxa_ohci->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) if (cpu_is_pxa3xx())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) pxa3xx_u2d_start_hc(&hcd->self);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) uhchr = __raw_readl(pxa_ohci->mmio_base + UHCHR) & ~UHCHR_SSE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) __raw_writel(uhchr, pxa_ohci->mmio_base + UHCHR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) __raw_writel(UHCHIE_UPRIE | UHCHIE_RWIE, pxa_ohci->mmio_base + UHCHIE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) /* Clear any OTG Pin Hold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) pxa27x_clear_otgph();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) static void pxa27x_stop_hc(struct pxa27x_ohci *pxa_ohci, struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) struct pxaohci_platform_data *inf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) struct usb_hcd *hcd = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) uint32_t uhccoms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) inf = dev_get_platdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) if (cpu_is_pxa3xx())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) pxa3xx_u2d_stop_hc(&hcd->self);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) if (inf->exit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) inf->exit(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) pxa27x_reset_hc(pxa_ohci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) /* Host Controller Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) uhccoms = __raw_readl(pxa_ohci->mmio_base + UHCCOMS) | 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) __raw_writel(uhccoms, pxa_ohci->mmio_base + UHCCOMS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) clk_disable_unprepare(pxa_ohci->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #ifdef CONFIG_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) static const struct of_device_id pxa_ohci_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) { .compatible = "marvell,pxa-ohci" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) MODULE_DEVICE_TABLE(of, pxa_ohci_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) static int ohci_pxa_of_init(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) struct pxaohci_platform_data *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) if (!np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) /* Right now device-tree probed devices don't get dma_mask set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) * Since shared usb code relies on it, set it here for now.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) * Once we have dma capability bindings this can go away.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) ret = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) if (!pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) if (of_property_read_bool(np, "marvell,enable-port1"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) pdata->flags |= ENABLE_PORT1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) if (of_property_read_bool(np, "marvell,enable-port2"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) pdata->flags |= ENABLE_PORT2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) if (of_property_read_bool(np, "marvell,enable-port3"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) pdata->flags |= ENABLE_PORT3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) if (of_property_read_bool(np, "marvell,port-sense-low"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) pdata->flags |= POWER_SENSE_LOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) if (of_property_read_bool(np, "marvell,power-control-low"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) pdata->flags |= POWER_CONTROL_LOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) if (of_property_read_bool(np, "marvell,no-oc-protection"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) pdata->flags |= NO_OC_PROTECTION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) if (of_property_read_bool(np, "marvell,oc-mode-perport"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) pdata->flags |= OC_MODE_PERPORT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) if (!of_property_read_u32(np, "marvell,power-on-delay", &tmp))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) pdata->power_on_delay = tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) if (!of_property_read_u32(np, "marvell,port-mode", &tmp))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) pdata->port_mode = tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) if (!of_property_read_u32(np, "marvell,power-budget", &tmp))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) pdata->power_budget = tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) pdev->dev.platform_data = pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) static int ohci_pxa_of_init(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) /*-------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) /* configure so an HC device and id are always provided */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) /* always called with process context; sleeping is OK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) * ohci_hcd_pxa27x_probe - initialize pxa27x-based HCDs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) * Context: !in_interrupt()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) * Allocates basic resources for this USB host controller, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) * then invokes the start() method for the HCD associated with it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) * through the hotplug entry's driver_data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) static int ohci_hcd_pxa27x_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) int retval, irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) struct usb_hcd *hcd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) struct pxaohci_platform_data *inf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) struct pxa27x_ohci *pxa_ohci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) struct ohci_hcd *ohci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) struct resource *r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) struct clk *usb_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) retval = ohci_pxa_of_init(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) if (retval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) inf = dev_get_platdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) if (!inf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) if (irq < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) pr_err("no resource of IORESOURCE_IRQ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) usb_clk = devm_clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) if (IS_ERR(usb_clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) return PTR_ERR(usb_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) hcd = usb_create_hcd(&ohci_pxa27x_hc_driver, &pdev->dev, "pxa27x");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) if (!hcd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) hcd->regs = devm_ioremap_resource(&pdev->dev, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) if (IS_ERR(hcd->regs)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) retval = PTR_ERR(hcd->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) hcd->rsrc_start = r->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) hcd->rsrc_len = resource_size(r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) /* initialize "struct pxa27x_ohci" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) pxa_ohci = to_pxa27x_ohci(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) pxa_ohci->clk = usb_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) pxa_ohci->mmio_base = (void __iomem *)hcd->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) for (i = 0; i < 3; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) char name[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) if (!(inf->flags & (ENABLE_PORT1 << i)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) sprintf(name, "vbus%u", i + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) pxa_ohci->vbus[i] = devm_regulator_get(&pdev->dev, name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) retval = pxa27x_start_hc(pxa_ohci, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) if (retval < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) pr_debug("pxa27x_start_hc failed");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) /* Select Power Management Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) pxa27x_ohci_select_pmm(pxa_ohci, inf->port_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) if (inf->power_budget)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) hcd->power_budget = inf->power_budget;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) /* The value of NDP in roothub_a is incorrect on this hardware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) ohci = hcd_to_ohci(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) ohci->num_ports = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) retval = usb_add_hcd(hcd, irq, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) if (retval == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) device_wakeup_enable(hcd->self.controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) pxa27x_stop_hc(pxa_ohci, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) usb_put_hcd(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) /* may be called without controller electrically present */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) /* may be called with controller, bus, and devices active */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) * ohci_hcd_pxa27x_remove - shutdown processing for pxa27x-based HCDs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) * @dev: USB Host Controller being removed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) * Context: !in_interrupt()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) * Reverses the effect of ohci_hcd_pxa27x_probe(), first invoking
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) * the HCD's stop() method. It is always called from a thread
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) * context, normally "rmmod", "apmd", or something similar.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) static int ohci_hcd_pxa27x_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) struct usb_hcd *hcd = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) struct pxa27x_ohci *pxa_ohci = to_pxa27x_ohci(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) usb_remove_hcd(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) pxa27x_stop_hc(pxa_ohci, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) for (i = 0; i < 3; ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) pxa27x_ohci_set_vbus_power(pxa_ohci, i, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) usb_put_hcd(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) /*-------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) static int ohci_hcd_pxa27x_drv_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) struct usb_hcd *hcd = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) struct pxa27x_ohci *pxa_ohci = to_pxa27x_ohci(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) struct ohci_hcd *ohci = hcd_to_ohci(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) bool do_wakeup = device_may_wakeup(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) if (time_before(jiffies, ohci->next_statechange))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) msleep(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) ohci->next_statechange = jiffies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) ret = ohci_suspend(hcd, do_wakeup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) pxa27x_stop_hc(pxa_ohci, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) static int ohci_hcd_pxa27x_drv_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) struct usb_hcd *hcd = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) struct pxa27x_ohci *pxa_ohci = to_pxa27x_ohci(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) struct pxaohci_platform_data *inf = dev_get_platdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) struct ohci_hcd *ohci = hcd_to_ohci(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) if (time_before(jiffies, ohci->next_statechange))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) msleep(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) ohci->next_statechange = jiffies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) status = pxa27x_start_hc(pxa_ohci, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) /* Select Power Management Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) pxa27x_ohci_select_pmm(pxa_ohci, inf->port_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) ohci_resume(hcd, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) static const struct dev_pm_ops ohci_hcd_pxa27x_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) .suspend = ohci_hcd_pxa27x_drv_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) .resume = ohci_hcd_pxa27x_drv_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) static struct platform_driver ohci_hcd_pxa27x_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) .probe = ohci_hcd_pxa27x_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) .remove = ohci_hcd_pxa27x_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) .shutdown = usb_hcd_platform_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) .name = "pxa27x-ohci",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) .of_match_table = of_match_ptr(pxa_ohci_dt_ids),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) .pm = &ohci_hcd_pxa27x_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) static const struct ohci_driver_overrides pxa27x_overrides __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) .extra_priv_size = sizeof(struct pxa27x_ohci),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) static int __init ohci_pxa27x_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) if (usb_disabled())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) pr_info("%s: " DRIVER_DESC "\n", hcd_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) ohci_init_driver(&ohci_pxa27x_hc_driver, &pxa27x_overrides);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) ohci_pxa27x_hc_driver.hub_control = pxa27x_ohci_hub_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) return platform_driver_register(&ohci_hcd_pxa27x_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) module_init(ohci_pxa27x_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) static void __exit ohci_pxa27x_cleanup(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) platform_driver_unregister(&ohci_hcd_pxa27x_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) module_exit(ohci_pxa27x_cleanup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) MODULE_DESCRIPTION(DRIVER_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) MODULE_ALIAS("platform:pxa27x-ohci");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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