^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-1.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Open Host Controller Interface (OHCI) driver for USB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Maintainer: Alan Stern <stern@rowland.harvard.edu>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * (C) Copyright 2000-2004 David Brownell <dbrownell@users.sourceforge.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * [ Initialisation is based on Linus' ]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * [ uhci code and gregs ohci fragments ]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * [ (C) Copyright 1999 Linus Torvalds ]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * [ (C) Copyright 1999 Gregory P. Smith]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * OHCI is the main "non-Intel/VIA" standard for USB 1.1 host controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * interfaces (though some non-x86 Intel chips use it). It supports
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * smarter hardware than UHCI. A download link for the spec available
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * through the https://www.usb.org website.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * This file is licenced under the GPL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/moduleparam.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/timer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <linux/list.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <linux/usb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <linux/usb/otg.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <linux/usb/hcd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include <linux/dmapool.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #include <linux/workqueue.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #include <linux/debugfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #include <linux/genalloc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #include <asm/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #include <asm/unaligned.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #include <asm/byteorder.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define DRIVER_AUTHOR "Roman Weissgaerber, David Brownell"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define DRIVER_DESC "USB 1.1 'Open' Host Controller (OHCI) Driver"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /*-------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /* For initializing controller (mask in an HCFS mode too) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define OHCI_CONTROL_INIT OHCI_CTRL_CBSR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define OHCI_INTR_INIT \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) (OHCI_INTR_MIE | OHCI_INTR_RHSC | OHCI_INTR_UE \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) | OHCI_INTR_RD | OHCI_INTR_WDH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #ifdef __hppa__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /* On PA-RISC, PDC can leave IR set incorrectly; ignore it there. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define IR_DISABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #ifdef CONFIG_ARCH_OMAP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /* OMAP doesn't support IR (no SMM; not needed) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define IR_DISABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /*-------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) static const char hcd_name [] = "ohci_hcd";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define STATECHANGE_DELAY msecs_to_jiffies(300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define IO_WATCHDOG_DELAY msecs_to_jiffies(275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define IO_WATCHDOG_OFF 0xffffff00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #include "ohci.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #include "pci-quirks.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) static void ohci_dump(struct ohci_hcd *ohci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) static void ohci_stop(struct usb_hcd *hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) static void io_watchdog_func(struct timer_list *t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #include "ohci-hub.c"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #include "ohci-dbg.c"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #include "ohci-mem.c"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #include "ohci-q.c"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * On architectures with edge-triggered interrupts we must never return
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * IRQ_NONE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #if defined(CONFIG_SA1111) /* ... or other edge-triggered systems */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define IRQ_NOTMINE IRQ_HANDLED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define IRQ_NOTMINE IRQ_NONE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /* Some boards misreport power switching/overcurrent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static bool distrust_firmware;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) module_param (distrust_firmware, bool, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) MODULE_PARM_DESC (distrust_firmware,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) "true to distrust firmware power/overcurrent setup");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /* Some boards leave IR set wrongly, since they fail BIOS/SMM handshakes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static bool no_handshake;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) module_param (no_handshake, bool, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) MODULE_PARM_DESC (no_handshake, "true (not default) disables BIOS handshake");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /*-------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static int number_of_tds(struct urb *urb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) int len, i, num, this_sg_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) struct scatterlist *sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) len = urb->transfer_buffer_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) i = urb->num_mapped_sgs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) if (len > 0 && i > 0) { /* Scatter-gather transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) num = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) sg = urb->sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) for (;;) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) this_sg_len = min_t(int, sg_dma_len(sg), len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) num += DIV_ROUND_UP(this_sg_len, 4096);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) len -= this_sg_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) if (--i <= 0 || len <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) sg = sg_next(sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) } else { /* Non-SG transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /* one TD for every 4096 Bytes (could be up to 8K) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) num = DIV_ROUND_UP(len, 4096);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) return num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) * queue up an urb for anything except the root hub
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static int ohci_urb_enqueue (
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) struct usb_hcd *hcd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) struct urb *urb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) gfp_t mem_flags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) struct ohci_hcd *ohci = hcd_to_ohci (hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) struct ed *ed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) urb_priv_t *urb_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) unsigned int pipe = urb->pipe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) int i, size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) int retval = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) /* every endpoint has a ed, locate and maybe (re)initialize it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) ed = ed_get(ohci, urb->ep, urb->dev, pipe, urb->interval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) if (! ed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /* for the private part of the URB we need the number of TDs (size) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) switch (ed->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) case PIPE_CONTROL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) /* td_submit_urb() doesn't yet handle these */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) if (urb->transfer_buffer_length > 4096)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) return -EMSGSIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /* 1 TD for setup, 1 for ACK, plus ... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) size = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) /* FALLTHROUGH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) // case PIPE_INTERRUPT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) // case PIPE_BULK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) size += number_of_tds(urb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) /* maybe a zero-length packet to wrap it up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) if (size == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) size++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) else if ((urb->transfer_flags & URB_ZERO_PACKET) != 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) && (urb->transfer_buffer_length
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) % usb_maxpacket (urb->dev, pipe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) usb_pipeout (pipe))) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) size++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) case PIPE_ISOCHRONOUS: /* number of packets from URB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) size = urb->number_of_packets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) /* allocate the private part of the URB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) urb_priv = kzalloc (sizeof (urb_priv_t) + size * sizeof (struct td *),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) mem_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) if (!urb_priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) INIT_LIST_HEAD (&urb_priv->pending);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) urb_priv->length = size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) urb_priv->ed = ed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) /* allocate the TDs (deferring hash chain updates) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) for (i = 0; i < size; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) urb_priv->td [i] = td_alloc (ohci, mem_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) if (!urb_priv->td [i]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) urb_priv->length = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) urb_free_priv (ohci, urb_priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) spin_lock_irqsave (&ohci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) /* don't submit to a dead HC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) if (!HCD_HW_ACCESSIBLE(hcd)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) retval = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) if (ohci->rh_state != OHCI_RH_RUNNING) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) retval = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) retval = usb_hcd_link_urb_to_ep(hcd, urb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) if (retval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) /* schedule the ed if needed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) if (ed->state == ED_IDLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) retval = ed_schedule (ohci, ed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) if (retval < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) usb_hcd_unlink_urb_from_ep(hcd, urb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) /* Start up the I/O watchdog timer, if it's not running */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) if (ohci->prev_frame_no == IO_WATCHDOG_OFF &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) list_empty(&ohci->eds_in_use) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) !(ohci->flags & OHCI_QUIRK_QEMU)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) ohci->prev_frame_no = ohci_frame_no(ohci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) mod_timer(&ohci->io_watchdog,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) jiffies + IO_WATCHDOG_DELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) list_add(&ed->in_use_list, &ohci->eds_in_use);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) if (ed->type == PIPE_ISOCHRONOUS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) u16 frame = ohci_frame_no(ohci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) /* delay a few frames before the first TD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) frame += max_t (u16, 8, ed->interval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) frame &= ~(ed->interval - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) frame |= ed->branch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) urb->start_frame = frame;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) ed->last_iso = frame + ed->interval * (size - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) } else if (ed->type == PIPE_ISOCHRONOUS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) u16 next = ohci_frame_no(ohci) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) u16 frame = ed->last_iso + ed->interval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) u16 length = ed->interval * (size - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) /* Behind the scheduling threshold? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) if (unlikely(tick_before(frame, next))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) /* URB_ISO_ASAP: Round up to the first available slot */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) if (urb->transfer_flags & URB_ISO_ASAP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) frame += (next - frame + ed->interval - 1) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) -ed->interval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) * Not ASAP: Use the next slot in the stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) * no matter what.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) * Some OHCI hardware doesn't handle late TDs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) * correctly. After retiring them it proceeds
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) * to the next ED instead of the next TD.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) * Therefore we have to omit the late TDs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) * entirely.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) urb_priv->td_cnt = DIV_ROUND_UP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) (u16) (next - frame),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) ed->interval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) if (urb_priv->td_cnt >= urb_priv->length) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) ++urb_priv->td_cnt; /* Mark it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) ohci_dbg(ohci, "iso underrun %p (%u+%u < %u)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) urb, frame, length,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) next);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) urb->start_frame = frame;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) ed->last_iso = frame + length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) /* fill the TDs and link them to the ed; and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) * enable that part of the schedule, if needed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) * and update count of queued periodic urbs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) urb->hcpriv = urb_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) td_submit_urb (ohci, urb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) if (retval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) urb_free_priv (ohci, urb_priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) spin_unlock_irqrestore (&ohci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) * decouple the URB from the HC queues (TDs, urb_priv).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) * reporting is always done
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) * asynchronously, and we might be dealing with an urb that's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) * partially transferred, or an ED with other urbs being unlinked.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) static int ohci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) struct ohci_hcd *ohci = hcd_to_ohci (hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) urb_priv_t *urb_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) spin_lock_irqsave (&ohci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) rc = usb_hcd_check_unlink_urb(hcd, urb, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) if (rc == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) /* Unless an IRQ completed the unlink while it was being
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) * handed to us, flag it for unlink and giveback, and force
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) * some upcoming INTR_SF to call finish_unlinks()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) urb_priv = urb->hcpriv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) if (urb_priv->ed->state == ED_OPER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) start_ed_unlink(ohci, urb_priv->ed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) if (ohci->rh_state != OHCI_RH_RUNNING) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) /* With HC dead, we can clean up right away */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) ohci_work(ohci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) spin_unlock_irqrestore (&ohci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) /*-------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) /* frees config/altsetting state for endpoints,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) * including ED memory, dummy TD, and bulk/intr data toggle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) ohci_endpoint_disable (struct usb_hcd *hcd, struct usb_host_endpoint *ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) struct ohci_hcd *ohci = hcd_to_ohci (hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) struct ed *ed = ep->hcpriv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) unsigned limit = 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) /* ASSERT: any requests/urbs are being unlinked */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) /* ASSERT: nobody can be submitting urbs for this any more */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) if (!ed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) rescan:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) spin_lock_irqsave (&ohci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) if (ohci->rh_state != OHCI_RH_RUNNING) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) sanitize:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) ed->state = ED_IDLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) ohci_work(ohci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) switch (ed->state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) case ED_UNLINK: /* wait for hw to finish? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) /* major IRQ delivery trouble loses INTR_SF too... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) if (limit-- == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) ohci_warn(ohci, "ED unlink timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) goto sanitize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) spin_unlock_irqrestore (&ohci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) schedule_timeout_uninterruptible(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) goto rescan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) case ED_IDLE: /* fully unlinked */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) if (list_empty (&ed->td_list)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) td_free (ohci, ed->dummy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) ed_free (ohci, ed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) /* caller was supposed to have unlinked any requests;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) * that's not our job. can't recover; must leak ed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) ohci_err (ohci, "leak ed %p (#%02x) state %d%s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) ed, ep->desc.bEndpointAddress, ed->state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) list_empty (&ed->td_list) ? "" : " (has tds)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) td_free (ohci, ed->dummy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) ep->hcpriv = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) spin_unlock_irqrestore (&ohci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) static int ohci_get_frame (struct usb_hcd *hcd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) struct ohci_hcd *ohci = hcd_to_ohci (hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) return ohci_frame_no(ohci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) static void ohci_usb_reset (struct ohci_hcd *ohci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) ohci->hc_control = ohci_readl (ohci, &ohci->regs->control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) ohci->hc_control &= OHCI_CTRL_RWC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) ohci->rh_state = OHCI_RH_HALTED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) /* ohci_shutdown forcibly disables IRQs and DMA, helping kexec and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) * other cases where the next software may expect clean state from the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) * "firmware". this is bus-neutral, unlike shutdown() methods.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) static void _ohci_shutdown(struct usb_hcd *hcd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) struct ohci_hcd *ohci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) ohci = hcd_to_ohci (hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) ohci_writel(ohci, (u32) ~0, &ohci->regs->intrdisable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) /* Software reset, after which the controller goes into SUSPEND */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) ohci_writel(ohci, OHCI_HCR, &ohci->regs->cmdstatus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) ohci_readl(ohci, &ohci->regs->cmdstatus); /* flush the writes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) ohci_writel(ohci, ohci->fminterval, &ohci->regs->fminterval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) ohci->rh_state = OHCI_RH_HALTED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) static void ohci_shutdown(struct usb_hcd *hcd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) struct ohci_hcd *ohci = hcd_to_ohci(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) spin_lock_irqsave(&ohci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) _ohci_shutdown(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) spin_unlock_irqrestore(&ohci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) /*-------------------------------------------------------------------------*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) * HC functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) *-------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) /* init memory, and kick BIOS/SMM off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) static int ohci_init (struct ohci_hcd *ohci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) struct usb_hcd *hcd = ohci_to_hcd(ohci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) /* Accept arbitrarily long scatter-gather lists */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) if (!hcd->localmem_pool)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) hcd->self.sg_tablesize = ~0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) if (distrust_firmware)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) ohci->flags |= OHCI_QUIRK_HUB_POWER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) ohci->rh_state = OHCI_RH_HALTED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) ohci->regs = hcd->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) /* REVISIT this BIOS handshake is now moved into PCI "quirks", and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) * was never needed for most non-PCI systems ... remove the code?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) #ifndef IR_DISABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) /* SMM owns the HC? not for long! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) if (!no_handshake && ohci_readl (ohci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) &ohci->regs->control) & OHCI_CTRL_IR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) u32 temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) ohci_dbg (ohci, "USB HC TakeOver from BIOS/SMM\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) /* this timeout is arbitrary. we make it long, so systems
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) * depending on usb keyboards may be usable even if the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) * BIOS/SMM code seems pretty broken.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) temp = 500; /* arbitrary: five seconds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) ohci_writel (ohci, OHCI_INTR_OC, &ohci->regs->intrenable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) ohci_writel (ohci, OHCI_OCR, &ohci->regs->cmdstatus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) while (ohci_readl (ohci, &ohci->regs->control) & OHCI_CTRL_IR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) msleep (10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) if (--temp == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) ohci_err (ohci, "USB HC takeover failed!"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) " (BIOS/SMM bug)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) ohci_usb_reset (ohci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) /* Disable HC interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) ohci_writel (ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) /* flush the writes, and save key bits like RWC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) if (ohci_readl (ohci, &ohci->regs->control) & OHCI_CTRL_RWC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) ohci->hc_control |= OHCI_CTRL_RWC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) /* Read the number of ports unless overridden */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) if (ohci->num_ports == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) ohci->num_ports = roothub_a(ohci) & RH_A_NDP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) if (ohci->hcca)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) timer_setup(&ohci->io_watchdog, io_watchdog_func, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) ohci->prev_frame_no = IO_WATCHDOG_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) if (hcd->localmem_pool)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) ohci->hcca = gen_pool_dma_alloc_align(hcd->localmem_pool,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) sizeof(*ohci->hcca),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) &ohci->hcca_dma, 256);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) ohci->hcca = dma_alloc_coherent(hcd->self.controller,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) sizeof(*ohci->hcca),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) &ohci->hcca_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) if (!ohci->hcca)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) if ((ret = ohci_mem_init (ohci)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) ohci_stop (hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) create_debug_files (ohci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) /*-------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) /* Start an OHCI controller, set the BUS operational
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) * resets USB and controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) * enable interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) static int ohci_run (struct ohci_hcd *ohci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) u32 mask, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) int first = ohci->fminterval == 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) struct usb_hcd *hcd = ohci_to_hcd(ohci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) ohci->rh_state = OHCI_RH_HALTED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) /* boot firmware should have set this up (5.1.1.3.1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) if (first) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) val = ohci_readl (ohci, &ohci->regs->fminterval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) ohci->fminterval = val & 0x3fff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) if (ohci->fminterval != FI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) ohci_dbg (ohci, "fminterval delta %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) ohci->fminterval - FI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) ohci->fminterval |= FSMP (ohci->fminterval) << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) /* also: power/overcurrent flags in roothub.a */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) /* Reset USB nearly "by the book". RemoteWakeupConnected has
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) * to be checked in case boot firmware (BIOS/SMM/...) has set up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) * wakeup in a way the bus isn't aware of (e.g., legacy PCI PM).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) * If the bus glue detected wakeup capability then it should
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) * already be enabled; if so we'll just enable it again.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) if ((ohci->hc_control & OHCI_CTRL_RWC) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) device_set_wakeup_capable(hcd->self.controller, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) switch (ohci->hc_control & OHCI_CTRL_HCFS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) case OHCI_USB_OPER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) case OHCI_USB_SUSPEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) case OHCI_USB_RESUME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) ohci->hc_control &= OHCI_CTRL_RWC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) ohci->hc_control |= OHCI_USB_RESUME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) val = 10 /* msec wait */;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) // case OHCI_USB_RESET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) ohci->hc_control &= OHCI_CTRL_RWC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) ohci->hc_control |= OHCI_USB_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) val = 50 /* msec wait */;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) // flush the writes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) (void) ohci_readl (ohci, &ohci->regs->control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) msleep(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) memset (ohci->hcca, 0, sizeof (struct ohci_hcca));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) /* 2msec timelimit here means no irqs/preempt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) spin_lock_irq (&ohci->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) retry:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) /* HC Reset requires max 10 us delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) ohci_writel (ohci, OHCI_HCR, &ohci->regs->cmdstatus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) val = 30; /* ... allow extra time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) while ((ohci_readl (ohci, &ohci->regs->cmdstatus) & OHCI_HCR) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) if (--val == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) spin_unlock_irq (&ohci->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) ohci_err (ohci, "USB HC reset timed out!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) udelay (1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) /* now we're in the SUSPEND state ... must go OPERATIONAL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) * within 2msec else HC enters RESUME
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) * ... but some hardware won't init fmInterval "by the book"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) * (SiS, OPTi ...), so reset again instead. SiS doesn't need
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) * this if we write fmInterval after we're OPERATIONAL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) * Unclear about ALi, ServerWorks, and others ... this could
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) * easily be a longstanding bug in chip init on Linux.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) if (ohci->flags & OHCI_QUIRK_INITRESET) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) // flush those writes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) (void) ohci_readl (ohci, &ohci->regs->control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) /* Tell the controller where the control and bulk lists are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) * The lists are empty now. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) ohci_writel (ohci, 0, &ohci->regs->ed_controlhead);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) ohci_writel (ohci, 0, &ohci->regs->ed_bulkhead);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) /* a reset clears this */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) ohci_writel (ohci, (u32) ohci->hcca_dma, &ohci->regs->hcca);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) periodic_reinit (ohci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) /* some OHCI implementations are finicky about how they init.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) * bogus values here mean not even enumeration could work.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) if ((ohci_readl (ohci, &ohci->regs->fminterval) & 0x3fff0000) == 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) || !ohci_readl (ohci, &ohci->regs->periodicstart)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) if (!(ohci->flags & OHCI_QUIRK_INITRESET)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) ohci->flags |= OHCI_QUIRK_INITRESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) ohci_dbg (ohci, "enabling initreset quirk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) goto retry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) spin_unlock_irq (&ohci->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) ohci_err (ohci, "init err (%08x %04x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) ohci_readl (ohci, &ohci->regs->fminterval),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) ohci_readl (ohci, &ohci->regs->periodicstart));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) return -EOVERFLOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) /* use rhsc irqs after hub_wq is allocated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) hcd->uses_new_polling = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) /* start controller operations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) ohci->hc_control &= OHCI_CTRL_RWC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) ohci->hc_control |= OHCI_CONTROL_INIT | OHCI_USB_OPER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) ohci->rh_state = OHCI_RH_RUNNING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) /* wake on ConnectStatusChange, matching external hubs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) ohci_writel (ohci, RH_HS_DRWE, &ohci->regs->roothub.status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) /* Choose the interrupts we care about now, others later on demand */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) mask = OHCI_INTR_INIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) ohci_writel (ohci, ~0, &ohci->regs->intrstatus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) ohci_writel (ohci, mask, &ohci->regs->intrenable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) /* handle root hub init quirks ... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) val = roothub_a (ohci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) /* Configure for per-port over-current protection by default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) val &= ~RH_A_NOCP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) val |= RH_A_OCPM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) if (ohci->flags & OHCI_QUIRK_SUPERIO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) /* NSC 87560 and maybe others.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) * Ganged power switching, no over-current protection.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) val |= RH_A_NOCP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) val &= ~(RH_A_POTPGT | RH_A_NPS | RH_A_PSM | RH_A_OCPM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) } else if ((ohci->flags & OHCI_QUIRK_AMD756) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) (ohci->flags & OHCI_QUIRK_HUB_POWER)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) /* hub power always on; required for AMD-756 and some
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) * Mac platforms.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) val |= RH_A_NPS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) ohci_writel(ohci, val, &ohci->regs->roothub.a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) ohci_writel (ohci, RH_HS_LPSC, &ohci->regs->roothub.status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) ohci_writel (ohci, (val & RH_A_NPS) ? 0 : RH_B_PPCM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) &ohci->regs->roothub.b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) // flush those writes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) (void) ohci_readl (ohci, &ohci->regs->control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) ohci->next_statechange = jiffies + STATECHANGE_DELAY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) spin_unlock_irq (&ohci->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) // POTPGT delay is bits 24-31, in 2 ms units.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) mdelay ((val >> 23) & 0x1fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) ohci_dump(ohci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) /* ohci_setup routine for generic controller initialization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) int ohci_setup(struct usb_hcd *hcd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) struct ohci_hcd *ohci = hcd_to_ohci(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) ohci_hcd_init(ohci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) return ohci_init(ohci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) EXPORT_SYMBOL_GPL(ohci_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) /* ohci_start routine for generic controller start of all OHCI bus glue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) static int ohci_start(struct usb_hcd *hcd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) struct ohci_hcd *ohci = hcd_to_ohci(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) ret = ohci_run(ohci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) ohci_err(ohci, "can't start\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) ohci_stop(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) /*-------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) * Some OHCI controllers are known to lose track of completed TDs. They
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) * don't add the TDs to the hardware done queue, which means we never see
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) * them as being completed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) * This watchdog routine checks for such problems. Without some way to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) * tell when those TDs have completed, we would never take their EDs off
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) * the unlink list. As a result, URBs could never be dequeued and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) * endpoints could never be released.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) static void io_watchdog_func(struct timer_list *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) struct ohci_hcd *ohci = from_timer(ohci, t, io_watchdog);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) bool takeback_all_pending = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) u32 head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) struct ed *ed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) struct td *td, *td_start, *td_next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) unsigned frame_no, prev_frame_no = IO_WATCHDOG_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) spin_lock_irqsave(&ohci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) * One way to lose track of completed TDs is if the controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) * never writes back the done queue head. If it hasn't been
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) * written back since the last time this function ran and if it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) * was non-empty at that time, something is badly wrong with the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) * hardware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) status = ohci_readl(ohci, &ohci->regs->intrstatus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) if (!(status & OHCI_INTR_WDH) && ohci->wdh_cnt == ohci->prev_wdh_cnt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) if (ohci->prev_donehead) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) ohci_err(ohci, "HcDoneHead not written back; disabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) died:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) usb_hc_died(ohci_to_hcd(ohci));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) ohci_dump(ohci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) _ohci_shutdown(ohci_to_hcd(ohci));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) /* No write back because the done queue was empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) takeback_all_pending = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) /* Check every ED which might have pending TDs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) list_for_each_entry(ed, &ohci->eds_in_use, in_use_list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) if (ed->pending_td) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) if (takeback_all_pending ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) OKAY_TO_TAKEBACK(ohci, ed)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) unsigned tmp = hc32_to_cpu(ohci, ed->hwINFO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) ohci_dbg(ohci, "takeback pending TD for dev %d ep 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) 0x007f & tmp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) (0x000f & (tmp >> 7)) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) ((tmp & ED_IN) >> 5));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) add_to_done_list(ohci, ed->pending_td);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) /* Starting from the latest pending TD, */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) td = ed->pending_td;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) /* or the last TD on the done list, */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) if (!td) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) list_for_each_entry(td_next, &ed->td_list, td_list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) if (!td_next->next_dl_td)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) td = td_next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) /* find the last TD processed by the controller. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) head = hc32_to_cpu(ohci, READ_ONCE(ed->hwHeadP)) & TD_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) td_start = td;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) td_next = list_prepare_entry(td, &ed->td_list, td_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) list_for_each_entry_continue(td_next, &ed->td_list, td_list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) if (head == (u32) td_next->td_dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) td = td_next; /* head pointer has passed this TD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) if (td != td_start) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) * In case a WDH cycle is in progress, we will wait
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) * for the next two cycles to complete before assuming
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) * this TD will never get on the done queue.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) ed->takeback_wdh_cnt = ohci->wdh_cnt + 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) ed->pending_td = td;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) ohci_work(ohci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) if (ohci->rh_state == OHCI_RH_RUNNING) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) * Sometimes a controller just stops working. We can tell
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) * by checking that the frame counter has advanced since
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) * the last time we ran.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) * But be careful: Some controllers violate the spec by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) * stopping their frame counter when no ports are active.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) frame_no = ohci_frame_no(ohci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) if (frame_no == ohci->prev_frame_no) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) int active_cnt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) unsigned tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) for (i = 0; i < ohci->num_ports; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) tmp = roothub_portstatus(ohci, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) /* Enabled and not suspended? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) if ((tmp & RH_PS_PES) && !(tmp & RH_PS_PSS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) ++active_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) if (active_cnt > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) ohci_err(ohci, "frame counter not updating; disabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) goto died;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) if (!list_empty(&ohci->eds_in_use)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) prev_frame_no = frame_no;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) ohci->prev_wdh_cnt = ohci->wdh_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) ohci->prev_donehead = ohci_readl(ohci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) &ohci->regs->donehead);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) mod_timer(&ohci->io_watchdog,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) jiffies + IO_WATCHDOG_DELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) ohci->prev_frame_no = prev_frame_no;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) spin_unlock_irqrestore(&ohci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) /* an interrupt happens */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) static irqreturn_t ohci_irq (struct usb_hcd *hcd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) struct ohci_hcd *ohci = hcd_to_ohci (hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) struct ohci_regs __iomem *regs = ohci->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) int ints;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) /* Read interrupt status (and flush pending writes). We ignore the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) * optimization of checking the LSB of hcca->done_head; it doesn't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) * work on all systems (edge triggering for OHCI can be a factor).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) ints = ohci_readl(ohci, ®s->intrstatus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) /* Check for an all 1's result which is a typical consequence
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) * of dead, unclocked, or unplugged (CardBus...) devices
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) if (ints == ~(u32)0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) ohci->rh_state = OHCI_RH_HALTED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) ohci_dbg (ohci, "device removed!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) usb_hc_died(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) /* We only care about interrupts that are enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) ints &= ohci_readl(ohci, ®s->intrenable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) /* interrupt for some other device? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) if (ints == 0 || unlikely(ohci->rh_state == OHCI_RH_HALTED))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) return IRQ_NOTMINE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) if (ints & OHCI_INTR_UE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) // e.g. due to PCI Master/Target Abort
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) if (quirk_nec(ohci)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) /* Workaround for a silicon bug in some NEC chips used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) * in Apple's PowerBooks. Adapted from Darwin code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) ohci_err (ohci, "OHCI Unrecoverable Error, scheduling NEC chip restart\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) ohci_writel (ohci, OHCI_INTR_UE, ®s->intrdisable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) schedule_work (&ohci->nec_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) ohci_err (ohci, "OHCI Unrecoverable Error, disabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) ohci->rh_state = OHCI_RH_HALTED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) usb_hc_died(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) ohci_dump(ohci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) ohci_usb_reset (ohci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) if (ints & OHCI_INTR_RHSC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) ohci_dbg(ohci, "rhsc\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) ohci->next_statechange = jiffies + STATECHANGE_DELAY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) ohci_writel(ohci, OHCI_INTR_RD | OHCI_INTR_RHSC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) ®s->intrstatus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) /* NOTE: Vendors didn't always make the same implementation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) * choices for RHSC. Many followed the spec; RHSC triggers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) * on an edge, like setting and maybe clearing a port status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) * change bit. With others it's level-triggered, active
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) * until hub_wq clears all the port status change bits. We'll
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) * always disable it here and rely on polling until hub_wq
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) * re-enables it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) ohci_writel(ohci, OHCI_INTR_RHSC, ®s->intrdisable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) usb_hcd_poll_rh_status(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) /* For connect and disconnect events, we expect the controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) * to turn on RHSC along with RD. But for remote wakeup events
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) * this might not happen.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) else if (ints & OHCI_INTR_RD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) ohci_dbg(ohci, "resume detect\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) ohci_writel(ohci, OHCI_INTR_RD, ®s->intrstatus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) if (ohci->autostop) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) spin_lock (&ohci->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) ohci_rh_resume (ohci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) spin_unlock (&ohci->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) usb_hcd_resume_root_hub(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) spin_lock(&ohci->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) if (ints & OHCI_INTR_WDH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) update_done_list(ohci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) /* could track INTR_SO to reduce available PCI/... bandwidth */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) /* handle any pending URB/ED unlinks, leaving INTR_SF enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) * when there's still unlinking to be done (next frame).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) ohci_work(ohci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) if ((ints & OHCI_INTR_SF) != 0 && !ohci->ed_rm_list
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) && ohci->rh_state == OHCI_RH_RUNNING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) ohci_writel (ohci, OHCI_INTR_SF, ®s->intrdisable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) if (ohci->rh_state == OHCI_RH_RUNNING) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) ohci_writel (ohci, ints, ®s->intrstatus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) if (ints & OHCI_INTR_WDH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) ++ohci->wdh_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) ohci_writel (ohci, OHCI_INTR_MIE, ®s->intrenable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) // flush those writes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) (void) ohci_readl (ohci, &ohci->regs->control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) spin_unlock(&ohci->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) /*-------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) static void ohci_stop (struct usb_hcd *hcd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) struct ohci_hcd *ohci = hcd_to_ohci (hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) ohci_dump(ohci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) if (quirk_nec(ohci))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) flush_work(&ohci->nec_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) del_timer_sync(&ohci->io_watchdog);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) ohci->prev_frame_no = IO_WATCHDOG_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) ohci_writel (ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) ohci_usb_reset(ohci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) free_irq(hcd->irq, hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) hcd->irq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) if (quirk_amdiso(ohci))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) usb_amd_dev_put();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) remove_debug_files (ohci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) ohci_mem_cleanup (ohci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) if (ohci->hcca) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) if (hcd->localmem_pool)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) gen_pool_free(hcd->localmem_pool,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) (unsigned long)ohci->hcca,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) sizeof(*ohci->hcca));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) dma_free_coherent(hcd->self.controller,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) sizeof(*ohci->hcca),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) ohci->hcca, ohci->hcca_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) ohci->hcca = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) ohci->hcca_dma = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) /*-------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) #if defined(CONFIG_PM) || defined(CONFIG_USB_PCI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) /* must not be called from interrupt context */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) int ohci_restart(struct ohci_hcd *ohci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) int temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) struct urb_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) ohci_init(ohci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) spin_lock_irq(&ohci->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) ohci->rh_state = OHCI_RH_HALTED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) /* Recycle any "live" eds/tds (and urbs). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) if (!list_empty (&ohci->pending))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) ohci_dbg(ohci, "abort schedule...\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) list_for_each_entry (priv, &ohci->pending, pending) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) struct urb *urb = priv->td[0]->urb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) struct ed *ed = priv->ed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) switch (ed->state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) case ED_OPER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) ed->state = ED_UNLINK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) ed->hwINFO |= cpu_to_hc32(ohci, ED_DEQUEUE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) ed_deschedule (ohci, ed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) ed->ed_next = ohci->ed_rm_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) ed->ed_prev = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) ohci->ed_rm_list = ed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) case ED_UNLINK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) ohci_dbg(ohci, "bogus ed %p state %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) ed, ed->state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) if (!urb->unlinked)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) urb->unlinked = -ESHUTDOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) ohci_work(ohci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) spin_unlock_irq(&ohci->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) /* paranoia, in case that didn't work: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) /* empty the interrupt branches */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) for (i = 0; i < NUM_INTS; i++) ohci->load [i] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) for (i = 0; i < NUM_INTS; i++) ohci->hcca->int_table [i] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) /* no EDs to remove */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) ohci->ed_rm_list = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) /* empty control and bulk lists */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) ohci->ed_controltail = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) ohci->ed_bulktail = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) if ((temp = ohci_run (ohci)) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) ohci_err (ohci, "can't restart, %d\n", temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) return temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) ohci_dbg(ohci, "restart complete\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) EXPORT_SYMBOL_GPL(ohci_restart);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) int ohci_suspend(struct usb_hcd *hcd, bool do_wakeup)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) struct ohci_hcd *ohci = hcd_to_ohci (hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) int rc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) /* Disable irq emission and mark HW unaccessible. Use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) * the spinlock to properly synchronize with possible pending
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) * RH suspend or resume activity.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) spin_lock_irqsave (&ohci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) ohci_writel(ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) (void)ohci_readl(ohci, &ohci->regs->intrdisable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) spin_unlock_irqrestore (&ohci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) synchronize_irq(hcd->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) if (do_wakeup && HCD_WAKEUP_PENDING(hcd)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) ohci_resume(hcd, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) rc = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) EXPORT_SYMBOL_GPL(ohci_suspend);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) int ohci_resume(struct usb_hcd *hcd, bool hibernated)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) struct ohci_hcd *ohci = hcd_to_ohci(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) int port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) bool need_reinit = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) /* Make sure resume from hibernation re-enumerates everything */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) if (hibernated)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) ohci_usb_reset(ohci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) /* See if the controller is already running or has been reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) ohci->hc_control = ohci_readl(ohci, &ohci->regs->control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) if (ohci->hc_control & (OHCI_CTRL_IR | OHCI_SCHED_ENABLES)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) need_reinit = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) switch (ohci->hc_control & OHCI_CTRL_HCFS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) case OHCI_USB_OPER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) case OHCI_USB_RESET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) need_reinit = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) /* If needed, reinitialize and suspend the root hub */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) if (need_reinit) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) spin_lock_irq(&ohci->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) ohci_rh_resume(ohci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) ohci_rh_suspend(ohci, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) spin_unlock_irq(&ohci->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) /* Normally just turn on port power and enable interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) ohci_dbg(ohci, "powerup ports\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) for (port = 0; port < ohci->num_ports; port++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) ohci_writel(ohci, RH_PS_PPS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) &ohci->regs->roothub.portstatus[port]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) ohci_writel(ohci, OHCI_INTR_MIE, &ohci->regs->intrenable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) ohci_readl(ohci, &ohci->regs->intrenable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) msleep(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) usb_hcd_resume_root_hub(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) EXPORT_SYMBOL_GPL(ohci_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) /*-------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) * Generic structure: This gets copied for platform drivers so that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) * individual entries can be overridden as needed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) static const struct hc_driver ohci_hc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) .description = hcd_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) .product_desc = "OHCI Host Controller",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) .hcd_priv_size = sizeof(struct ohci_hcd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) * generic hardware linkage
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) .irq = ohci_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) .flags = HCD_MEMORY | HCD_DMA | HCD_USB11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) * basic lifecycle operations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) .reset = ohci_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) .start = ohci_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) .stop = ohci_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) .shutdown = ohci_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) * managing i/o requests and associated device resources
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) .urb_enqueue = ohci_urb_enqueue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) .urb_dequeue = ohci_urb_dequeue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) .endpoint_disable = ohci_endpoint_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) * scheduling support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) .get_frame_number = ohci_get_frame,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) * root hub support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) .hub_status_data = ohci_hub_status_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) .hub_control = ohci_hub_control,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) .bus_suspend = ohci_bus_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) .bus_resume = ohci_bus_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) .start_port_reset = ohci_start_port_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) void ohci_init_driver(struct hc_driver *drv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) const struct ohci_driver_overrides *over)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) /* Copy the generic table to drv and then apply the overrides */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) *drv = ohci_hc_driver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) if (over) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) drv->product_desc = over->product_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) drv->hcd_priv_size += over->extra_priv_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) if (over->reset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) drv->reset = over->reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) EXPORT_SYMBOL_GPL(ohci_init_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) /*-------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) MODULE_AUTHOR (DRIVER_AUTHOR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) MODULE_DESCRIPTION(DRIVER_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) MODULE_LICENSE ("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) #if defined(CONFIG_ARCH_SA1100) && defined(CONFIG_SA1111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) #include "ohci-sa1111.c"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) #define SA1111_DRIVER ohci_hcd_sa1111_driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) #ifdef CONFIG_USB_OHCI_HCD_PPC_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) #include "ohci-ppc-of.c"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) #define OF_PLATFORM_DRIVER ohci_hcd_ppc_of_driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) #ifdef CONFIG_PPC_PS3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) #include "ohci-ps3.c"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) #define PS3_SYSTEM_BUS_DRIVER ps3_ohci_driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) #ifdef CONFIG_MFD_SM501
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) #include "ohci-sm501.c"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) #define SM501_OHCI_DRIVER ohci_hcd_sm501_driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) #ifdef CONFIG_MFD_TC6393XB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) #include "ohci-tmio.c"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) #define TMIO_OHCI_DRIVER ohci_hcd_tmio_driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) static int __init ohci_hcd_mod_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) int retval = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) if (usb_disabled())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) printk(KERN_INFO "%s: " DRIVER_DESC "\n", hcd_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) pr_debug ("%s: block sizes: ed %zd td %zd\n", hcd_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) sizeof (struct ed), sizeof (struct td));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) set_bit(USB_OHCI_LOADED, &usb_hcds_loaded);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) ohci_debug_root = debugfs_create_dir("ohci", usb_debug_root);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) #ifdef PS3_SYSTEM_BUS_DRIVER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) retval = ps3_ohci_driver_register(&PS3_SYSTEM_BUS_DRIVER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) if (retval < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) goto error_ps3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) #ifdef OF_PLATFORM_DRIVER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) retval = platform_driver_register(&OF_PLATFORM_DRIVER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) if (retval < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) goto error_of_platform;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) #ifdef SA1111_DRIVER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) retval = sa1111_driver_register(&SA1111_DRIVER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) if (retval < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) goto error_sa1111;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) #ifdef SM501_OHCI_DRIVER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) retval = platform_driver_register(&SM501_OHCI_DRIVER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) if (retval < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) goto error_sm501;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) #ifdef TMIO_OHCI_DRIVER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) retval = platform_driver_register(&TMIO_OHCI_DRIVER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) if (retval < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) goto error_tmio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) /* Error path */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) #ifdef TMIO_OHCI_DRIVER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) platform_driver_unregister(&TMIO_OHCI_DRIVER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) error_tmio:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) #ifdef SM501_OHCI_DRIVER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) platform_driver_unregister(&SM501_OHCI_DRIVER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) error_sm501:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) #ifdef SA1111_DRIVER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) sa1111_driver_unregister(&SA1111_DRIVER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) error_sa1111:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) #ifdef OF_PLATFORM_DRIVER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) platform_driver_unregister(&OF_PLATFORM_DRIVER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) error_of_platform:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) #ifdef PS3_SYSTEM_BUS_DRIVER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) ps3_ohci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) error_ps3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) debugfs_remove(ohci_debug_root);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) ohci_debug_root = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) clear_bit(USB_OHCI_LOADED, &usb_hcds_loaded);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) module_init(ohci_hcd_mod_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) static void __exit ohci_hcd_mod_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) #ifdef TMIO_OHCI_DRIVER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) platform_driver_unregister(&TMIO_OHCI_DRIVER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) #ifdef SM501_OHCI_DRIVER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) platform_driver_unregister(&SM501_OHCI_DRIVER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) #ifdef SA1111_DRIVER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) sa1111_driver_unregister(&SA1111_DRIVER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) #ifdef OF_PLATFORM_DRIVER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) platform_driver_unregister(&OF_PLATFORM_DRIVER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) #ifdef PS3_SYSTEM_BUS_DRIVER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) ps3_ohci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) debugfs_remove(ohci_debug_root);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) clear_bit(USB_OHCI_LOADED, &usb_hcds_loaded);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) module_exit(ohci_hcd_mod_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags