^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * MAX3421 Host Controller driver for USB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Author: David Mosberger-Tang <davidm@egauge.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * (C) Copyright 2014 David Mosberger-Tang <davidm@egauge.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * MAX3421 is a chip implementing a USB 2.0 Full-/Low-Speed host
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * controller on a SPI bus.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Based on:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * o MAX3421E datasheet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * https://datasheets.maximintegrated.com/en/ds/MAX3421E.pdf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * o MAX3421E Programming Guide
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * https://www.hdl.co.jp/ftpdata/utl-001/AN3785.pdf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * o gadget/dummy_hcd.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * For USB HCD implementation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * o Arduino MAX3421 driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * https://github.com/felis/USB_Host_Shield_2.0/blob/master/Usb.cpp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * This file is licenced under the GPL v2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * Important note on worst-case (full-speed) packet size constraints
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * (See USB 2.0 Section 5.6.3 and following):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * - control: 64 bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * - isochronous: 1023 bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * - interrupt: 64 bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * - bulk: 64 bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * Since the MAX3421 FIFO size is 64 bytes, we do not have to work about
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * multi-FIFO writes/reads for a single USB packet *except* for isochronous
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * transfers. We don't support isochronous transfers at this time, so we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * just assume that a USB packet always fits into a single FIFO buffer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * NOTE: The June 2006 version of "MAX3421E Programming Guide"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * (AN3785) has conflicting info for the RCVDAVIRQ bit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * The description of RCVDAVIRQ says "The CPU *must* clear
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * this IRQ bit (by writing a 1 to it) before reading the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * RCVFIFO data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * However, the earlier section on "Programming BULK-IN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * Transfers" says * that:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * After the CPU retrieves the data, it clears the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * RCVDAVIRQ bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * The December 2006 version has been corrected and it consistently
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * states the second behavior is the correct one.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * Synchronous SPI transactions sleep so we can't perform any such
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * transactions while holding a spin-lock (and/or while interrupts are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * masked). To achieve this, all SPI transactions are issued from a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * single thread (max3421_spi_thread).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #include <linux/jiffies.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #include <linux/usb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #include <linux/usb/hcd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #include <linux/platform_data/max3421-hcd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define DRIVER_DESC "MAX3421 USB Host-Controller Driver"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define DRIVER_VERSION "1.0"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /* 11-bit counter that wraps around (USB 2.0 Section 8.3.3): */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define USB_MAX_FRAME_NUMBER 0x7ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define USB_MAX_RETRIES 3 /* # of retries before error is reported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * Max. # of times we're willing to retransmit a request immediately in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * resposne to a NAK. Afterwards, we fall back on trying once a frame.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define NAK_MAX_FAST_RETRANSMITS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define POWER_BUDGET 500 /* in mA; use 8 for low-power port testing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /* Port-change mask: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define PORT_C_MASK ((USB_PORT_STAT_C_CONNECTION | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) USB_PORT_STAT_C_ENABLE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) USB_PORT_STAT_C_SUSPEND | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) USB_PORT_STAT_C_OVERCURRENT | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) USB_PORT_STAT_C_RESET) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define MAX3421_GPOUT_COUNT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) enum max3421_rh_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) MAX3421_RH_RESET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) MAX3421_RH_SUSPENDED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) MAX3421_RH_RUNNING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) enum pkt_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) PKT_STATE_SETUP, /* waiting to send setup packet to ctrl pipe */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) PKT_STATE_TRANSFER, /* waiting to xfer transfer_buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) PKT_STATE_TERMINATE /* waiting to terminate control transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) enum scheduling_pass {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) SCHED_PASS_PERIODIC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) SCHED_PASS_NON_PERIODIC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) SCHED_PASS_DONE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /* Bit numbers for max3421_hcd->todo: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) ENABLE_IRQ = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) RESET_HCD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) RESET_PORT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) CHECK_UNLINK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) IOPIN_UPDATE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) struct max3421_dma_buf {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) u8 data[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) struct max3421_hcd {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) struct task_struct *spi_thread;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) enum max3421_rh_state rh_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /* lower 16 bits contain port status, upper 16 bits the change mask: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) u32 port_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) unsigned active:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) struct list_head ep_list; /* list of EP's with work */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) * The following are owned by spi_thread (may be accessed by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) * SPI-thread without acquiring the HCD lock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) u8 rev; /* chip revision */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) u16 frame_number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) * kmalloc'd buffers guaranteed to be in separate (DMA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) * cache-lines:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) struct max3421_dma_buf *tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) struct max3421_dma_buf *rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) * URB we're currently processing. Must not be reset to NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) * unless MAX3421E chip is idle:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) struct urb *curr_urb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) enum scheduling_pass sched_pass;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) int urb_done; /* > 0 -> no errors, < 0: errno */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) size_t curr_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) u8 hien;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) u8 mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) u8 iopins[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) unsigned long todo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #ifdef DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) unsigned long err_stat[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) struct max3421_ep {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) struct usb_host_endpoint *ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) struct list_head ep_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) u32 naks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) u16 last_active; /* frame # this ep was last active */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) enum pkt_state pkt_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) u8 retries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) u8 retransmit; /* packet needs retransmission */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define MAX3421_FIFO_SIZE 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define MAX3421_SPI_DIR_RD 0 /* read register from MAX3421 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define MAX3421_SPI_DIR_WR 1 /* write register to MAX3421 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) /* SPI commands: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define MAX3421_SPI_DIR_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define MAX3421_SPI_REG_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define MAX3421_REG_RCVFIFO 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define MAX3421_REG_SNDFIFO 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define MAX3421_REG_SUDFIFO 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define MAX3421_REG_RCVBC 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define MAX3421_REG_SNDBC 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define MAX3421_REG_USBIRQ 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define MAX3421_REG_USBIEN 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define MAX3421_REG_USBCTL 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define MAX3421_REG_CPUCTL 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define MAX3421_REG_PINCTL 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define MAX3421_REG_REVISION 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define MAX3421_REG_IOPINS1 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define MAX3421_REG_IOPINS2 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define MAX3421_REG_GPINIRQ 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define MAX3421_REG_GPINIEN 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define MAX3421_REG_GPINPOL 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define MAX3421_REG_HIRQ 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define MAX3421_REG_HIEN 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define MAX3421_REG_MODE 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define MAX3421_REG_PERADDR 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define MAX3421_REG_HCTL 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define MAX3421_REG_HXFR 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define MAX3421_REG_HRSL 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) MAX3421_USBIRQ_OSCOKIRQ_BIT = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) MAX3421_USBIRQ_NOVBUSIRQ_BIT = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) MAX3421_USBIRQ_VBUSIRQ_BIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) MAX3421_CPUCTL_IE_BIT = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) MAX3421_CPUCTL_PULSEWID0_BIT = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) MAX3421_CPUCTL_PULSEWID1_BIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) MAX3421_USBCTL_PWRDOWN_BIT = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) MAX3421_USBCTL_CHIPRES_BIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) MAX3421_PINCTL_GPXA_BIT = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) MAX3421_PINCTL_GPXB_BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) MAX3421_PINCTL_POSINT_BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) MAX3421_PINCTL_INTLEVEL_BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) MAX3421_PINCTL_FDUPSPI_BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) MAX3421_PINCTL_EP0INAK_BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) MAX3421_PINCTL_EP2INAK_BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) MAX3421_PINCTL_EP3INAK_BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) MAX3421_HI_BUSEVENT_BIT = 0, /* bus-reset/-resume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) MAX3421_HI_RWU_BIT, /* remote wakeup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) MAX3421_HI_RCVDAV_BIT, /* receive FIFO data available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) MAX3421_HI_SNDBAV_BIT, /* send buffer available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) MAX3421_HI_SUSDN_BIT, /* suspend operation done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) MAX3421_HI_CONDET_BIT, /* peripheral connect/disconnect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) MAX3421_HI_FRAME_BIT, /* frame generator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) MAX3421_HI_HXFRDN_BIT, /* host transfer done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) MAX3421_HCTL_BUSRST_BIT = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) MAX3421_HCTL_FRMRST_BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) MAX3421_HCTL_SAMPLEBUS_BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) MAX3421_HCTL_SIGRSM_BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) MAX3421_HCTL_RCVTOG0_BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) MAX3421_HCTL_RCVTOG1_BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) MAX3421_HCTL_SNDTOG0_BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) MAX3421_HCTL_SNDTOG1_BIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) MAX3421_MODE_HOST_BIT = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) MAX3421_MODE_LOWSPEED_BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) MAX3421_MODE_HUBPRE_BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) MAX3421_MODE_SOFKAENAB_BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) MAX3421_MODE_SEPIRQ_BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) MAX3421_MODE_DELAYISO_BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) MAX3421_MODE_DMPULLDN_BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) MAX3421_MODE_DPPULLDN_BIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) MAX3421_HRSL_OK = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) MAX3421_HRSL_BUSY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) MAX3421_HRSL_BADREQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) MAX3421_HRSL_UNDEF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) MAX3421_HRSL_NAK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) MAX3421_HRSL_STALL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) MAX3421_HRSL_TOGERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) MAX3421_HRSL_WRONGPID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) MAX3421_HRSL_BADBC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) MAX3421_HRSL_PIDERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) MAX3421_HRSL_PKTERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) MAX3421_HRSL_CRCERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) MAX3421_HRSL_KERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) MAX3421_HRSL_JERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) MAX3421_HRSL_TIMEOUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) MAX3421_HRSL_BABBLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) MAX3421_HRSL_RESULT_MASK = 0xf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) MAX3421_HRSL_RCVTOGRD_BIT = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) MAX3421_HRSL_SNDTOGRD_BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) MAX3421_HRSL_KSTATUS_BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) MAX3421_HRSL_JSTATUS_BIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) /* Return same error-codes as ohci.h:cc_to_error: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) static const int hrsl_to_error[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) [MAX3421_HRSL_OK] = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) [MAX3421_HRSL_BUSY] = -EINVAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) [MAX3421_HRSL_BADREQ] = -EINVAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) [MAX3421_HRSL_UNDEF] = -EINVAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) [MAX3421_HRSL_NAK] = -EAGAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) [MAX3421_HRSL_STALL] = -EPIPE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) [MAX3421_HRSL_TOGERR] = -EILSEQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) [MAX3421_HRSL_WRONGPID] = -EPROTO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) [MAX3421_HRSL_BADBC] = -EREMOTEIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) [MAX3421_HRSL_PIDERR] = -EPROTO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) [MAX3421_HRSL_PKTERR] = -EPROTO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) [MAX3421_HRSL_CRCERR] = -EILSEQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) [MAX3421_HRSL_KERR] = -EIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) [MAX3421_HRSL_JERR] = -EIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) [MAX3421_HRSL_TIMEOUT] = -ETIME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) [MAX3421_HRSL_BABBLE] = -EOVERFLOW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) * See https://www.beyondlogic.org/usbnutshell/usb4.shtml#Control for a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) * reasonable overview of how control transfers use the the IN/OUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) * tokens.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define MAX3421_HXFR_BULK_IN(ep) (0x00 | (ep)) /* bulk or interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define MAX3421_HXFR_SETUP 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define MAX3421_HXFR_BULK_OUT(ep) (0x20 | (ep)) /* bulk or interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define MAX3421_HXFR_ISO_IN(ep) (0x40 | (ep))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define MAX3421_HXFR_ISO_OUT(ep) (0x60 | (ep))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define MAX3421_HXFR_HS_IN 0x80 /* handshake in */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define MAX3421_HXFR_HS_OUT 0xa0 /* handshake out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define field(val, bit) ((val) << (bit))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) static inline s16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) frame_diff(u16 left, u16 right)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) return ((unsigned) (left - right)) % (USB_MAX_FRAME_NUMBER + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) static inline struct max3421_hcd *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) hcd_to_max3421(struct usb_hcd *hcd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) return (struct max3421_hcd *) hcd->hcd_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) static inline struct usb_hcd *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) max3421_to_hcd(struct max3421_hcd *max3421_hcd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) return container_of((void *) max3421_hcd, struct usb_hcd, hcd_priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) static u8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) spi_rd8(struct usb_hcd *hcd, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) struct max3421_hcd *max3421_hcd = hcd_to_max3421(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) struct spi_device *spi = to_spi_device(hcd->self.controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) struct spi_transfer transfer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) struct spi_message msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) memset(&transfer, 0, sizeof(transfer));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) spi_message_init(&msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) max3421_hcd->tx->data[0] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) (field(reg, MAX3421_SPI_REG_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) field(MAX3421_SPI_DIR_RD, MAX3421_SPI_DIR_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) transfer.tx_buf = max3421_hcd->tx->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) transfer.rx_buf = max3421_hcd->rx->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) transfer.len = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) spi_message_add_tail(&transfer, &msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) spi_sync(spi, &msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) return max3421_hcd->rx->data[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) spi_wr8(struct usb_hcd *hcd, unsigned int reg, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) struct spi_device *spi = to_spi_device(hcd->self.controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) struct max3421_hcd *max3421_hcd = hcd_to_max3421(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) struct spi_transfer transfer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) struct spi_message msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) memset(&transfer, 0, sizeof(transfer));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) spi_message_init(&msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) max3421_hcd->tx->data[0] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) (field(reg, MAX3421_SPI_REG_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) field(MAX3421_SPI_DIR_WR, MAX3421_SPI_DIR_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) max3421_hcd->tx->data[1] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) transfer.tx_buf = max3421_hcd->tx->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) transfer.len = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) spi_message_add_tail(&transfer, &msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) spi_sync(spi, &msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) spi_rd_buf(struct usb_hcd *hcd, unsigned int reg, void *buf, size_t len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) struct spi_device *spi = to_spi_device(hcd->self.controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) struct max3421_hcd *max3421_hcd = hcd_to_max3421(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) struct spi_transfer transfer[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) struct spi_message msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) memset(transfer, 0, sizeof(transfer));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) spi_message_init(&msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) max3421_hcd->tx->data[0] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) (field(reg, MAX3421_SPI_REG_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) field(MAX3421_SPI_DIR_RD, MAX3421_SPI_DIR_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) transfer[0].tx_buf = max3421_hcd->tx->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) transfer[0].len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) transfer[1].rx_buf = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) transfer[1].len = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) spi_message_add_tail(&transfer[0], &msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) spi_message_add_tail(&transfer[1], &msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) spi_sync(spi, &msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) spi_wr_buf(struct usb_hcd *hcd, unsigned int reg, void *buf, size_t len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) struct spi_device *spi = to_spi_device(hcd->self.controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) struct max3421_hcd *max3421_hcd = hcd_to_max3421(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) struct spi_transfer transfer[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) struct spi_message msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) memset(transfer, 0, sizeof(transfer));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) spi_message_init(&msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) max3421_hcd->tx->data[0] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) (field(reg, MAX3421_SPI_REG_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) field(MAX3421_SPI_DIR_WR, MAX3421_SPI_DIR_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) transfer[0].tx_buf = max3421_hcd->tx->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) transfer[0].len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) transfer[1].tx_buf = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) transfer[1].len = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) spi_message_add_tail(&transfer[0], &msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) spi_message_add_tail(&transfer[1], &msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) spi_sync(spi, &msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) * Figure out the correct setting for the LOWSPEED and HUBPRE mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) * bits. The HUBPRE bit needs to be set when MAX3421E operates at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) * full speed, but it's talking to a low-speed device (i.e., through a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) * hub). Setting that bit ensures that every low-speed packet is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) * preceded by a full-speed PRE PID. Possible configurations:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) * Hub speed: Device speed: => LOWSPEED bit: HUBPRE bit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) * FULL FULL => 0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) * FULL LOW => 1 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) * LOW LOW => 1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) * LOW FULL => 1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) max3421_set_speed(struct usb_hcd *hcd, struct usb_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) struct max3421_hcd *max3421_hcd = hcd_to_max3421(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) u8 mode_lowspeed, mode_hubpre, mode = max3421_hcd->mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) mode_lowspeed = BIT(MAX3421_MODE_LOWSPEED_BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) mode_hubpre = BIT(MAX3421_MODE_HUBPRE_BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) if (max3421_hcd->port_status & USB_PORT_STAT_LOW_SPEED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) mode |= mode_lowspeed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) mode &= ~mode_hubpre;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) } else if (dev->speed == USB_SPEED_LOW) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) mode |= mode_lowspeed | mode_hubpre;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) mode &= ~(mode_lowspeed | mode_hubpre);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) if (mode != max3421_hcd->mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) max3421_hcd->mode = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) spi_wr8(hcd, MAX3421_REG_MODE, max3421_hcd->mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) * Caller must NOT hold HCD spinlock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) max3421_set_address(struct usb_hcd *hcd, struct usb_device *dev, int epnum)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) int rcvtog, sndtog;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) u8 hctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) /* setup new endpoint's toggle bits: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) rcvtog = usb_gettoggle(dev, epnum, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) sndtog = usb_gettoggle(dev, epnum, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) hctl = (BIT(rcvtog + MAX3421_HCTL_RCVTOG0_BIT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) BIT(sndtog + MAX3421_HCTL_SNDTOG0_BIT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) spi_wr8(hcd, MAX3421_REG_HCTL, hctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) * Note: devnum for one and the same device can change during
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) * address-assignment so it's best to just always load the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) * address whenever the end-point changed/was forced.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) spi_wr8(hcd, MAX3421_REG_PERADDR, dev->devnum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) max3421_ctrl_setup(struct usb_hcd *hcd, struct urb *urb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) spi_wr_buf(hcd, MAX3421_REG_SUDFIFO, urb->setup_packet, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) return MAX3421_HXFR_SETUP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) max3421_transfer_in(struct usb_hcd *hcd, struct urb *urb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) struct max3421_hcd *max3421_hcd = hcd_to_max3421(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) int epnum = usb_pipeendpoint(urb->pipe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) max3421_hcd->curr_len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) max3421_hcd->hien |= BIT(MAX3421_HI_RCVDAV_BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) return MAX3421_HXFR_BULK_IN(epnum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) max3421_transfer_out(struct usb_hcd *hcd, struct urb *urb, int fast_retransmit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) struct spi_device *spi = to_spi_device(hcd->self.controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) struct max3421_hcd *max3421_hcd = hcd_to_max3421(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) int epnum = usb_pipeendpoint(urb->pipe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) u32 max_packet;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) void *src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) src = urb->transfer_buffer + urb->actual_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) if (fast_retransmit) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) if (max3421_hcd->rev == 0x12) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) /* work around rev 0x12 bug: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) spi_wr8(hcd, MAX3421_REG_SNDBC, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) spi_wr8(hcd, MAX3421_REG_SNDFIFO, ((u8 *) src)[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) spi_wr8(hcd, MAX3421_REG_SNDBC, max3421_hcd->curr_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) return MAX3421_HXFR_BULK_OUT(epnum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) max_packet = usb_maxpacket(urb->dev, urb->pipe, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) if (max_packet > MAX3421_FIFO_SIZE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) * We do not support isochronous transfers at this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) * time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) dev_err(&spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) "%s: packet-size of %u too big (limit is %u bytes)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) __func__, max_packet, MAX3421_FIFO_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) max3421_hcd->urb_done = -EMSGSIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) return -EMSGSIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) max3421_hcd->curr_len = min((urb->transfer_buffer_length -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) urb->actual_length), max_packet);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) spi_wr_buf(hcd, MAX3421_REG_SNDFIFO, src, max3421_hcd->curr_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) spi_wr8(hcd, MAX3421_REG_SNDBC, max3421_hcd->curr_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) return MAX3421_HXFR_BULK_OUT(epnum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) * Issue the next host-transfer command.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) * Caller must NOT hold HCD spinlock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) max3421_next_transfer(struct usb_hcd *hcd, int fast_retransmit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) struct max3421_hcd *max3421_hcd = hcd_to_max3421(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) struct urb *urb = max3421_hcd->curr_urb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) struct max3421_ep *max3421_ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) int cmd = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) if (!urb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) return; /* nothing to do */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) max3421_ep = urb->ep->hcpriv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) switch (max3421_ep->pkt_state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) case PKT_STATE_SETUP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) cmd = max3421_ctrl_setup(hcd, urb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) case PKT_STATE_TRANSFER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) if (usb_urb_dir_in(urb))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) cmd = max3421_transfer_in(hcd, urb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) cmd = max3421_transfer_out(hcd, urb, fast_retransmit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) case PKT_STATE_TERMINATE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) * IN transfers are terminated with HS_OUT token,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) * OUT transfers with HS_IN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) if (usb_urb_dir_in(urb))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) cmd = MAX3421_HXFR_HS_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) cmd = MAX3421_HXFR_HS_IN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) if (cmd < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) /* issue the command and wait for host-xfer-done interrupt: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) spi_wr8(hcd, MAX3421_REG_HXFR, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) max3421_hcd->hien |= BIT(MAX3421_HI_HXFRDN_BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) * Find the next URB to process and start its execution.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) * At this time, we do not anticipate ever connecting a USB hub to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) * MAX3421 chip, so at most USB device can be connected and we can use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) * a simplistic scheduler: at the start of a frame, schedule all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) * periodic transfers. Once that is done, use the remainder of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) * frame to process non-periodic (bulk & control) transfers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) * Preconditions:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) * o Caller must NOT hold HCD spinlock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) * o max3421_hcd->curr_urb MUST BE NULL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) * o MAX3421E chip must be idle.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) max3421_select_and_start_urb(struct usb_hcd *hcd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) struct spi_device *spi = to_spi_device(hcd->self.controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) struct max3421_hcd *max3421_hcd = hcd_to_max3421(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) struct urb *urb, *curr_urb = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) struct max3421_ep *max3421_ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) int epnum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) struct usb_host_endpoint *ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) struct list_head *pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) spin_lock_irqsave(&max3421_hcd->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) for (;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) max3421_hcd->sched_pass < SCHED_PASS_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) ++max3421_hcd->sched_pass)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) list_for_each(pos, &max3421_hcd->ep_list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) urb = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) max3421_ep = container_of(pos, struct max3421_ep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) ep_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) ep = max3421_ep->ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) switch (usb_endpoint_type(&ep->desc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) case USB_ENDPOINT_XFER_ISOC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) case USB_ENDPOINT_XFER_INT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) if (max3421_hcd->sched_pass !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) SCHED_PASS_PERIODIC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) case USB_ENDPOINT_XFER_CONTROL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) case USB_ENDPOINT_XFER_BULK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) if (max3421_hcd->sched_pass !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) SCHED_PASS_NON_PERIODIC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) if (list_empty(&ep->urb_list))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) continue; /* nothing to do */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) urb = list_first_entry(&ep->urb_list, struct urb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) urb_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) if (urb->unlinked) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) dev_dbg(&spi->dev, "%s: URB %p unlinked=%d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) __func__, urb, urb->unlinked);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) max3421_hcd->curr_urb = urb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) max3421_hcd->urb_done = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) spin_unlock_irqrestore(&max3421_hcd->lock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) switch (usb_endpoint_type(&ep->desc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) case USB_ENDPOINT_XFER_CONTROL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) * Allow one control transaction per
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) * frame per endpoint:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) if (frame_diff(max3421_ep->last_active,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) max3421_hcd->frame_number) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) case USB_ENDPOINT_XFER_BULK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) if (max3421_ep->retransmit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) && (frame_diff(max3421_ep->last_active,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) max3421_hcd->frame_number)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) == 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) * We already tried this EP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) * during this frame and got a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) * NAK or error; wait for next frame
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) case USB_ENDPOINT_XFER_ISOC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) case USB_ENDPOINT_XFER_INT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) if (frame_diff(max3421_hcd->frame_number,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) max3421_ep->last_active)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) < urb->interval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) * We already processed this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) * end-point in the current
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) * frame
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) /* move current ep to tail: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) list_move_tail(pos, &max3421_hcd->ep_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) curr_urb = urb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) if (!curr_urb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) spin_unlock_irqrestore(&max3421_hcd->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) urb = max3421_hcd->curr_urb = curr_urb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) epnum = usb_endpoint_num(&urb->ep->desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) if (max3421_ep->retransmit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) /* restart (part of) a USB transaction: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) max3421_ep->retransmit = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) /* start USB transaction: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) if (usb_endpoint_xfer_control(&ep->desc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) * See USB 2.0 spec section 8.6.1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) * Initialization via SETUP Token:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) usb_settoggle(urb->dev, epnum, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) usb_settoggle(urb->dev, epnum, 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) max3421_ep->pkt_state = PKT_STATE_SETUP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) max3421_ep->pkt_state = PKT_STATE_TRANSFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) spin_unlock_irqrestore(&max3421_hcd->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) max3421_ep->last_active = max3421_hcd->frame_number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) max3421_set_address(hcd, urb->dev, epnum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) max3421_set_speed(hcd, urb->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) max3421_next_transfer(hcd, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) * Check all endpoints for URBs that got unlinked.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) * Caller must NOT hold HCD spinlock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) max3421_check_unlink(struct usb_hcd *hcd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) struct spi_device *spi = to_spi_device(hcd->self.controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) struct max3421_hcd *max3421_hcd = hcd_to_max3421(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) struct max3421_ep *max3421_ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) struct usb_host_endpoint *ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) struct urb *urb, *next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) int retval = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) spin_lock_irqsave(&max3421_hcd->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) list_for_each_entry(max3421_ep, &max3421_hcd->ep_list, ep_list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) ep = max3421_ep->ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) list_for_each_entry_safe(urb, next, &ep->urb_list, urb_list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) if (urb->unlinked) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) retval = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) dev_dbg(&spi->dev, "%s: URB %p unlinked=%d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) __func__, urb, urb->unlinked);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) usb_hcd_unlink_urb_from_ep(hcd, urb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) spin_unlock_irqrestore(&max3421_hcd->lock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) usb_hcd_giveback_urb(hcd, urb, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) spin_lock_irqsave(&max3421_hcd->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) spin_unlock_irqrestore(&max3421_hcd->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) * Caller must NOT hold HCD spinlock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) max3421_slow_retransmit(struct usb_hcd *hcd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) struct max3421_hcd *max3421_hcd = hcd_to_max3421(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) struct urb *urb = max3421_hcd->curr_urb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) struct max3421_ep *max3421_ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) max3421_ep = urb->ep->hcpriv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) max3421_ep->retransmit = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) max3421_hcd->curr_urb = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) * Caller must NOT hold HCD spinlock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) max3421_recv_data_available(struct usb_hcd *hcd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) struct max3421_hcd *max3421_hcd = hcd_to_max3421(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) struct urb *urb = max3421_hcd->curr_urb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) size_t remaining, transfer_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) u8 rcvbc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) rcvbc = spi_rd8(hcd, MAX3421_REG_RCVBC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) if (rcvbc > MAX3421_FIFO_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) rcvbc = MAX3421_FIFO_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) if (urb->actual_length >= urb->transfer_buffer_length)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) remaining = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) remaining = urb->transfer_buffer_length - urb->actual_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) transfer_size = rcvbc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) if (transfer_size > remaining)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) transfer_size = remaining;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) if (transfer_size > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) void *dst = urb->transfer_buffer + urb->actual_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) spi_rd_buf(hcd, MAX3421_REG_RCVFIFO, dst, transfer_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) urb->actual_length += transfer_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) max3421_hcd->curr_len = transfer_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) /* ack the RCVDAV irq now that the FIFO has been read: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) spi_wr8(hcd, MAX3421_REG_HIRQ, BIT(MAX3421_HI_RCVDAV_BIT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) max3421_handle_error(struct usb_hcd *hcd, u8 hrsl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) struct spi_device *spi = to_spi_device(hcd->self.controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) struct max3421_hcd *max3421_hcd = hcd_to_max3421(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) u8 result_code = hrsl & MAX3421_HRSL_RESULT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) struct urb *urb = max3421_hcd->curr_urb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) struct max3421_ep *max3421_ep = urb->ep->hcpriv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) int switch_sndfifo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) * If an OUT command results in any response other than OK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) * (i.e., error or NAK), we have to perform a dummy-write to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) * SNDBC so the FIFO gets switched back to us. Otherwise, we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) * get out of sync with the SNDFIFO double buffer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) switch_sndfifo = (max3421_ep->pkt_state == PKT_STATE_TRANSFER &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) usb_urb_dir_out(urb));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) switch (result_code) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) case MAX3421_HRSL_OK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) return; /* this shouldn't happen */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) case MAX3421_HRSL_WRONGPID: /* received wrong PID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) case MAX3421_HRSL_BUSY: /* SIE busy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) case MAX3421_HRSL_BADREQ: /* bad val in HXFR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) case MAX3421_HRSL_UNDEF: /* reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) case MAX3421_HRSL_KERR: /* K-state instead of response */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) case MAX3421_HRSL_JERR: /* J-state instead of response */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) * packet experienced an error that we cannot recover
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) * from; report error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) max3421_hcd->urb_done = hrsl_to_error[result_code];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) dev_dbg(&spi->dev, "%s: unexpected error HRSL=0x%02x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) __func__, hrsl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) case MAX3421_HRSL_TOGERR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) if (usb_urb_dir_in(urb))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) ; /* don't do anything (device will switch toggle) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) /* flip the send toggle bit: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) int sndtog = (hrsl >> MAX3421_HRSL_SNDTOGRD_BIT) & 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) sndtog ^= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) spi_wr8(hcd, MAX3421_REG_HCTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) BIT(sndtog + MAX3421_HCTL_SNDTOG0_BIT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) case MAX3421_HRSL_BADBC: /* bad byte count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) case MAX3421_HRSL_PIDERR: /* received PID is corrupted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) case MAX3421_HRSL_PKTERR: /* packet error (stuff, EOP) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) case MAX3421_HRSL_CRCERR: /* CRC error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) case MAX3421_HRSL_BABBLE: /* device talked too long */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) case MAX3421_HRSL_TIMEOUT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) if (max3421_ep->retries++ < USB_MAX_RETRIES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) /* retry the packet again in the next frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) max3421_slow_retransmit(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) /* Based on ohci.h cc_to_err[]: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) max3421_hcd->urb_done = hrsl_to_error[result_code];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) dev_dbg(&spi->dev, "%s: unexpected error HRSL=0x%02x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) __func__, hrsl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) case MAX3421_HRSL_STALL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) dev_dbg(&spi->dev, "%s: unexpected error HRSL=0x%02x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) __func__, hrsl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) max3421_hcd->urb_done = hrsl_to_error[result_code];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) case MAX3421_HRSL_NAK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) * Device wasn't ready for data or has no data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) * available: retry the packet again.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) if (max3421_ep->naks++ < NAK_MAX_FAST_RETRANSMITS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) max3421_next_transfer(hcd, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) switch_sndfifo = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) max3421_slow_retransmit(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) if (switch_sndfifo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) spi_wr8(hcd, MAX3421_REG_SNDBC, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) * Caller must NOT hold HCD spinlock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) max3421_transfer_in_done(struct usb_hcd *hcd, struct urb *urb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) struct spi_device *spi = to_spi_device(hcd->self.controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) struct max3421_hcd *max3421_hcd = hcd_to_max3421(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) u32 max_packet;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) if (urb->actual_length >= urb->transfer_buffer_length)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) return 1; /* read is complete, so we're done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) * USB 2.0 Section 5.3.2 Pipes: packets must be full size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) * except for last one.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) max_packet = usb_maxpacket(urb->dev, urb->pipe, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) if (max_packet > MAX3421_FIFO_SIZE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) * We do not support isochronous transfers at this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) * time...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) dev_err(&spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) "%s: packet-size of %u too big (limit is %u bytes)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) __func__, max_packet, MAX3421_FIFO_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) if (max3421_hcd->curr_len < max_packet) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) if (urb->transfer_flags & URB_SHORT_NOT_OK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) * remaining > 0 and received an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) * unexpected partial packet ->
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) * error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) return -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) /* short read, but it's OK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) return 0; /* not done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) * Caller must NOT hold HCD spinlock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) max3421_transfer_out_done(struct usb_hcd *hcd, struct urb *urb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) struct max3421_hcd *max3421_hcd = hcd_to_max3421(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) urb->actual_length += max3421_hcd->curr_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) if (urb->actual_length < urb->transfer_buffer_length)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) if (urb->transfer_flags & URB_ZERO_PACKET) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) * Some hardware needs a zero-size packet at the end
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) * of a bulk-out transfer if the last transfer was a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) * full-sized packet (i.e., such hardware use <
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) * max_packet as an indicator that the end of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) * packet has been reached).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) u32 max_packet = usb_maxpacket(urb->dev, urb->pipe, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) if (max3421_hcd->curr_len == max_packet)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) * Caller must NOT hold HCD spinlock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) max3421_host_transfer_done(struct usb_hcd *hcd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) struct max3421_hcd *max3421_hcd = hcd_to_max3421(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) struct urb *urb = max3421_hcd->curr_urb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) struct max3421_ep *max3421_ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) u8 result_code, hrsl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) int urb_done = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) max3421_hcd->hien &= ~(BIT(MAX3421_HI_HXFRDN_BIT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) BIT(MAX3421_HI_RCVDAV_BIT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) hrsl = spi_rd8(hcd, MAX3421_REG_HRSL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) result_code = hrsl & MAX3421_HRSL_RESULT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) #ifdef DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) ++max3421_hcd->err_stat[result_code];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) max3421_ep = urb->ep->hcpriv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) if (unlikely(result_code != MAX3421_HRSL_OK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) max3421_handle_error(hcd, hrsl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) max3421_ep->naks = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) max3421_ep->retries = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) switch (max3421_ep->pkt_state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) case PKT_STATE_SETUP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) if (urb->transfer_buffer_length > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) max3421_ep->pkt_state = PKT_STATE_TRANSFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) max3421_ep->pkt_state = PKT_STATE_TERMINATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) case PKT_STATE_TRANSFER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) if (usb_urb_dir_in(urb))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) urb_done = max3421_transfer_in_done(hcd, urb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) urb_done = max3421_transfer_out_done(hcd, urb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) if (urb_done > 0 && usb_pipetype(urb->pipe) == PIPE_CONTROL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) * We aren't really done - we still need to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) * terminate the control transfer:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) max3421_hcd->urb_done = urb_done = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) max3421_ep->pkt_state = PKT_STATE_TERMINATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) case PKT_STATE_TERMINATE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) urb_done = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) if (urb_done)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) max3421_hcd->urb_done = urb_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) max3421_next_transfer(hcd, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) * Caller must NOT hold HCD spinlock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) max3421_detect_conn(struct usb_hcd *hcd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) struct max3421_hcd *max3421_hcd = hcd_to_max3421(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) unsigned int jk, have_conn = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) u32 old_port_status, chg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) u8 hrsl, mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) hrsl = spi_rd8(hcd, MAX3421_REG_HRSL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) jk = ((((hrsl >> MAX3421_HRSL_JSTATUS_BIT) & 1) << 0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) (((hrsl >> MAX3421_HRSL_KSTATUS_BIT) & 1) << 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) mode = max3421_hcd->mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) switch (jk) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) case 0x0: /* SE0: disconnect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) * Turn off SOFKAENAB bit to avoid getting interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) * every milli-second:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) mode &= ~BIT(MAX3421_MODE_SOFKAENAB_BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) case 0x1: /* J=0,K=1: low-speed (in full-speed or vice versa) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) case 0x2: /* J=1,K=0: full-speed (in full-speed or vice versa) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) if (jk == 0x2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) /* need to switch to the other speed: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) mode ^= BIT(MAX3421_MODE_LOWSPEED_BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) /* turn on SOFKAENAB bit: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) mode |= BIT(MAX3421_MODE_SOFKAENAB_BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) have_conn = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) case 0x3: /* illegal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) max3421_hcd->mode = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) spi_wr8(hcd, MAX3421_REG_MODE, max3421_hcd->mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) spin_lock_irqsave(&max3421_hcd->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) old_port_status = max3421_hcd->port_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) if (have_conn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) max3421_hcd->port_status |= USB_PORT_STAT_CONNECTION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) max3421_hcd->port_status &= ~USB_PORT_STAT_CONNECTION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) if (mode & BIT(MAX3421_MODE_LOWSPEED_BIT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) max3421_hcd->port_status |= USB_PORT_STAT_LOW_SPEED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) max3421_hcd->port_status &= ~USB_PORT_STAT_LOW_SPEED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) chg = (old_port_status ^ max3421_hcd->port_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) max3421_hcd->port_status |= chg << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) spin_unlock_irqrestore(&max3421_hcd->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) static irqreturn_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) max3421_irq_handler(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) struct usb_hcd *hcd = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) struct spi_device *spi = to_spi_device(hcd->self.controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) struct max3421_hcd *max3421_hcd = hcd_to_max3421(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) if (max3421_hcd->spi_thread &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) max3421_hcd->spi_thread->state != TASK_RUNNING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) wake_up_process(max3421_hcd->spi_thread);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) if (!test_and_set_bit(ENABLE_IRQ, &max3421_hcd->todo))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) disable_irq_nosync(spi->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) #ifdef DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) dump_eps(struct usb_hcd *hcd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) struct max3421_hcd *max3421_hcd = hcd_to_max3421(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) struct max3421_ep *max3421_ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) struct usb_host_endpoint *ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) char ubuf[512], *dp, *end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) struct urb *urb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) int epnum, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) spin_lock_irqsave(&max3421_hcd->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) list_for_each_entry(max3421_ep, &max3421_hcd->ep_list, ep_list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) ep = max3421_ep->ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) dp = ubuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) end = dp + sizeof(ubuf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) *dp = '\0';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) list_for_each_entry(urb, &ep->urb_list, urb_list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) ret = snprintf(dp, end - dp, " %p(%d.%s %d/%d)", urb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) usb_pipetype(urb->pipe),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) usb_urb_dir_in(urb) ? "IN" : "OUT",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) urb->actual_length,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) urb->transfer_buffer_length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) if (ret < 0 || ret >= end - dp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) break; /* error or buffer full */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) dp += ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) epnum = usb_endpoint_num(&ep->desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) pr_info("EP%0u %u lst %04u rtr %u nak %6u rxmt %u: %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) epnum, max3421_ep->pkt_state, max3421_ep->last_active,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) max3421_ep->retries, max3421_ep->naks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) max3421_ep->retransmit, ubuf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) spin_unlock_irqrestore(&max3421_hcd->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) #endif /* DEBUG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) /* Return zero if no work was performed, 1 otherwise. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) max3421_handle_irqs(struct usb_hcd *hcd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) struct max3421_hcd *max3421_hcd = hcd_to_max3421(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) u32 chg, old_port_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) u8 hirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) * Read and ack pending interrupts (CPU must never
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) * clear SNDBAV directly and RCVDAV must be cleared by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) * max3421_recv_data_available()!):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) hirq = spi_rd8(hcd, MAX3421_REG_HIRQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) hirq &= max3421_hcd->hien;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) if (!hirq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) spi_wr8(hcd, MAX3421_REG_HIRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) hirq & ~(BIT(MAX3421_HI_SNDBAV_BIT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) BIT(MAX3421_HI_RCVDAV_BIT)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) if (hirq & BIT(MAX3421_HI_FRAME_BIT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) max3421_hcd->frame_number = ((max3421_hcd->frame_number + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) & USB_MAX_FRAME_NUMBER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) max3421_hcd->sched_pass = SCHED_PASS_PERIODIC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) if (hirq & BIT(MAX3421_HI_RCVDAV_BIT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) max3421_recv_data_available(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) if (hirq & BIT(MAX3421_HI_HXFRDN_BIT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) max3421_host_transfer_done(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) if (hirq & BIT(MAX3421_HI_CONDET_BIT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) max3421_detect_conn(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) * Now process interrupts that may affect HCD state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) * other than the end-points:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) spin_lock_irqsave(&max3421_hcd->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) old_port_status = max3421_hcd->port_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) if (hirq & BIT(MAX3421_HI_BUSEVENT_BIT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) if (max3421_hcd->port_status & USB_PORT_STAT_RESET) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) /* BUSEVENT due to completion of Bus Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) max3421_hcd->port_status &= ~USB_PORT_STAT_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) max3421_hcd->port_status |= USB_PORT_STAT_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) /* BUSEVENT due to completion of Bus Resume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) pr_info("%s: BUSEVENT Bus Resume Done\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) if (hirq & BIT(MAX3421_HI_RWU_BIT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) pr_info("%s: RWU\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) if (hirq & BIT(MAX3421_HI_SUSDN_BIT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) pr_info("%s: SUSDN\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) chg = (old_port_status ^ max3421_hcd->port_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) max3421_hcd->port_status |= chg << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) spin_unlock_irqrestore(&max3421_hcd->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) #ifdef DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) static unsigned long last_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) char sbuf[16 * 16], *dp, *end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) if (time_after(jiffies, last_time + 5*HZ)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) dp = sbuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) end = sbuf + sizeof(sbuf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) *dp = '\0';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) for (i = 0; i < 16; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) int ret = snprintf(dp, end - dp, " %lu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) max3421_hcd->err_stat[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) if (ret < 0 || ret >= end - dp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) break; /* error or buffer full */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) dp += ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) pr_info("%s: hrsl_stats %s\n", __func__, sbuf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) memset(max3421_hcd->err_stat, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) sizeof(max3421_hcd->err_stat));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) last_time = jiffies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) dump_eps(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) max3421_reset_hcd(struct usb_hcd *hcd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) struct spi_device *spi = to_spi_device(hcd->self.controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) struct max3421_hcd *max3421_hcd = hcd_to_max3421(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) int timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) /* perform a chip reset and wait for OSCIRQ signal to appear: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) spi_wr8(hcd, MAX3421_REG_USBCTL, BIT(MAX3421_USBCTL_CHIPRES_BIT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) /* clear reset: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) spi_wr8(hcd, MAX3421_REG_USBCTL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) timeout = 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) while (1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) if (spi_rd8(hcd, MAX3421_REG_USBIRQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) & BIT(MAX3421_USBIRQ_OSCOKIRQ_BIT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) if (--timeout < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) dev_err(&spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) "timed out waiting for oscillator OK signal");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) cond_resched();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) * Turn on host mode, automatic generation of SOF packets, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) * enable pull-down registers on DM/DP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) max3421_hcd->mode = (BIT(MAX3421_MODE_HOST_BIT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) BIT(MAX3421_MODE_SOFKAENAB_BIT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) BIT(MAX3421_MODE_DMPULLDN_BIT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) BIT(MAX3421_MODE_DPPULLDN_BIT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) spi_wr8(hcd, MAX3421_REG_MODE, max3421_hcd->mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) /* reset frame-number: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) max3421_hcd->frame_number = USB_MAX_FRAME_NUMBER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) spi_wr8(hcd, MAX3421_REG_HCTL, BIT(MAX3421_HCTL_FRMRST_BIT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) /* sample the state of the D+ and D- lines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) spi_wr8(hcd, MAX3421_REG_HCTL, BIT(MAX3421_HCTL_SAMPLEBUS_BIT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) max3421_detect_conn(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) /* enable frame, connection-detected, and bus-event interrupts: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) max3421_hcd->hien = (BIT(MAX3421_HI_FRAME_BIT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) BIT(MAX3421_HI_CONDET_BIT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) BIT(MAX3421_HI_BUSEVENT_BIT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) spi_wr8(hcd, MAX3421_REG_HIEN, max3421_hcd->hien);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) /* enable interrupts: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) spi_wr8(hcd, MAX3421_REG_CPUCTL, BIT(MAX3421_CPUCTL_IE_BIT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) max3421_urb_done(struct usb_hcd *hcd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) struct max3421_hcd *max3421_hcd = hcd_to_max3421(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) struct urb *urb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) status = max3421_hcd->urb_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) max3421_hcd->urb_done = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) if (status > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) urb = max3421_hcd->curr_urb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) if (urb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) /* save the old end-points toggles: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) u8 hrsl = spi_rd8(hcd, MAX3421_REG_HRSL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) int rcvtog = (hrsl >> MAX3421_HRSL_RCVTOGRD_BIT) & 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) int sndtog = (hrsl >> MAX3421_HRSL_SNDTOGRD_BIT) & 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) int epnum = usb_endpoint_num(&urb->ep->desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) /* no locking: HCD (i.e., we) own toggles, don't we? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) usb_settoggle(urb->dev, epnum, 0, rcvtog);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) usb_settoggle(urb->dev, epnum, 1, sndtog);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) max3421_hcd->curr_urb = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) spin_lock_irqsave(&max3421_hcd->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) usb_hcd_unlink_urb_from_ep(hcd, urb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) spin_unlock_irqrestore(&max3421_hcd->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) /* must be called without the HCD spinlock: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) usb_hcd_giveback_urb(hcd, urb, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) max3421_spi_thread(void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) struct usb_hcd *hcd = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) struct spi_device *spi = to_spi_device(hcd->self.controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) struct max3421_hcd *max3421_hcd = hcd_to_max3421(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) int i, i_worked = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) /* set full-duplex SPI mode, low-active interrupt pin: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) spi_wr8(hcd, MAX3421_REG_PINCTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) (BIT(MAX3421_PINCTL_FDUPSPI_BIT) | /* full-duplex */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) BIT(MAX3421_PINCTL_INTLEVEL_BIT))); /* low-active irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) while (!kthread_should_stop()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) max3421_hcd->rev = spi_rd8(hcd, MAX3421_REG_REVISION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) if (max3421_hcd->rev == 0x12 || max3421_hcd->rev == 0x13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) dev_err(&spi->dev, "bad rev 0x%02x", max3421_hcd->rev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) msleep(10000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) dev_info(&spi->dev, "rev 0x%x, SPI clk %dHz, bpw %u, irq %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) max3421_hcd->rev, spi->max_speed_hz, spi->bits_per_word,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) spi->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) while (!kthread_should_stop()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) if (!i_worked) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) * We'll be waiting for wakeups from the hard
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) * interrupt handler, so now is a good time to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) * sync our hien with the chip:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) spi_wr8(hcd, MAX3421_REG_HIEN, max3421_hcd->hien);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) set_current_state(TASK_INTERRUPTIBLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) if (test_and_clear_bit(ENABLE_IRQ, &max3421_hcd->todo))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) enable_irq(spi->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) schedule();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) __set_current_state(TASK_RUNNING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) i_worked = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) if (max3421_hcd->urb_done)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) i_worked |= max3421_urb_done(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) else if (max3421_handle_irqs(hcd))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) i_worked = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) else if (!max3421_hcd->curr_urb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) i_worked |= max3421_select_and_start_urb(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) if (test_and_clear_bit(RESET_HCD, &max3421_hcd->todo))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) /* reset the HCD: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) i_worked |= max3421_reset_hcd(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) if (test_and_clear_bit(RESET_PORT, &max3421_hcd->todo)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) /* perform a USB bus reset: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) spi_wr8(hcd, MAX3421_REG_HCTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) BIT(MAX3421_HCTL_BUSRST_BIT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) i_worked = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) if (test_and_clear_bit(CHECK_UNLINK, &max3421_hcd->todo))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) i_worked |= max3421_check_unlink(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) if (test_and_clear_bit(IOPIN_UPDATE, &max3421_hcd->todo)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) * IOPINS1/IOPINS2 do not auto-increment, so we can't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) * use spi_wr_buf().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) for (i = 0; i < ARRAY_SIZE(max3421_hcd->iopins); ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) u8 val = spi_rd8(hcd, MAX3421_REG_IOPINS1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) val = ((val & 0xf0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) (max3421_hcd->iopins[i] & 0x0f));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) spi_wr8(hcd, MAX3421_REG_IOPINS1 + i, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) max3421_hcd->iopins[i] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) i_worked = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) set_current_state(TASK_RUNNING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) dev_info(&spi->dev, "SPI thread exiting");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) max3421_reset_port(struct usb_hcd *hcd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) struct max3421_hcd *max3421_hcd = hcd_to_max3421(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) max3421_hcd->port_status &= ~(USB_PORT_STAT_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) USB_PORT_STAT_LOW_SPEED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) max3421_hcd->port_status |= USB_PORT_STAT_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) set_bit(RESET_PORT, &max3421_hcd->todo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) wake_up_process(max3421_hcd->spi_thread);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) max3421_reset(struct usb_hcd *hcd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) struct max3421_hcd *max3421_hcd = hcd_to_max3421(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) hcd->self.sg_tablesize = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) hcd->speed = HCD_USB2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) hcd->self.root_hub->speed = USB_SPEED_FULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) set_bit(RESET_HCD, &max3421_hcd->todo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) wake_up_process(max3421_hcd->spi_thread);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) max3421_start(struct usb_hcd *hcd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) struct max3421_hcd *max3421_hcd = hcd_to_max3421(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) spin_lock_init(&max3421_hcd->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) max3421_hcd->rh_state = MAX3421_RH_RUNNING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) INIT_LIST_HEAD(&max3421_hcd->ep_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) hcd->power_budget = POWER_BUDGET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) hcd->state = HC_STATE_RUNNING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) hcd->uses_new_polling = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) max3421_stop(struct usb_hcd *hcd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) max3421_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) struct spi_device *spi = to_spi_device(hcd->self.controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) struct max3421_hcd *max3421_hcd = hcd_to_max3421(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) struct max3421_ep *max3421_ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) int retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) switch (usb_pipetype(urb->pipe)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) case PIPE_INTERRUPT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) case PIPE_ISOCHRONOUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) if (urb->interval < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) dev_err(&spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) "%s: interval=%d for intr-/iso-pipe; expected > 0\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) __func__, urb->interval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) spin_lock_irqsave(&max3421_hcd->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) max3421_ep = urb->ep->hcpriv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) if (!max3421_ep) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) /* gets freed in max3421_endpoint_disable: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) max3421_ep = kzalloc(sizeof(struct max3421_ep), GFP_ATOMIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) if (!max3421_ep) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) retval = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) max3421_ep->ep = urb->ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) max3421_ep->last_active = max3421_hcd->frame_number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) urb->ep->hcpriv = max3421_ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) list_add_tail(&max3421_ep->ep_list, &max3421_hcd->ep_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) retval = usb_hcd_link_urb_to_ep(hcd, urb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) if (retval == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) /* Since we added to the queue, restart scheduling: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) max3421_hcd->sched_pass = SCHED_PASS_PERIODIC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) wake_up_process(max3421_hcd->spi_thread);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) spin_unlock_irqrestore(&max3421_hcd->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) max3421_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) struct max3421_hcd *max3421_hcd = hcd_to_max3421(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) int retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) spin_lock_irqsave(&max3421_hcd->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) * This will set urb->unlinked which in turn causes the entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) * to be dropped at the next opportunity.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) retval = usb_hcd_check_unlink_urb(hcd, urb, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) if (retval == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) set_bit(CHECK_UNLINK, &max3421_hcd->todo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) wake_up_process(max3421_hcd->spi_thread);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) spin_unlock_irqrestore(&max3421_hcd->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) max3421_endpoint_disable(struct usb_hcd *hcd, struct usb_host_endpoint *ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) struct max3421_hcd *max3421_hcd = hcd_to_max3421(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) spin_lock_irqsave(&max3421_hcd->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) if (ep->hcpriv) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) struct max3421_ep *max3421_ep = ep->hcpriv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) /* remove myself from the ep_list: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) if (!list_empty(&max3421_ep->ep_list))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) list_del(&max3421_ep->ep_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) kfree(max3421_ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) ep->hcpriv = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) spin_unlock_irqrestore(&max3421_hcd->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) max3421_get_frame_number(struct usb_hcd *hcd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) struct max3421_hcd *max3421_hcd = hcd_to_max3421(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) return max3421_hcd->frame_number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) * Should return a non-zero value when any port is undergoing a resume
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) * transition while the root hub is suspended.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) max3421_hub_status_data(struct usb_hcd *hcd, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) struct max3421_hcd *max3421_hcd = hcd_to_max3421(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) int retval = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) spin_lock_irqsave(&max3421_hcd->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) if (!HCD_HW_ACCESSIBLE(hcd))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) *buf = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) if ((max3421_hcd->port_status & PORT_C_MASK) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) *buf = (1 << 1); /* a hub over-current condition exists */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) dev_dbg(hcd->self.controller,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) "port status 0x%08x has changes\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) max3421_hcd->port_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) retval = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) if (max3421_hcd->rh_state == MAX3421_RH_SUSPENDED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) usb_hcd_resume_root_hub(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) spin_unlock_irqrestore(&max3421_hcd->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) hub_descriptor(struct usb_hub_descriptor *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) memset(desc, 0, sizeof(*desc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) * See Table 11-13: Hub Descriptor in USB 2.0 spec.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) desc->bDescriptorType = USB_DT_HUB; /* hub descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) desc->bDescLength = 9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) desc->wHubCharacteristics = cpu_to_le16(HUB_CHAR_INDV_PORT_LPSM |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) HUB_CHAR_COMMON_OCPM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) desc->bNbrPorts = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) * Set the MAX3421E general-purpose output with number PIN_NUMBER to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) * VALUE (0 or 1). PIN_NUMBER may be in the range from 1-8. For
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) * any other value, this function acts as a no-op.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) max3421_gpout_set_value(struct usb_hcd *hcd, u8 pin_number, u8 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) struct max3421_hcd *max3421_hcd = hcd_to_max3421(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) u8 mask, idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) --pin_number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) if (pin_number >= MAX3421_GPOUT_COUNT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) mask = 1u << (pin_number % 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) idx = pin_number / 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) if (value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) max3421_hcd->iopins[idx] |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) max3421_hcd->iopins[idx] &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) set_bit(IOPIN_UPDATE, &max3421_hcd->todo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) wake_up_process(max3421_hcd->spi_thread);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) max3421_hub_control(struct usb_hcd *hcd, u16 type_req, u16 value, u16 index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) char *buf, u16 length)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) struct spi_device *spi = to_spi_device(hcd->self.controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) struct max3421_hcd *max3421_hcd = hcd_to_max3421(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) struct max3421_hcd_platform_data *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) int retval = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) pdata = spi->dev.platform_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) spin_lock_irqsave(&max3421_hcd->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) switch (type_req) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) case ClearHubFeature:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) case ClearPortFeature:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) switch (value) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) case USB_PORT_FEAT_SUSPEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) case USB_PORT_FEAT_POWER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) dev_dbg(hcd->self.controller, "power-off\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) max3421_gpout_set_value(hcd, pdata->vbus_gpout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) !pdata->vbus_active_level);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) max3421_hcd->port_status &= ~(1 << value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) case GetHubDescriptor:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) hub_descriptor((struct usb_hub_descriptor *) buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) case DeviceRequest | USB_REQ_GET_DESCRIPTOR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) case GetPortErrorCount:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) case SetHubDepth:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) /* USB3 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) case GetHubStatus:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) *(__le32 *) buf = cpu_to_le32(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) case GetPortStatus:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) if (index != 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) retval = -EPIPE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) ((__le16 *) buf)[0] = cpu_to_le16(max3421_hcd->port_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) ((__le16 *) buf)[1] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) cpu_to_le16(max3421_hcd->port_status >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) case SetHubFeature:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) retval = -EPIPE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) case SetPortFeature:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) switch (value) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) case USB_PORT_FEAT_LINK_STATE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) case USB_PORT_FEAT_U1_TIMEOUT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) case USB_PORT_FEAT_U2_TIMEOUT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) case USB_PORT_FEAT_BH_PORT_RESET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) case USB_PORT_FEAT_SUSPEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) if (max3421_hcd->active)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) max3421_hcd->port_status |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) USB_PORT_STAT_SUSPEND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) case USB_PORT_FEAT_POWER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) dev_dbg(hcd->self.controller, "power-on\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) max3421_hcd->port_status |= USB_PORT_STAT_POWER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) max3421_gpout_set_value(hcd, pdata->vbus_gpout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) pdata->vbus_active_level);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) case USB_PORT_FEAT_RESET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) max3421_reset_port(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) if ((max3421_hcd->port_status & USB_PORT_STAT_POWER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) max3421_hcd->port_status |= (1 << value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) dev_dbg(hcd->self.controller,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) "hub control req%04x v%04x i%04x l%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) type_req, value, index, length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) error: /* "protocol stall" on error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) retval = -EPIPE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) spin_unlock_irqrestore(&max3421_hcd->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) max3421_bus_suspend(struct usb_hcd *hcd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) max3421_bus_resume(struct usb_hcd *hcd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) static const struct hc_driver max3421_hcd_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) .description = "max3421",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) .product_desc = DRIVER_DESC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) .hcd_priv_size = sizeof(struct max3421_hcd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) .flags = HCD_USB11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) .reset = max3421_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) .start = max3421_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) .stop = max3421_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) .get_frame_number = max3421_get_frame_number,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) .urb_enqueue = max3421_urb_enqueue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) .urb_dequeue = max3421_urb_dequeue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) .endpoint_disable = max3421_endpoint_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) .hub_status_data = max3421_hub_status_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) .hub_control = max3421_hub_control,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) .bus_suspend = max3421_bus_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) .bus_resume = max3421_bus_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) max3421_of_vbus_en_pin(struct device *dev, struct max3421_hcd_platform_data *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) int retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) uint32_t value[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) if (!pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) retval = of_property_read_u32_array(dev->of_node, "maxim,vbus-en-pin", value, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) if (retval) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) dev_err(dev, "device tree node property 'maxim,vbus-en-pin' is missing\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) dev_info(dev, "property 'maxim,vbus-en-pin' value is <%d %d>\n", value[0], value[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) pdata->vbus_gpout = value[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) pdata->vbus_active_level = value[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) max3421_probe(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) struct device *dev = &spi->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) struct max3421_hcd *max3421_hcd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) struct usb_hcd *hcd = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) struct max3421_hcd_platform_data *pdata = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) int retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) if (spi_setup(spi) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) dev_err(&spi->dev, "Unable to setup SPI bus");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) if (!spi->irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) dev_err(dev, "Failed to get SPI IRQ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) if (IS_ENABLED(CONFIG_OF) && dev->of_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) pdata = devm_kzalloc(&spi->dev, sizeof(*pdata), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) if (!pdata) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) retval = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) retval = max3421_of_vbus_en_pin(dev, pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) if (retval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) spi->dev.platform_data = pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) pdata = spi->dev.platform_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) if (!pdata) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) dev_err(&spi->dev, "driver configuration data is not provided\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) retval = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) if (pdata->vbus_active_level > 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) dev_err(&spi->dev, "vbus active level value %d is out of range (0/1)\n", pdata->vbus_active_level);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) retval = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) if (pdata->vbus_gpout < 1 || pdata->vbus_gpout > MAX3421_GPOUT_COUNT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) dev_err(&spi->dev, "vbus gpout value %d is out of range (1..8)\n", pdata->vbus_gpout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) retval = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) retval = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) hcd = usb_create_hcd(&max3421_hcd_desc, &spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) dev_name(&spi->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) if (!hcd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) dev_err(&spi->dev, "failed to create HCD structure\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) max3421_hcd = hcd_to_max3421(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) INIT_LIST_HEAD(&max3421_hcd->ep_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) spi_set_drvdata(spi, max3421_hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) max3421_hcd->tx = kmalloc(sizeof(*max3421_hcd->tx), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) if (!max3421_hcd->tx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) max3421_hcd->rx = kmalloc(sizeof(*max3421_hcd->rx), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) if (!max3421_hcd->rx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) max3421_hcd->spi_thread = kthread_run(max3421_spi_thread, hcd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) "max3421_spi_thread");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) if (max3421_hcd->spi_thread == ERR_PTR(-ENOMEM)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) dev_err(&spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) "failed to create SPI thread (out of memory)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) retval = usb_add_hcd(hcd, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) if (retval) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) dev_err(&spi->dev, "failed to add HCD\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) retval = request_irq(spi->irq, max3421_irq_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) IRQF_TRIGGER_LOW, "max3421", hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) if (retval < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) dev_err(&spi->dev, "failed to request irq %d\n", spi->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) if (IS_ENABLED(CONFIG_OF) && dev->of_node && pdata) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) devm_kfree(&spi->dev, pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) spi->dev.platform_data = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) if (hcd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) kfree(max3421_hcd->tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) kfree(max3421_hcd->rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) if (max3421_hcd->spi_thread)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) kthread_stop(max3421_hcd->spi_thread);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) usb_put_hcd(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) max3421_remove(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) struct max3421_hcd *max3421_hcd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) struct usb_hcd *hcd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) max3421_hcd = spi_get_drvdata(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) hcd = max3421_to_hcd(max3421_hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) usb_remove_hcd(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) spin_lock_irqsave(&max3421_hcd->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) kthread_stop(max3421_hcd->spi_thread);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) spin_unlock_irqrestore(&max3421_hcd->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) free_irq(spi->irq, hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) usb_put_hcd(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) static const struct of_device_id max3421_of_match_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) { .compatible = "maxim,max3421", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) MODULE_DEVICE_TABLE(of, max3421_of_match_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) static struct spi_driver max3421_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) .probe = max3421_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) .remove = max3421_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) .name = "max3421-hcd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) .of_match_table = of_match_ptr(max3421_of_match_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) module_spi_driver(max3421_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) MODULE_DESCRIPTION(DRIVER_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) MODULE_AUTHOR("David Mosberger <davidm@egauge.net>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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