^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * ISP1362 HCD (Host Controller Driver) for USB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * COPYRIGHT (C) by L. Wassmann <LW@KARO-electronics.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) /* ------------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define MAX_ROOT_PORTS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define USE_32BIT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) /* These options are mutually exclusive */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define USE_PLATFORM_DELAY 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define USE_NDELAY 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define DUMMY_DELAY_ACCESS do {} while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /* ------------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define USB_RESET_WIDTH 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define MAX_XFER_SIZE 1023
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /* Buffer sizes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define ISP1362_BUF_SIZE 4096
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define ISP1362_ISTL_BUFSIZE 512
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define ISP1362_INTL_BLKSIZE 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define ISP1362_INTL_BUFFERS 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define ISP1362_ATL_BLKSIZE 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define ISP1362_REG_WRITE_OFFSET 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define REG_WIDTH_16 0x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define REG_WIDTH_32 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define REG_WIDTH_MASK 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define REG_NO_MASK 0x0ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #ifdef ISP1362_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) typedef const unsigned int isp1362_reg_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define REG_ACCESS_R 0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define REG_ACCESS_W 0x400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define REG_ACCESS_RW 0x600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define REG_ACCESS_MASK 0x600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define ISP1362_REG_NO(r) ((r) & REG_NO_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define ISP1362_REG(name, addr, width, rw) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) static isp1362_reg_t ISP1362_REG_##name = ((addr) | (width) | (rw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define REG_ACCESS_TEST(r) BUG_ON(((r) & ISP1362_REG_WRITE_OFFSET) && !((r) & REG_ACCESS_W))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define REG_WIDTH_TEST(r, w) BUG_ON(((r) & REG_WIDTH_MASK) != (w))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) typedef const unsigned char isp1362_reg_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define ISP1362_REG_NO(r) (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define ISP1362_REG(name, addr, width, rw) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) static isp1362_reg_t __maybe_unused ISP1362_REG_##name = addr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define REG_ACCESS_TEST(r) do {} while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define REG_WIDTH_TEST(r, w) do {} while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /* OHCI compatible registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * Note: Some of the ISP1362 'OHCI' registers implement only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * a subset of the bits defined in the OHCI spec.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * Bitmasks for the individual bits of these registers are defined in "ohci.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) ISP1362_REG(HCREVISION, 0x00, REG_WIDTH_32, REG_ACCESS_R);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) ISP1362_REG(HCCONTROL, 0x01, REG_WIDTH_32, REG_ACCESS_RW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) ISP1362_REG(HCCMDSTAT, 0x02, REG_WIDTH_32, REG_ACCESS_RW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) ISP1362_REG(HCINTSTAT, 0x03, REG_WIDTH_32, REG_ACCESS_RW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) ISP1362_REG(HCINTENB, 0x04, REG_WIDTH_32, REG_ACCESS_RW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) ISP1362_REG(HCINTDIS, 0x05, REG_WIDTH_32, REG_ACCESS_RW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) ISP1362_REG(HCFMINTVL, 0x0d, REG_WIDTH_32, REG_ACCESS_RW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) ISP1362_REG(HCFMREM, 0x0e, REG_WIDTH_32, REG_ACCESS_RW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) ISP1362_REG(HCFMNUM, 0x0f, REG_WIDTH_32, REG_ACCESS_RW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) ISP1362_REG(HCLSTHRESH, 0x11, REG_WIDTH_32, REG_ACCESS_RW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) ISP1362_REG(HCRHDESCA, 0x12, REG_WIDTH_32, REG_ACCESS_RW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) ISP1362_REG(HCRHDESCB, 0x13, REG_WIDTH_32, REG_ACCESS_RW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) ISP1362_REG(HCRHSTATUS, 0x14, REG_WIDTH_32, REG_ACCESS_RW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) ISP1362_REG(HCRHPORT1, 0x15, REG_WIDTH_32, REG_ACCESS_RW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) ISP1362_REG(HCRHPORT2, 0x16, REG_WIDTH_32, REG_ACCESS_RW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /* Philips ISP1362 specific registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) ISP1362_REG(HCHWCFG, 0x20, REG_WIDTH_16, REG_ACCESS_RW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define HCHWCFG_DISABLE_SUSPEND (1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define HCHWCFG_GLOBAL_PWRDOWN (1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define HCHWCFG_PULLDOWN_DS2 (1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define HCHWCFG_PULLDOWN_DS1 (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define HCHWCFG_CLKNOTSTOP (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define HCHWCFG_ANALOG_OC (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define HCHWCFG_ONEINT (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define HCHWCFG_DACK_MODE (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define HCHWCFG_ONEDMA (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define HCHWCFG_DACK_POL (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define HCHWCFG_DREQ_POL (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define HCHWCFG_DBWIDTH_MASK (0x03 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define HCHWCFG_DBWIDTH(n) (((n) << 3) & HCHWCFG_DBWIDTH_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define HCHWCFG_INT_POL (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define HCHWCFG_INT_TRIGGER (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define HCHWCFG_INT_ENABLE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) ISP1362_REG(HCDMACFG, 0x21, REG_WIDTH_16, REG_ACCESS_RW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define HCDMACFG_CTR_ENABLE (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define HCDMACFG_BURST_LEN_MASK (0x03 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define HCDMACFG_BURST_LEN(n) (((n) << 5) & HCDMACFG_BURST_LEN_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define HCDMACFG_BURST_LEN_1 HCDMACFG_BURST_LEN(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define HCDMACFG_BURST_LEN_4 HCDMACFG_BURST_LEN(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define HCDMACFG_BURST_LEN_8 HCDMACFG_BURST_LEN(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define HCDMACFG_DMA_ENABLE (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define HCDMACFG_BUF_TYPE_MASK (0x07 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define HCDMACFG_BUF_TYPE(n) (((n) << 1) & HCDMACFG_BUF_TYPE_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define HCDMACFG_BUF_ISTL0 HCDMACFG_BUF_TYPE(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define HCDMACFG_BUF_ISTL1 HCDMACFG_BUF_TYPE(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define HCDMACFG_BUF_INTL HCDMACFG_BUF_TYPE(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define HCDMACFG_BUF_ATL HCDMACFG_BUF_TYPE(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define HCDMACFG_BUF_DIRECT HCDMACFG_BUF_TYPE(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define HCDMACFG_DMA_RW_SELECT (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) ISP1362_REG(HCXFERCTR, 0x22, REG_WIDTH_16, REG_ACCESS_RW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) ISP1362_REG(HCuPINT, 0x24, REG_WIDTH_16, REG_ACCESS_RW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define HCuPINT_SOF (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define HCuPINT_ISTL0 (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define HCuPINT_ISTL1 (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define HCuPINT_EOT (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define HCuPINT_OPR (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define HCuPINT_SUSP (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define HCuPINT_CLKRDY (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define HCuPINT_INTL (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define HCuPINT_ATL (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define HCuPINT_OTG (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) ISP1362_REG(HCuPINTENB, 0x25, REG_WIDTH_16, REG_ACCESS_RW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) /* same bit definitions apply as for HCuPINT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) ISP1362_REG(HCCHIPID, 0x27, REG_WIDTH_16, REG_ACCESS_R);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define HCCHIPID_MASK 0xff00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define HCCHIPID_MAGIC 0x3600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) ISP1362_REG(HCSCRATCH, 0x28, REG_WIDTH_16, REG_ACCESS_RW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) ISP1362_REG(HCSWRES, 0x29, REG_WIDTH_16, REG_ACCESS_W);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define HCSWRES_MAGIC 0x00f6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) ISP1362_REG(HCBUFSTAT, 0x2c, REG_WIDTH_16, REG_ACCESS_RW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define HCBUFSTAT_ISTL0_FULL (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define HCBUFSTAT_ISTL1_FULL (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define HCBUFSTAT_INTL_ACTIVE (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define HCBUFSTAT_ATL_ACTIVE (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define HCBUFSTAT_RESET_HWPP (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define HCBUFSTAT_ISTL0_ACTIVE (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define HCBUFSTAT_ISTL1_ACTIVE (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define HCBUFSTAT_ISTL0_DONE (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define HCBUFSTAT_ISTL1_DONE (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define HCBUFSTAT_PAIRED_PTDPP (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) ISP1362_REG(HCDIRADDR, 0x32, REG_WIDTH_32, REG_ACCESS_RW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define HCDIRADDR_ADDR_MASK 0x0000ffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define HCDIRADDR_ADDR(n) (((n) << 0) & HCDIRADDR_ADDR_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define HCDIRADDR_COUNT_MASK 0xffff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define HCDIRADDR_COUNT(n) (((n) << 16) & HCDIRADDR_COUNT_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) ISP1362_REG(HCDIRDATA, 0x45, REG_WIDTH_16, REG_ACCESS_RW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) ISP1362_REG(HCISTLBUFSZ, 0x30, REG_WIDTH_16, REG_ACCESS_RW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) ISP1362_REG(HCISTL0PORT, 0x40, REG_WIDTH_16, REG_ACCESS_RW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) ISP1362_REG(HCISTL1PORT, 0x42, REG_WIDTH_16, REG_ACCESS_RW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) ISP1362_REG(HCISTLRATE, 0x47, REG_WIDTH_16, REG_ACCESS_RW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) ISP1362_REG(HCINTLBUFSZ, 0x33, REG_WIDTH_16, REG_ACCESS_RW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) ISP1362_REG(HCINTLPORT, 0x43, REG_WIDTH_16, REG_ACCESS_RW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) ISP1362_REG(HCINTLBLKSZ, 0x53, REG_WIDTH_16, REG_ACCESS_RW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) ISP1362_REG(HCINTLDONE, 0x17, REG_WIDTH_32, REG_ACCESS_R);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) ISP1362_REG(HCINTLSKIP, 0x18, REG_WIDTH_32, REG_ACCESS_RW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) ISP1362_REG(HCINTLLAST, 0x19, REG_WIDTH_32, REG_ACCESS_RW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) ISP1362_REG(HCINTLCURR, 0x1a, REG_WIDTH_16, REG_ACCESS_R);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) ISP1362_REG(HCATLBUFSZ, 0x34, REG_WIDTH_16, REG_ACCESS_RW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) ISP1362_REG(HCATLPORT, 0x44, REG_WIDTH_16, REG_ACCESS_RW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) ISP1362_REG(HCATLBLKSZ, 0x54, REG_WIDTH_16, REG_ACCESS_RW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) ISP1362_REG(HCATLDONE, 0x1b, REG_WIDTH_32, REG_ACCESS_R);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) ISP1362_REG(HCATLSKIP, 0x1c, REG_WIDTH_32, REG_ACCESS_RW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) ISP1362_REG(HCATLLAST, 0x1d, REG_WIDTH_32, REG_ACCESS_RW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) ISP1362_REG(HCATLCURR, 0x1e, REG_WIDTH_16, REG_ACCESS_R);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) ISP1362_REG(HCATLDTC, 0x51, REG_WIDTH_16, REG_ACCESS_RW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) ISP1362_REG(HCATLDTCTO, 0x52, REG_WIDTH_16, REG_ACCESS_RW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) ISP1362_REG(OTGCONTROL, 0x62, REG_WIDTH_16, REG_ACCESS_RW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) ISP1362_REG(OTGSTATUS, 0x67, REG_WIDTH_16, REG_ACCESS_R);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) ISP1362_REG(OTGINT, 0x68, REG_WIDTH_16, REG_ACCESS_RW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) ISP1362_REG(OTGINTENB, 0x69, REG_WIDTH_16, REG_ACCESS_RW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) ISP1362_REG(OTGTIMER, 0x6A, REG_WIDTH_16, REG_ACCESS_RW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) ISP1362_REG(OTGALTTMR, 0x6C, REG_WIDTH_16, REG_ACCESS_RW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) /* Philips transfer descriptor, cpu-endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) struct ptd {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) u16 count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define PTD_COUNT_MSK (0x3ff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define PTD_TOGGLE_MSK (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define PTD_ACTIVE_MSK (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define PTD_CC_MSK (0xf << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) u16 mps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define PTD_MPS_MSK (0x3ff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define PTD_SPD_MSK (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define PTD_LAST_MSK (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define PTD_EP_MSK (0xf << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) u16 len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define PTD_LEN_MSK (0x3ff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define PTD_DIR_MSK (3 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define PTD_DIR_SETUP (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define PTD_DIR_OUT (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define PTD_DIR_IN (2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) u16 faddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define PTD_FA_MSK (0x7f << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) /* PTD Byte 7: [StartingFrame (if ISO PTD) | StartingFrame[0..4], PollingRate[0..2] (if INT PTD)] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define PTD_SF_ISO_MSK (0xff << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define PTD_SF_INT_MSK (0x1f << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define PTD_PR_MSK (0x07 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) } __attribute__ ((packed, aligned(2)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define PTD_HEADER_SIZE sizeof(struct ptd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) /* ------------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) /* Copied from ohci.h: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) * Hardware transfer status codes -- CC from PTD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define PTD_CC_NOERROR 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define PTD_CC_CRC 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define PTD_CC_BITSTUFFING 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define PTD_CC_DATATOGGLEM 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define PTD_CC_STALL 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define PTD_DEVNOTRESP 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define PTD_PIDCHECKFAIL 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define PTD_UNEXPECTEDPID 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define PTD_DATAOVERRUN 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define PTD_DATAUNDERRUN 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) /* 0x0A, 0x0B reserved for hardware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define PTD_BUFFEROVERRUN 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define PTD_BUFFERUNDERRUN 0x0D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) /* 0x0E, 0x0F reserved for HCD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define PTD_NOTACCESSED 0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) /* map OHCI TD status codes (CC) to errno values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) static const int cc_to_error[16] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) /* No Error */ 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) /* CRC Error */ -EILSEQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) /* Bit Stuff */ -EPROTO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) /* Data Togg */ -EILSEQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) /* Stall */ -EPIPE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) /* DevNotResp */ -ETIMEDOUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) /* PIDCheck */ -EPROTO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) /* UnExpPID */ -EPROTO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) /* DataOver */ -EOVERFLOW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) /* DataUnder */ -EREMOTEIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) /* (for hw) */ -EIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) /* (for hw) */ -EIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) /* BufferOver */ -ECOMM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) /* BuffUnder */ -ENOSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) /* (for HCD) */ -EALREADY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) /* (for HCD) */ -EALREADY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) * HcControl (control) register masks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define OHCI_CTRL_HCFS (3 << 6) /* host controller functional state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define OHCI_CTRL_RWC (1 << 9) /* remote wakeup connected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define OHCI_CTRL_RWE (1 << 10) /* remote wakeup enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) /* pre-shifted values for HCFS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) # define OHCI_USB_RESET (0 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) # define OHCI_USB_RESUME (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) # define OHCI_USB_OPER (2 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) # define OHCI_USB_SUSPEND (3 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) * HcCommandStatus (cmdstatus) register masks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define OHCI_HCR (1 << 0) /* host controller reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define OHCI_SOC (3 << 16) /* scheduling overrun count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) * masks used with interrupt registers:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) * HcInterruptStatus (intrstatus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) * HcInterruptEnable (intrenable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) * HcInterruptDisable (intrdisable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define OHCI_INTR_SO (1 << 0) /* scheduling overrun */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define OHCI_INTR_WDH (1 << 1) /* writeback of done_head */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define OHCI_INTR_SF (1 << 2) /* start frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define OHCI_INTR_RD (1 << 3) /* resume detect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define OHCI_INTR_UE (1 << 4) /* unrecoverable error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define OHCI_INTR_FNO (1 << 5) /* frame number overflow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define OHCI_INTR_RHSC (1 << 6) /* root hub status change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define OHCI_INTR_OC (1 << 30) /* ownership change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define OHCI_INTR_MIE (1 << 31) /* master interrupt enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) /* roothub.portstatus [i] bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define RH_PS_CCS 0x00000001 /* current connect status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define RH_PS_PES 0x00000002 /* port enable status*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define RH_PS_PSS 0x00000004 /* port suspend status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define RH_PS_POCI 0x00000008 /* port over current indicator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define RH_PS_PRS 0x00000010 /* port reset status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define RH_PS_PPS 0x00000100 /* port power status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define RH_PS_LSDA 0x00000200 /* low speed device attached */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define RH_PS_CSC 0x00010000 /* connect status change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define RH_PS_PESC 0x00020000 /* port enable status change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define RH_PS_PSSC 0x00040000 /* port suspend status change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define RH_PS_OCIC 0x00080000 /* over current indicator change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define RH_PS_PRSC 0x00100000 /* port reset status change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) /* roothub.status bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define RH_HS_LPS 0x00000001 /* local power status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define RH_HS_OCI 0x00000002 /* over current indicator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define RH_HS_DRWE 0x00008000 /* device remote wakeup enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define RH_HS_LPSC 0x00010000 /* local power status change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define RH_HS_OCIC 0x00020000 /* over current indicator change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define RH_HS_CRWE 0x80000000 /* clear remote wakeup enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) /* roothub.b masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define RH_B_DR 0x0000ffff /* device removable flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define RH_B_PPCM 0xffff0000 /* port power control mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) /* roothub.a masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define RH_A_NDP (0xff << 0) /* number of downstream ports */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define RH_A_PSM (1 << 8) /* power switching mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define RH_A_NPS (1 << 9) /* no power switching */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define RH_A_DT (1 << 10) /* device type (mbz) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define RH_A_OCPM (1 << 11) /* over current protection mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define RH_A_NOCP (1 << 12) /* no over current protection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define RH_A_POTPGT (0xff << 24) /* power on to power good time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define FI 0x2edf /* 12000 bits per frame (-1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define FSMP(fi) (0x7fff & ((6 * ((fi) - 210)) / 7))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define LSTHRESH 0x628 /* lowspeed bit threshold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) /* ------------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) /* PTD accessor macros. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define PTD_GET_COUNT(p) (((p)->count & PTD_COUNT_MSK) >> 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define PTD_COUNT(v) (((v) << 0) & PTD_COUNT_MSK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define PTD_GET_TOGGLE(p) (((p)->count & PTD_TOGGLE_MSK) >> 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define PTD_TOGGLE(v) (((v) << 10) & PTD_TOGGLE_MSK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define PTD_GET_ACTIVE(p) (((p)->count & PTD_ACTIVE_MSK) >> 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define PTD_ACTIVE(v) (((v) << 11) & PTD_ACTIVE_MSK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define PTD_GET_CC(p) (((p)->count & PTD_CC_MSK) >> 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define PTD_CC(v) (((v) << 12) & PTD_CC_MSK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define PTD_GET_MPS(p) (((p)->mps & PTD_MPS_MSK) >> 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define PTD_MPS(v) (((v) << 0) & PTD_MPS_MSK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define PTD_GET_SPD(p) (((p)->mps & PTD_SPD_MSK) >> 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define PTD_SPD(v) (((v) << 10) & PTD_SPD_MSK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define PTD_GET_LAST(p) (((p)->mps & PTD_LAST_MSK) >> 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define PTD_LAST(v) (((v) << 11) & PTD_LAST_MSK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define PTD_GET_EP(p) (((p)->mps & PTD_EP_MSK) >> 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define PTD_EP(v) (((v) << 12) & PTD_EP_MSK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define PTD_GET_LEN(p) (((p)->len & PTD_LEN_MSK) >> 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define PTD_LEN(v) (((v) << 0) & PTD_LEN_MSK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define PTD_GET_DIR(p) (((p)->len & PTD_DIR_MSK) >> 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define PTD_DIR(v) (((v) << 10) & PTD_DIR_MSK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define PTD_GET_FA(p) (((p)->faddr & PTD_FA_MSK) >> 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define PTD_FA(v) (((v) << 0) & PTD_FA_MSK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define PTD_GET_SF_INT(p) (((p)->faddr & PTD_SF_INT_MSK) >> 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define PTD_SF_INT(v) (((v) << 8) & PTD_SF_INT_MSK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define PTD_GET_SF_ISO(p) (((p)->faddr & PTD_SF_ISO_MSK) >> 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define PTD_SF_ISO(v) (((v) << 8) & PTD_SF_ISO_MSK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define PTD_GET_PR(p) (((p)->faddr & PTD_PR_MSK) >> 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define PTD_PR(v) (((v) << 13) & PTD_PR_MSK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define LOG2_PERIODIC_SIZE 5 /* arbitrary; this matches OHCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define PERIODIC_SIZE (1 << LOG2_PERIODIC_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) struct isp1362_ep {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) struct usb_host_endpoint *hep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) struct usb_device *udev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) /* philips transfer descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) struct ptd ptd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) u8 maxpacket;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) u8 epnum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) u8 nextpid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) u16 error_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) u16 length; /* of current packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) s16 ptd_offset; /* buffer offset in ISP1362 where
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) PTD has been stored
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) (for access thru HCDIRDATA) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) int ptd_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) int num_ptds;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) void *data; /* to databuf */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) /* queue of active EPs (the ones transmitted to the chip) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) struct list_head active;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) /* periodic schedule */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) u8 branch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) u16 interval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) u16 load;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) u16 last_iso;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) /* async schedule */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) struct list_head schedule; /* list of all EPs that need processing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) struct list_head remove_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) int num_req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) struct isp1362_ep_queue {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) struct list_head active; /* list of PTDs currently processed by HC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) atomic_t finishing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) unsigned long buf_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) unsigned long skip_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) int free_ptd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) u16 buf_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) u16 buf_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) u16 blk_size; /* PTD buffer block size for ATL and INTL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) u8 buf_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) u8 buf_avail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) char name[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) /* for statistical tracking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) u8 stat_maxptds; /* Max # of ptds seen simultaneously in fifo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) u8 ptd_count; /* number of ptds submitted to this queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) struct isp1362_hcd {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) void __iomem *addr_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) void __iomem *data_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) struct isp1362_platform_data *board;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) struct dentry *debug_file;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) unsigned long stat1, stat2, stat4, stat8, stat16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) /* HC registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) u32 intenb; /* "OHCI" interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) u16 irqenb; /* uP interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) /* Root hub registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) u32 rhdesca;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) u32 rhdescb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) u32 rhstatus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) u32 rhport[MAX_ROOT_PORTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) unsigned long next_statechange;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) /* HC control reg shadow copy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) u32 hc_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) /* async schedule: control, bulk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) struct list_head async;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) /* periodic schedule: int */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) u16 load[PERIODIC_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) struct list_head periodic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) u16 fmindex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) /* periodic schedule: isochronous */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) struct list_head isoc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) unsigned int istl_flip:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) unsigned int irq_active:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) /* Schedules for the current frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) struct isp1362_ep_queue atl_queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) struct isp1362_ep_queue intl_queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) struct isp1362_ep_queue istl_queue[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) /* list of PTDs retrieved from HC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) struct list_head remove_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) ISP1362_INT_SOF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) ISP1362_INT_ISTL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) ISP1362_INT_ISTL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) ISP1362_INT_EOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) ISP1362_INT_OPR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) ISP1362_INT_SUSP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) ISP1362_INT_CLKRDY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) ISP1362_INT_INTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) ISP1362_INT_ATL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) ISP1362_INT_OTG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) NUM_ISP1362_IRQS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) } IRQ_NAMES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) unsigned int irq_stat[NUM_ISP1362_IRQS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) int req_serial;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) static inline const char *ISP1362_INT_NAME(int n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) switch (n) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) case ISP1362_INT_SOF: return "SOF";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) case ISP1362_INT_ISTL0: return "ISTL0";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) case ISP1362_INT_ISTL1: return "ISTL1";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) case ISP1362_INT_EOT: return "EOT";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) case ISP1362_INT_OPR: return "OPR";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) case ISP1362_INT_SUSP: return "SUSP";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) case ISP1362_INT_CLKRDY: return "CLKRDY";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) case ISP1362_INT_INTL: return "INTL";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) case ISP1362_INT_ATL: return "ATL";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) case ISP1362_INT_OTG: return "OTG";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) default: return "unknown";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) static inline void ALIGNSTAT(struct isp1362_hcd *isp1362_hcd, void *ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) unsigned long p = (unsigned long)ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) if (!(p & 0xf))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) isp1362_hcd->stat16++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) else if (!(p & 0x7))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) isp1362_hcd->stat8++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) else if (!(p & 0x3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) isp1362_hcd->stat4++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) else if (!(p & 0x1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) isp1362_hcd->stat2++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) isp1362_hcd->stat1++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) static inline struct isp1362_hcd *hcd_to_isp1362_hcd(struct usb_hcd *hcd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) return (struct isp1362_hcd *) (hcd->hcd_priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) static inline struct usb_hcd *isp1362_hcd_to_hcd(struct isp1362_hcd *isp1362_hcd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) return container_of((void *)isp1362_hcd, struct usb_hcd, hcd_priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) #define frame_before(f1, f2) ((s16)((u16)f1 - (u16)f2) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) * ISP1362 HW Interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) #define DBG(level, fmt...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) if (dbg_level > level) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) pr_debug(fmt); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) #ifdef VERBOSE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) # define VDBG(fmt...) DBG(3, fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) # define VDBG(fmt...) do {} while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) #ifdef REGISTERS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) # define RDBG(fmt...) DBG(1, fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) # define RDBG(fmt...) do {} while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) #ifdef URB_TRACE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) #define URB_DBG(fmt...) DBG(0, fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) #define URB_DBG(fmt...) do {} while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) #if USE_PLATFORM_DELAY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) #if USE_NDELAY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) #error USE_PLATFORM_DELAY and USE_NDELAY defined simultaneously.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) #define isp1362_delay(h, d) (h)->board->delay(isp1362_hcd_to_hcd(h)->self.controller, d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) #elif USE_NDELAY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) #define isp1362_delay(h, d) ndelay(d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) #define isp1362_delay(h, d) do {} while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) #define get_urb(ep) ({ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) BUG_ON(list_empty(&ep->hep->urb_list)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) container_of(ep->hep->urb_list.next, struct urb, urb_list); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) /* basic access functions for ISP1362 chip registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) /* NOTE: The contents of the address pointer register cannot be read back! The driver must ensure,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) * that all register accesses are performed with interrupts disabled, since the interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) * handler has no way of restoring the previous state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) static void isp1362_write_addr(struct isp1362_hcd *isp1362_hcd, isp1362_reg_t reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) REG_ACCESS_TEST(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) DUMMY_DELAY_ACCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) writew(ISP1362_REG_NO(reg), isp1362_hcd->addr_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) DUMMY_DELAY_ACCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) isp1362_delay(isp1362_hcd, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) static void isp1362_write_data16(struct isp1362_hcd *isp1362_hcd, u16 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) DUMMY_DELAY_ACCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) writew(val, isp1362_hcd->data_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) static u16 isp1362_read_data16(struct isp1362_hcd *isp1362_hcd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) u16 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) DUMMY_DELAY_ACCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) val = readw(isp1362_hcd->data_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) static void isp1362_write_data32(struct isp1362_hcd *isp1362_hcd, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) #if USE_32BIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) DUMMY_DELAY_ACCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) writel(val, isp1362_hcd->data_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) DUMMY_DELAY_ACCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) writew((u16)val, isp1362_hcd->data_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) DUMMY_DELAY_ACCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) writew(val >> 16, isp1362_hcd->data_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) static u32 isp1362_read_data32(struct isp1362_hcd *isp1362_hcd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) #if USE_32BIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) DUMMY_DELAY_ACCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) val = readl(isp1362_hcd->data_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) DUMMY_DELAY_ACCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) val = (u32)readw(isp1362_hcd->data_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) DUMMY_DELAY_ACCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) val |= (u32)readw(isp1362_hcd->data_reg) << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) /* use readsw/writesw to access the fifo whenever possible */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) /* assume HCDIRDATA or XFERCTR & addr_reg have been set up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) static void isp1362_read_fifo(struct isp1362_hcd *isp1362_hcd, void *buf, u16 len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) u8 *dp = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) u16 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) if (!len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) RDBG("%s: Reading %d byte from fifo to mem @ %p\n", __func__, len, buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) #if USE_32BIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) if (len >= 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) RDBG("%s: Using readsl for %d dwords\n", __func__, len >> 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) readsl(isp1362_hcd->data_reg, dp, len >> 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) dp += len & ~3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) len &= 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) if (len >= 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) RDBG("%s: Using readsw for %d words\n", __func__, len >> 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) insw((unsigned long)isp1362_hcd->data_reg, dp, len >> 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) dp += len & ~1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) len &= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) BUG_ON(len & ~1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) if (len > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) data = isp1362_read_data16(isp1362_hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) RDBG("%s: Reading trailing byte %02x to mem @ %08x\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) (u8)data, (u32)dp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) *dp = (u8)data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) static void isp1362_write_fifo(struct isp1362_hcd *isp1362_hcd, void *buf, u16 len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) u8 *dp = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) u16 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) if (!len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) if ((unsigned long)dp & 0x1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) /* not aligned */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) for (; len > 1; len -= 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) data = *dp++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) data |= *dp++ << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) isp1362_write_data16(isp1362_hcd, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) if (len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) isp1362_write_data16(isp1362_hcd, *dp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) RDBG("%s: Writing %d byte to fifo from memory @%p\n", __func__, len, buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) #if USE_32BIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) if (len >= 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) RDBG("%s: Using writesl for %d dwords\n", __func__, len >> 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) writesl(isp1362_hcd->data_reg, dp, len >> 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) dp += len & ~3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) len &= 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) if (len >= 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) RDBG("%s: Using writesw for %d words\n", __func__, len >> 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) outsw((unsigned long)isp1362_hcd->data_reg, dp, len >> 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) dp += len & ~1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) len &= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) BUG_ON(len & ~1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) if (len > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) /* finally write any trailing byte; we don't need to care
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) * about the high byte of the last word written
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) data = (u16)*dp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) RDBG("%s: Sending trailing byte %02x from mem @ %08x\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) data, (u32)dp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) isp1362_write_data16(isp1362_hcd, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) #define isp1362_read_reg16(d, r) ({ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) u16 __v; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) REG_WIDTH_TEST(ISP1362_REG_##r, REG_WIDTH_16); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) isp1362_write_addr(d, ISP1362_REG_##r); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) __v = isp1362_read_data16(d); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) RDBG("%s: Read %04x from %s[%02x]\n", __func__, __v, #r, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) ISP1362_REG_NO(ISP1362_REG_##r)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) __v; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) #define isp1362_read_reg32(d, r) ({ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) u32 __v; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) REG_WIDTH_TEST(ISP1362_REG_##r, REG_WIDTH_32); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) isp1362_write_addr(d, ISP1362_REG_##r); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) __v = isp1362_read_data32(d); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) RDBG("%s: Read %08x from %s[%02x]\n", __func__, __v, #r, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) ISP1362_REG_NO(ISP1362_REG_##r)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) __v; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) #define isp1362_write_reg16(d, r, v) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) REG_WIDTH_TEST(ISP1362_REG_##r, REG_WIDTH_16); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) isp1362_write_addr(d, (ISP1362_REG_##r) | ISP1362_REG_WRITE_OFFSET); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) isp1362_write_data16(d, (u16)(v)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) RDBG("%s: Wrote %04x to %s[%02x]\n", __func__, (u16)(v), #r, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) ISP1362_REG_NO(ISP1362_REG_##r)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) #define isp1362_write_reg32(d, r, v) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) REG_WIDTH_TEST(ISP1362_REG_##r, REG_WIDTH_32); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) isp1362_write_addr(d, (ISP1362_REG_##r) | ISP1362_REG_WRITE_OFFSET); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) isp1362_write_data32(d, (u32)(v)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) RDBG("%s: Wrote %08x to %s[%02x]\n", __func__, (u32)(v), #r, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) ISP1362_REG_NO(ISP1362_REG_##r)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) #define isp1362_set_mask16(d, r, m) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) u16 __v; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) __v = isp1362_read_reg16(d, r); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) if ((__v | m) != __v) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) isp1362_write_reg16(d, r, __v | m); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) #define isp1362_clr_mask16(d, r, m) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) u16 __v; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) __v = isp1362_read_reg16(d, r); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) if ((__v & ~m) != __v) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) isp1362_write_reg16(d, r, __v & ~m); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) #define isp1362_set_mask32(d, r, m) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) u32 __v; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) __v = isp1362_read_reg32(d, r); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) if ((__v | m) != __v) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) isp1362_write_reg32(d, r, __v | m); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) #define isp1362_clr_mask32(d, r, m) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) u32 __v; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) __v = isp1362_read_reg32(d, r); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) if ((__v & ~m) != __v) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) isp1362_write_reg32(d, r, __v & ~m); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) #define isp1362_show_reg(d, r) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) if ((ISP1362_REG_##r & REG_WIDTH_MASK) == REG_WIDTH_32) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) DBG(0, "%-12s[%02x]: %08x\n", #r, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) ISP1362_REG_NO(ISP1362_REG_##r), isp1362_read_reg32(d, r)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) else \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) DBG(0, "%-12s[%02x]: %04x\n", #r, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) ISP1362_REG_NO(ISP1362_REG_##r), isp1362_read_reg16(d, r)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) static void __attribute__((__unused__)) isp1362_show_regs(struct isp1362_hcd *isp1362_hcd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) isp1362_show_reg(isp1362_hcd, HCREVISION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) isp1362_show_reg(isp1362_hcd, HCCONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) isp1362_show_reg(isp1362_hcd, HCCMDSTAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) isp1362_show_reg(isp1362_hcd, HCINTSTAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) isp1362_show_reg(isp1362_hcd, HCINTENB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) isp1362_show_reg(isp1362_hcd, HCFMINTVL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) isp1362_show_reg(isp1362_hcd, HCFMREM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) isp1362_show_reg(isp1362_hcd, HCFMNUM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) isp1362_show_reg(isp1362_hcd, HCLSTHRESH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) isp1362_show_reg(isp1362_hcd, HCRHDESCA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) isp1362_show_reg(isp1362_hcd, HCRHDESCB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) isp1362_show_reg(isp1362_hcd, HCRHSTATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) isp1362_show_reg(isp1362_hcd, HCRHPORT1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) isp1362_show_reg(isp1362_hcd, HCRHPORT2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) isp1362_show_reg(isp1362_hcd, HCHWCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) isp1362_show_reg(isp1362_hcd, HCDMACFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) isp1362_show_reg(isp1362_hcd, HCXFERCTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) isp1362_show_reg(isp1362_hcd, HCuPINT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) if (in_interrupt())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) DBG(0, "%-12s[%02x]: %04x\n", "HCuPINTENB",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) ISP1362_REG_NO(ISP1362_REG_HCuPINTENB), isp1362_hcd->irqenb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) isp1362_show_reg(isp1362_hcd, HCuPINTENB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) isp1362_show_reg(isp1362_hcd, HCCHIPID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) isp1362_show_reg(isp1362_hcd, HCSCRATCH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) isp1362_show_reg(isp1362_hcd, HCBUFSTAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) isp1362_show_reg(isp1362_hcd, HCDIRADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) /* Access would advance fifo
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) * isp1362_show_reg(isp1362_hcd, HCDIRDATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) isp1362_show_reg(isp1362_hcd, HCISTLBUFSZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) isp1362_show_reg(isp1362_hcd, HCISTLRATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) isp1362_show_reg(isp1362_hcd, HCINTLBUFSZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) isp1362_show_reg(isp1362_hcd, HCINTLBLKSZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) isp1362_show_reg(isp1362_hcd, HCINTLDONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) isp1362_show_reg(isp1362_hcd, HCINTLSKIP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) isp1362_show_reg(isp1362_hcd, HCINTLLAST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) isp1362_show_reg(isp1362_hcd, HCINTLCURR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) isp1362_show_reg(isp1362_hcd, HCATLBUFSZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) isp1362_show_reg(isp1362_hcd, HCATLBLKSZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) /* only valid after ATL_DONE interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) * isp1362_show_reg(isp1362_hcd, HCATLDONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) isp1362_show_reg(isp1362_hcd, HCATLSKIP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) isp1362_show_reg(isp1362_hcd, HCATLLAST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) isp1362_show_reg(isp1362_hcd, HCATLCURR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) isp1362_show_reg(isp1362_hcd, HCATLDTC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) isp1362_show_reg(isp1362_hcd, HCATLDTCTO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) static void isp1362_write_diraddr(struct isp1362_hcd *isp1362_hcd, u16 offset, u16 len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) len = (len + 1) & ~1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) isp1362_clr_mask16(isp1362_hcd, HCDMACFG, HCDMACFG_CTR_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) isp1362_write_reg32(isp1362_hcd, HCDIRADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) HCDIRADDR_ADDR(offset) | HCDIRADDR_COUNT(len));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) static void isp1362_read_buffer(struct isp1362_hcd *isp1362_hcd, void *buf, u16 offset, int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) isp1362_write_diraddr(isp1362_hcd, offset, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) DBG(3, "%s: Reading %d byte from buffer @%04x to memory @ %p\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) __func__, len, offset, buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) isp1362_write_reg16(isp1362_hcd, HCuPINT, HCuPINT_EOT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) isp1362_write_addr(isp1362_hcd, ISP1362_REG_HCDIRDATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) isp1362_read_fifo(isp1362_hcd, buf, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) isp1362_write_reg16(isp1362_hcd, HCuPINT, HCuPINT_EOT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) static void isp1362_write_buffer(struct isp1362_hcd *isp1362_hcd, void *buf, u16 offset, int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) isp1362_write_diraddr(isp1362_hcd, offset, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) DBG(3, "%s: Writing %d byte to buffer @%04x from memory @ %p\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) __func__, len, offset, buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) isp1362_write_reg16(isp1362_hcd, HCuPINT, HCuPINT_EOT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) isp1362_write_addr(isp1362_hcd, ISP1362_REG_HCDIRDATA | ISP1362_REG_WRITE_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) isp1362_write_fifo(isp1362_hcd, buf, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) isp1362_write_reg16(isp1362_hcd, HCuPINT, HCuPINT_EOT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) static void __attribute__((unused)) dump_data(char *buf, int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) if (dbg_level > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) int k;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) int lf = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) for (k = 0; k < len; ++k) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) if (!lf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) DBG(0, "%04x:", k);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) printk(" %02x", ((u8 *) buf)[k]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) lf = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) if (!k)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) if (k % 16 == 15) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) printk("\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) lf = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) if (k % 8 == 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) printk(" ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) if (k % 4 == 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) printk(" ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) if (lf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) printk("\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) #if defined(PTD_TRACE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) static void dump_ptd(struct ptd *ptd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) DBG(0, "EP %p: CC=%x EP=%d DIR=%x CNT=%d LEN=%d MPS=%d TGL=%x ACT=%x FA=%d SPD=%x SF=%x PR=%x LST=%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) container_of(ptd, struct isp1362_ep, ptd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) PTD_GET_CC(ptd), PTD_GET_EP(ptd), PTD_GET_DIR(ptd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) PTD_GET_COUNT(ptd), PTD_GET_LEN(ptd), PTD_GET_MPS(ptd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) PTD_GET_TOGGLE(ptd), PTD_GET_ACTIVE(ptd), PTD_GET_FA(ptd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) PTD_GET_SPD(ptd), PTD_GET_SF_INT(ptd), PTD_GET_PR(ptd), PTD_GET_LAST(ptd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) DBG(0, " %04x %04x %04x %04x\n", ptd->count, ptd->mps, ptd->len, ptd->faddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) static void dump_ptd_out_data(struct ptd *ptd, u8 *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) if (dbg_level > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) if (PTD_GET_DIR(ptd) != PTD_DIR_IN && PTD_GET_LEN(ptd)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) DBG(0, "--out->\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) dump_data(buf, PTD_GET_LEN(ptd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) static void dump_ptd_in_data(struct ptd *ptd, u8 *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) if (dbg_level > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) if (PTD_GET_DIR(ptd) == PTD_DIR_IN && PTD_GET_COUNT(ptd)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) DBG(0, "<--in--\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) dump_data(buf, PTD_GET_COUNT(ptd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) DBG(0, "-----\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) static void dump_ptd_queue(struct isp1362_ep_queue *epq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) struct isp1362_ep *ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) int dbg = dbg_level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) dbg_level = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) list_for_each_entry(ep, &epq->active, active) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) dump_ptd(&ep->ptd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) dump_data(ep->data, ep->length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) dbg_level = dbg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) #define dump_ptd(ptd) do {} while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) #define dump_ptd_in_data(ptd, buf) do {} while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) #define dump_ptd_out_data(ptd, buf) do {} while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) #define dump_ptd_data(ptd, buf) do {} while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) #define dump_ptd_queue(epq) do {} while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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