^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * ISP116x register declarations and HCD data structures
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2005 Olav Kongas <ok@artecdesign.ee>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Portions:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2004 Lothar Wassmann
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (C) 2004 Psion Teklogix
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright (C) 2004 David Brownell
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) /* us of 1ms frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define MAX_LOAD_LIMIT 850
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) /* Full speed: max # of bytes to transfer for a single urb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) at a time must be < 1024 && must be multiple of 64.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 832 allows transferring 4kiB within 5 frames. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define MAX_TRANSFER_SIZE_FULLSPEED 832
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /* Low speed: there is no reason to schedule in very big
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) chunks; often the requested long transfers are for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) string descriptors containing short strings. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define MAX_TRANSFER_SIZE_LOWSPEED 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /* Bytetime (us), a rough indication of how much time it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) would take to transfer a byte of useful data over USB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define BYTE_TIME_FULLSPEED 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define BYTE_TIME_LOWSPEED 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* Buffer sizes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define ISP116x_BUF_SIZE 4096
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define ISP116x_ITL_BUFSIZE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define ISP116x_ATL_BUFSIZE ((ISP116x_BUF_SIZE) - 2*(ISP116x_ITL_BUFSIZE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define ISP116x_WRITE_OFFSET 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /*------------ ISP116x registers/bits ------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define HCREVISION 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define HCCONTROL 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define HCCONTROL_HCFS (3 << 6) /* host controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) functional state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define HCCONTROL_USB_RESET (0 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define HCCONTROL_USB_RESUME (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define HCCONTROL_USB_OPER (2 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define HCCONTROL_USB_SUSPEND (3 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define HCCONTROL_RWC (1 << 9) /* remote wakeup connected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define HCCONTROL_RWE (1 << 10) /* remote wakeup enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define HCCMDSTAT 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define HCCMDSTAT_HCR (1 << 0) /* host controller reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define HCCMDSTAT_SOC (3 << 16) /* scheduling overrun count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define HCINTSTAT 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define HCINT_SO (1 << 0) /* scheduling overrun */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define HCINT_WDH (1 << 1) /* writeback of done_head */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define HCINT_SF (1 << 2) /* start frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define HCINT_RD (1 << 3) /* resume detect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define HCINT_UE (1 << 4) /* unrecoverable error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define HCINT_FNO (1 << 5) /* frame number overflow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define HCINT_RHSC (1 << 6) /* root hub status change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define HCINT_OC (1 << 30) /* ownership change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define HCINT_MIE (1 << 31) /* master interrupt enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define HCINTENB 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define HCINTDIS 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define HCFMINTVL 0x0d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define HCFMREM 0x0e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define HCFMNUM 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define HCLSTHRESH 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define HCRHDESCA 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define RH_A_NDP (0x3 << 0) /* # downstream ports */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define RH_A_PSM (1 << 8) /* power switching mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define RH_A_NPS (1 << 9) /* no power switching */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define RH_A_DT (1 << 10) /* device type (mbz) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define RH_A_OCPM (1 << 11) /* overcurrent protection
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define RH_A_NOCP (1 << 12) /* no overcurrent protection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define RH_A_POTPGT (0xff << 24) /* power on -> power good
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define HCRHDESCB 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define RH_B_DR (0xffff << 0) /* device removable flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define RH_B_PPCM (0xffff << 16) /* port power control mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define HCRHSTATUS 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define RH_HS_LPS (1 << 0) /* local power status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define RH_HS_OCI (1 << 1) /* over current indicator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define RH_HS_DRWE (1 << 15) /* device remote wakeup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define RH_HS_LPSC (1 << 16) /* local power status change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define RH_HS_OCIC (1 << 17) /* over current indicator
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define RH_HS_CRWE (1 << 31) /* clear remote wakeup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define HCRHPORT1 0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define RH_PS_CCS (1 << 0) /* current connect status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define RH_PS_PES (1 << 1) /* port enable status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define RH_PS_PSS (1 << 2) /* port suspend status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define RH_PS_POCI (1 << 3) /* port over current
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) indicator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define RH_PS_PRS (1 << 4) /* port reset status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define RH_PS_PPS (1 << 8) /* port power status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define RH_PS_LSDA (1 << 9) /* low speed device attached */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define RH_PS_CSC (1 << 16) /* connect status change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define RH_PS_PESC (1 << 17) /* port enable status change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define RH_PS_PSSC (1 << 18) /* port suspend status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define RH_PS_OCIC (1 << 19) /* over current indicator
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define RH_PS_PRSC (1 << 20) /* port reset status change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define HCRHPORT_CLRMASK (0x1f << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define HCRHPORT2 0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define HCHWCFG 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define HCHWCFG_15KRSEL (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define HCHWCFG_CLKNOTSTOP (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define HCHWCFG_ANALOG_OC (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define HCHWCFG_DACK_MODE (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define HCHWCFG_EOT_POL (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define HCHWCFG_DACK_POL (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define HCHWCFG_DREQ_POL (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define HCHWCFG_DBWIDTH_MASK (0x03 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define HCHWCFG_DBWIDTH(n) (((n) << 3) & HCHWCFG_DBWIDTH_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define HCHWCFG_INT_POL (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define HCHWCFG_INT_TRIGGER (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define HCHWCFG_INT_ENABLE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define HCDMACFG 0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define HCDMACFG_BURST_LEN_MASK (0x03 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define HCDMACFG_BURST_LEN(n) (((n) << 5) & HCDMACFG_BURST_LEN_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define HCDMACFG_BURST_LEN_1 HCDMACFG_BURST_LEN(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define HCDMACFG_BURST_LEN_4 HCDMACFG_BURST_LEN(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define HCDMACFG_BURST_LEN_8 HCDMACFG_BURST_LEN(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define HCDMACFG_DMA_ENABLE (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define HCDMACFG_BUF_TYPE_MASK (0x07 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define HCDMACFG_CTR_SEL (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define HCDMACFG_ITLATL_SEL (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define HCDMACFG_DMA_RW_SELECT (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define HCXFERCTR 0x22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define HCuPINT 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define HCuPINT_SOF (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define HCuPINT_ATL (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define HCuPINT_AIIEOT (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define HCuPINT_OPR (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define HCuPINT_SUSP (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define HCuPINT_CLKRDY (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define HCuPINTENB 0x25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define HCCHIPID 0x27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define HCCHIPID_MASK 0xff00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define HCCHIPID_MAGIC 0x6100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define HCSCRATCH 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define HCSWRES 0x29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define HCSWRES_MAGIC 0x00f6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define HCITLBUFLEN 0x2a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define HCATLBUFLEN 0x2b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define HCBUFSTAT 0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define HCBUFSTAT_ITL0_FULL (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define HCBUFSTAT_ITL1_FULL (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define HCBUFSTAT_ATL_FULL (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define HCBUFSTAT_ITL0_DONE (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define HCBUFSTAT_ITL1_DONE (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define HCBUFSTAT_ATL_DONE (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define HCRDITL0LEN 0x2d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define HCRDITL1LEN 0x2e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define HCITLPORT 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define HCATLPORT 0x41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /* Philips transfer descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) struct ptd {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) u16 count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define PTD_COUNT_MSK (0x3ff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define PTD_TOGGLE_MSK (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define PTD_ACTIVE_MSK (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define PTD_CC_MSK (0xf << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) u16 mps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define PTD_MPS_MSK (0x3ff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define PTD_SPD_MSK (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define PTD_LAST_MSK (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define PTD_EP_MSK (0xf << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) u16 len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define PTD_LEN_MSK (0x3ff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define PTD_DIR_MSK (3 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define PTD_DIR_SETUP (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define PTD_DIR_OUT (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define PTD_DIR_IN (2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define PTD_B5_5_MSK (1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) u16 faddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define PTD_FA_MSK (0x7f << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define PTD_FMT_MSK (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) } __attribute__ ((packed, aligned(2)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /* PTD accessor macros. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define PTD_GET_COUNT(p) (((p)->count & PTD_COUNT_MSK) >> 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define PTD_COUNT(v) (((v) << 0) & PTD_COUNT_MSK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define PTD_GET_TOGGLE(p) (((p)->count & PTD_TOGGLE_MSK) >> 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define PTD_TOGGLE(v) (((v) << 10) & PTD_TOGGLE_MSK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define PTD_GET_ACTIVE(p) (((p)->count & PTD_ACTIVE_MSK) >> 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define PTD_ACTIVE(v) (((v) << 11) & PTD_ACTIVE_MSK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define PTD_GET_CC(p) (((p)->count & PTD_CC_MSK) >> 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define PTD_CC(v) (((v) << 12) & PTD_CC_MSK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define PTD_GET_MPS(p) (((p)->mps & PTD_MPS_MSK) >> 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define PTD_MPS(v) (((v) << 0) & PTD_MPS_MSK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define PTD_GET_SPD(p) (((p)->mps & PTD_SPD_MSK) >> 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define PTD_SPD(v) (((v) << 10) & PTD_SPD_MSK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define PTD_GET_LAST(p) (((p)->mps & PTD_LAST_MSK) >> 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define PTD_LAST(v) (((v) << 11) & PTD_LAST_MSK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define PTD_GET_EP(p) (((p)->mps & PTD_EP_MSK) >> 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define PTD_EP(v) (((v) << 12) & PTD_EP_MSK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define PTD_GET_LEN(p) (((p)->len & PTD_LEN_MSK) >> 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define PTD_LEN(v) (((v) << 0) & PTD_LEN_MSK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define PTD_GET_DIR(p) (((p)->len & PTD_DIR_MSK) >> 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define PTD_DIR(v) (((v) << 10) & PTD_DIR_MSK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define PTD_GET_B5_5(p) (((p)->len & PTD_B5_5_MSK) >> 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define PTD_B5_5(v) (((v) << 13) & PTD_B5_5_MSK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define PTD_GET_FA(p) (((p)->faddr & PTD_FA_MSK) >> 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define PTD_FA(v) (((v) << 0) & PTD_FA_MSK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define PTD_GET_FMT(p) (((p)->faddr & PTD_FMT_MSK) >> 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define PTD_FMT(v) (((v) << 7) & PTD_FMT_MSK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /* Hardware transfer status codes -- CC from ptd->count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define TD_CC_NOERROR 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define TD_CC_CRC 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define TD_CC_BITSTUFFING 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define TD_CC_DATATOGGLEM 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define TD_CC_STALL 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define TD_DEVNOTRESP 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define TD_PIDCHECKFAIL 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define TD_UNEXPECTEDPID 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define TD_DATAOVERRUN 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define TD_DATAUNDERRUN 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) /* 0x0A, 0x0B reserved for hardware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define TD_BUFFEROVERRUN 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define TD_BUFFERUNDERRUN 0x0D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) /* 0x0E, 0x0F reserved for HCD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define TD_NOTACCESSED 0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) /* map PTD status codes (CC) to errno values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) static const int cc_to_error[16] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) /* No Error */ 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) /* CRC Error */ -EILSEQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) /* Bit Stuff */ -EPROTO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) /* Data Togg */ -EILSEQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) /* Stall */ -EPIPE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) /* DevNotResp */ -ETIME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) /* PIDCheck */ -EPROTO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) /* UnExpPID */ -EPROTO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) /* DataOver */ -EOVERFLOW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) /* DataUnder */ -EREMOTEIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) /* (for hw) */ -EIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) /* (for hw) */ -EIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) /* BufferOver */ -ECOMM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) /* BuffUnder */ -ENOSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) /* (for HCD) */ -EALREADY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) /* (for HCD) */ -EALREADY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) /*--------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define LOG2_PERIODIC_SIZE 5 /* arbitrary; this matches OHCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define PERIODIC_SIZE (1 << LOG2_PERIODIC_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) struct isp116x {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) void __iomem *addr_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) void __iomem *data_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) struct isp116x_platform_data *board;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) struct dentry *dentry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) unsigned long stat1, stat2, stat4, stat8, stat16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) /* HC registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) u32 intenb; /* "OHCI" interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) u16 irqenb; /* uP interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) /* Root hub registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) u32 rhdesca;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) u32 rhdescb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) u32 rhstatus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) /* async schedule: control, bulk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) struct list_head async;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) /* periodic schedule: int */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) u16 load[PERIODIC_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) struct isp116x_ep *periodic[PERIODIC_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) unsigned periodic_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) u16 fmindex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) /* Schedule for the current frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) struct isp116x_ep *atl_active;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) int atl_buflen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) int atl_bufshrt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) int atl_last_dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) atomic_t atl_finishing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) static inline struct isp116x *hcd_to_isp116x(struct usb_hcd *hcd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) return (struct isp116x *)(hcd->hcd_priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) static inline struct usb_hcd *isp116x_to_hcd(struct isp116x *isp116x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) return container_of((void *)isp116x, struct usb_hcd, hcd_priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) struct isp116x_ep {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) struct usb_host_endpoint *hep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) struct usb_device *udev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) struct ptd ptd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) u8 maxpacket;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) u8 epnum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) u8 nextpid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) u16 error_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) u16 length; /* of current packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) unsigned char *data; /* to databuf */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) /* queue of active EP's (the ones scheduled for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) current frame) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) struct isp116x_ep *active;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) /* periodic schedule */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) u16 period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) u16 branch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) u16 load;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) struct isp116x_ep *next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) /* async schedule */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) struct list_head schedule;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) /*-------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define DBG(stuff...) pr_debug("116x: " stuff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #ifdef VERBOSE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) # define VDBG DBG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) # define VDBG(stuff...) do{}while(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define ERR(stuff...) printk(KERN_ERR "116x: " stuff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define WARNING(stuff...) printk(KERN_WARNING "116x: " stuff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define INFO(stuff...) printk(KERN_INFO "116x: " stuff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) /* ------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #if defined(USE_PLATFORM_DELAY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #if defined(USE_NDELAY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #error USE_PLATFORM_DELAY and USE_NDELAY simultaneously defined.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define isp116x_delay(h,d) (h)->board->delay( \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) isp116x_to_hcd(h)->self.controller,d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define isp116x_check_platform_delay(h) ((h)->board->delay == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #elif defined(USE_NDELAY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define isp116x_delay(h,d) ndelay(d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define isp116x_check_platform_delay(h) 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define isp116x_delay(h,d) do{}while(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define isp116x_check_platform_delay(h) 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) static inline void isp116x_write_addr(struct isp116x *isp116x, unsigned reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) writew(reg & 0xff, isp116x->addr_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) isp116x_delay(isp116x, 300);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) static inline void isp116x_write_data16(struct isp116x *isp116x, u16 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) writew(val, isp116x->data_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) isp116x_delay(isp116x, 150);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) static inline void isp116x_raw_write_data16(struct isp116x *isp116x, u16 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) __raw_writew(val, isp116x->data_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) isp116x_delay(isp116x, 150);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) static inline u16 isp116x_read_data16(struct isp116x *isp116x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) u16 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) val = readw(isp116x->data_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) isp116x_delay(isp116x, 150);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) static inline u16 isp116x_raw_read_data16(struct isp116x *isp116x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) u16 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) val = __raw_readw(isp116x->data_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) isp116x_delay(isp116x, 150);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) static inline void isp116x_write_data32(struct isp116x *isp116x, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) writew(val & 0xffff, isp116x->data_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) isp116x_delay(isp116x, 150);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) writew(val >> 16, isp116x->data_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) isp116x_delay(isp116x, 150);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) static inline u32 isp116x_read_data32(struct isp116x *isp116x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) val = (u32) readw(isp116x->data_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) isp116x_delay(isp116x, 150);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) val |= ((u32) readw(isp116x->data_reg)) << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) isp116x_delay(isp116x, 150);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) /* Let's keep register access functions out of line. Hint:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) we wait at least 150 ns at every access.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) static u16 isp116x_read_reg16(struct isp116x *isp116x, unsigned reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) isp116x_write_addr(isp116x, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) return isp116x_read_data16(isp116x);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) static u32 isp116x_read_reg32(struct isp116x *isp116x, unsigned reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) isp116x_write_addr(isp116x, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) return isp116x_read_data32(isp116x);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) static void isp116x_write_reg16(struct isp116x *isp116x, unsigned reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) unsigned val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) isp116x_write_addr(isp116x, reg | ISP116x_WRITE_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) isp116x_write_data16(isp116x, (u16) (val & 0xffff));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) static void isp116x_write_reg32(struct isp116x *isp116x, unsigned reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) unsigned val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) isp116x_write_addr(isp116x, reg | ISP116x_WRITE_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) isp116x_write_data32(isp116x, (u32) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) #define isp116x_show_reg_log(d,r,s) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) if ((r) < 0x20) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) DBG("%-12s[%02x]: %08x\n", #r, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) r, isp116x_read_reg32(d, r)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) } else { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) DBG("%-12s[%02x]: %04x\n", #r, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) r, isp116x_read_reg16(d, r)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) #define isp116x_show_reg_seq(d,r,s) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) if ((r) < 0x20) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) seq_printf(s, "%-12s[%02x]: %08x\n", #r, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) r, isp116x_read_reg32(d, r)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) } else { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) seq_printf(s, "%-12s[%02x]: %04x\n", #r, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) r, isp116x_read_reg16(d, r)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) #define isp116x_show_regs(d,type,s) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) isp116x_show_reg_##type(d, HCREVISION, s); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) isp116x_show_reg_##type(d, HCCONTROL, s); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) isp116x_show_reg_##type(d, HCCMDSTAT, s); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) isp116x_show_reg_##type(d, HCINTSTAT, s); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) isp116x_show_reg_##type(d, HCINTENB, s); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) isp116x_show_reg_##type(d, HCFMINTVL, s); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) isp116x_show_reg_##type(d, HCFMREM, s); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) isp116x_show_reg_##type(d, HCFMNUM, s); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) isp116x_show_reg_##type(d, HCLSTHRESH, s); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) isp116x_show_reg_##type(d, HCRHDESCA, s); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) isp116x_show_reg_##type(d, HCRHDESCB, s); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) isp116x_show_reg_##type(d, HCRHSTATUS, s); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) isp116x_show_reg_##type(d, HCRHPORT1, s); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) isp116x_show_reg_##type(d, HCRHPORT2, s); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) isp116x_show_reg_##type(d, HCHWCFG, s); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) isp116x_show_reg_##type(d, HCDMACFG, s); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) isp116x_show_reg_##type(d, HCXFERCTR, s); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) isp116x_show_reg_##type(d, HCuPINT, s); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) isp116x_show_reg_##type(d, HCuPINTENB, s); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) isp116x_show_reg_##type(d, HCCHIPID, s); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) isp116x_show_reg_##type(d, HCSCRATCH, s); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) isp116x_show_reg_##type(d, HCITLBUFLEN, s); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) isp116x_show_reg_##type(d, HCATLBUFLEN, s); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) isp116x_show_reg_##type(d, HCBUFSTAT, s); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) isp116x_show_reg_##type(d, HCRDITL0LEN, s); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) isp116x_show_reg_##type(d, HCRDITL1LEN, s); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) Dump registers for debugfs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) static inline void isp116x_show_regs_seq(struct isp116x *isp116x,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) struct seq_file *s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) isp116x_show_regs(isp116x, seq, s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) Dump registers to syslog.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) static inline void isp116x_show_regs_log(struct isp116x *isp116x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) isp116x_show_regs(isp116x, log, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) #if defined(URB_TRACE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) #define PIPETYPE(pipe) ({ char *__s; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) if (usb_pipecontrol(pipe)) __s = "ctrl"; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) else if (usb_pipeint(pipe)) __s = "int"; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) else if (usb_pipebulk(pipe)) __s = "bulk"; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) else __s = "iso"; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) __s;})
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) #define PIPEDIR(pipe) ({ usb_pipein(pipe) ? "in" : "out"; })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) #define URB_NOTSHORT(urb) ({ (urb)->transfer_flags & URB_SHORT_NOT_OK ? \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) "short_not_ok" : ""; })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) /* print debug info about the URB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) static void urb_dbg(struct urb *urb, char *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) unsigned int pipe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) if (!urb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) DBG("%s: zero urb\n", msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) pipe = urb->pipe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) DBG("%s: FA %d ep%d%s %s: len %d/%d %s\n", msg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) usb_pipedevice(pipe), usb_pipeendpoint(pipe),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) PIPEDIR(pipe), PIPETYPE(pipe),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) urb->transfer_buffer_length, urb->actual_length, URB_NOTSHORT(urb));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) #define urb_dbg(urb,msg) do{}while(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) #endif /* ! defined(URB_TRACE) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) #if defined(PTD_TRACE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) #define PTD_DIR_STR(ptd) ({char __c; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) switch(PTD_GET_DIR(ptd)){ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) case 0: __c = 's'; break; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) case 1: __c = 'o'; break; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) default: __c = 'i'; break; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) }; __c;})
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) Dump PTD info. The code documents the format
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) perfectly, right :)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) static inline void dump_ptd(struct ptd *ptd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) printk(KERN_WARNING "td: %x %d%c%d %d,%d,%d %x %x%x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) PTD_GET_CC(ptd), PTD_GET_FA(ptd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) PTD_DIR_STR(ptd), PTD_GET_EP(ptd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) PTD_GET_COUNT(ptd), PTD_GET_LEN(ptd), PTD_GET_MPS(ptd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) PTD_GET_TOGGLE(ptd), PTD_GET_ACTIVE(ptd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) PTD_GET_SPD(ptd), PTD_GET_LAST(ptd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) static inline void dump_ptd_out_data(struct ptd *ptd, u8 * buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) int k;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) if (PTD_GET_DIR(ptd) != PTD_DIR_IN && PTD_GET_LEN(ptd)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) printk(KERN_WARNING "-> ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) for (k = 0; k < PTD_GET_LEN(ptd); ++k)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) printk("%02x ", ((u8 *) buf)[k]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) printk("\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) static inline void dump_ptd_in_data(struct ptd *ptd, u8 * buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) int k;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) if (PTD_GET_DIR(ptd) == PTD_DIR_IN && PTD_GET_COUNT(ptd)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) printk(KERN_WARNING "<- ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) for (k = 0; k < PTD_GET_COUNT(ptd); ++k)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) printk("%02x ", ((u8 *) buf)[k]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) printk("\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) if (PTD_GET_LAST(ptd))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) printk(KERN_WARNING "-\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) #define dump_ptd(ptd) do{}while(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) #define dump_ptd_in_data(ptd,buf) do{}while(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) #define dump_ptd_out_data(ptd,buf) do{}while(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) #endif /* ! defined(PTD_TRACE) */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags