^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0+ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Macros and prototypes for i.MX21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2006 Loping Dog Embedded Systems
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2009 Martin Fuzzey
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Originally written by Jay Monkman <jtm@lopingdog.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Ported to 2.6.30, debugged and enhanced by Martin Fuzzey
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #ifndef __LINUX_IMX21_HCD_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define __LINUX_IMX21_HCD_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #ifdef CONFIG_DYNAMIC_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/platform_data/usb-mx2.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define NUM_ISO_ETDS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define USB_NUM_ETD 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define DMEM_SIZE 4096
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /* Register definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define USBOTG_HWMODE 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define USBOTG_HWMODE_ANASDBEN (1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define USBOTG_HWMODE_OTGXCVR_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define USBOTG_HWMODE_OTGXCVR_MASK (3 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define USBOTG_HWMODE_OTGXCVR_TD_RD (0 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define USBOTG_HWMODE_OTGXCVR_TS_RD (2 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define USBOTG_HWMODE_OTGXCVR_TD_RS (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define USBOTG_HWMODE_OTGXCVR_TS_RS (3 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define USBOTG_HWMODE_HOSTXCVR_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define USBOTG_HWMODE_HOSTXCVR_MASK (3 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define USBOTG_HWMODE_HOSTXCVR_TD_RD (0 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define USBOTG_HWMODE_HOSTXCVR_TS_RD (2 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define USBOTG_HWMODE_HOSTXCVR_TD_RS (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define USBOTG_HWMODE_HOSTXCVR_TS_RS (3 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define USBOTG_HWMODE_CRECFG_MASK (3 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define USBOTG_HWMODE_CRECFG_HOST (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define USBOTG_HWMODE_CRECFG_FUNC (2 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define USBOTG_HWMODE_CRECFG_HNP (3 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define USBOTG_CINT_STAT 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define USBOTG_CINT_STEN 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define USBOTG_ASHNPINT (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define USBOTG_ASFCINT (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define USBOTG_ASHCINT (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define USBOTG_SHNPINT (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define USBOTG_FCINT (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define USBOTG_HCINT (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define USBOTG_CLK_CTRL 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define USBOTG_CLK_CTRL_FUNC (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define USBOTG_CLK_CTRL_HST (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define USBOTG_CLK_CTRL_MAIN (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define USBOTG_RST_CTRL 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define USBOTG_RST_RSTI2C (1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define USBOTG_RST_RSTCTRL (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define USBOTG_RST_RSTFC (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define USBOTG_RST_RSTFSKE (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define USBOTG_RST_RSTRH (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define USBOTG_RST_RSTHSIE (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define USBOTG_RST_RSTHC (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define USBOTG_FRM_INTVL 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define USBOTG_FRM_REMAIN 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define USBOTG_HNP_CSR 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define USBOTG_HNP_ISR 0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define USBOTG_HNP_IEN 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define USBOTG_I2C_TXCVR_REG(x) (0x100 + (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define USBOTG_I2C_XCVR_DEVAD 0x118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define USBOTG_I2C_SEQ_OP_REG 0x119
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define USBOTG_I2C_SEQ_RD_STARTAD 0x11a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define USBOTG_I2C_OP_CTRL_REG 0x11b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define USBOTG_I2C_SCLK_TO_SCK_HPER 0x11e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define USBOTG_I2C_MASTER_INT_REG 0x11f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define USBH_HOST_CTRL 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define USBH_HOST_CTRL_HCRESET (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define USBH_HOST_CTRL_SCHDOVR(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define USBH_HOST_CTRL_RMTWUEN (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define USBH_HOST_CTRL_HCUSBSTE_RESET (0 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define USBH_HOST_CTRL_HCUSBSTE_RESUME (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define USBH_HOST_CTRL_HCUSBSTE_OPERATIONAL (2 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define USBH_HOST_CTRL_HCUSBSTE_SUSPEND (3 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define USBH_HOST_CTRL_CTLBLKSR_1 (0 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define USBH_HOST_CTRL_CTLBLKSR_2 (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define USBH_HOST_CTRL_CTLBLKSR_3 (2 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define USBH_HOST_CTRL_CTLBLKSR_4 (3 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define USBH_SYSISR 0x88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define USBH_SYSISR_PSCINT (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define USBH_SYSISR_FMOFINT (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define USBH_SYSISR_HERRINT (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define USBH_SYSISR_RESDETINT (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define USBH_SYSISR_SOFINT (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define USBH_SYSISR_DONEINT (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define USBH_SYSISR_SORINT (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define USBH_SYSIEN 0x8c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define USBH_SYSIEN_PSCINT (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define USBH_SYSIEN_FMOFINT (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define USBH_SYSIEN_HERRINT (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define USBH_SYSIEN_RESDETINT (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define USBH_SYSIEN_SOFINT (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define USBH_SYSIEN_DONEINT (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define USBH_SYSIEN_SORINT (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define USBH_XBUFSTAT 0x98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define USBH_YBUFSTAT 0x9c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define USBH_XYINTEN 0xa0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define USBH_XFILLSTAT 0xa8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define USBH_YFILLSTAT 0xac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define USBH_ETDENSET 0xc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define USBH_ETDENCLR 0xc4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define USBH_IMMEDINT 0xcc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define USBH_ETDDONESTAT 0xd0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define USBH_ETDDONEEN 0xd4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define USBH_FRMNUB 0xe0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define USBH_LSTHRESH 0xe4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define USBH_ROOTHUBA 0xe8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define USBH_ROOTHUBA_PWRTOGOOD_MASK (0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define USBH_ROOTHUBA_PWRTOGOOD_SHIFT (24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define USBH_ROOTHUBA_NOOVRCURP (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define USBH_ROOTHUBA_OVRCURPM (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define USBH_ROOTHUBA_DEVTYPE (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define USBH_ROOTHUBA_PWRSWTMD (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define USBH_ROOTHUBA_NOPWRSWT (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define USBH_ROOTHUBA_NDNSTMPRT_MASK (0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define USBH_ROOTHUBB 0xec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define USBH_ROOTHUBB_PRTPWRCM(x) (1 << ((x) + 16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define USBH_ROOTHUBB_DEVREMOVE(x) (1 << (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define USBH_ROOTSTAT 0xf0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define USBH_ROOTSTAT_CLRRMTWUE (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define USBH_ROOTSTAT_OVRCURCHG (1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define USBH_ROOTSTAT_DEVCONWUE (1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define USBH_ROOTSTAT_OVRCURI (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define USBH_ROOTSTAT_LOCPWRS (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define USBH_PORTSTAT(x) (0xf4 + ((x) * 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define USBH_PORTSTAT_PRTRSTSC (1 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define USBH_PORTSTAT_OVRCURIC (1 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define USBH_PORTSTAT_PRTSTATSC (1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define USBH_PORTSTAT_PRTENBLSC (1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define USBH_PORTSTAT_CONNECTSC (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define USBH_PORTSTAT_LSDEVCON (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define USBH_PORTSTAT_PRTPWRST (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define USBH_PORTSTAT_PRTRSTST (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define USBH_PORTSTAT_PRTOVRCURI (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define USBH_PORTSTAT_PRTSUSPST (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define USBH_PORTSTAT_PRTENABST (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define USBH_PORTSTAT_CURCONST (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define USB_DMAREV 0x800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define USB_DMAINTSTAT 0x804
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define USB_DMAINTSTAT_EPERR (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define USB_DMAINTSTAT_ETDERR (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define USB_DMAINTEN 0x808
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define USB_DMAINTEN_EPERRINTEN (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define USB_DMAINTEN_ETDERRINTEN (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define USB_ETDDMAERSTAT 0x80c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define USB_EPDMAERSTAT 0x810
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define USB_ETDDMAEN 0x820
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define USB_EPDMAEN 0x824
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define USB_ETDDMAXTEN 0x828
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define USB_EPDMAXTEN 0x82c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define USB_ETDDMAENXYT 0x830
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define USB_EPDMAENXYT 0x834
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define USB_ETDDMABST4EN 0x838
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define USB_EPDMABST4EN 0x83c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define USB_MISCCONTROL 0x840
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define USB_MISCCONTROL_ISOPREVFRM (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define USB_MISCCONTROL_SKPRTRY (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define USB_MISCCONTROL_ARBMODE (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define USB_MISCCONTROL_FILTCC (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define USB_ETDDMACHANLCLR 0x848
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define USB_EPDMACHANLCLR 0x84c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define USB_ETDSMSA(x) (0x900 + ((x) * 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define USB_EPSMSA(x) (0x980 + ((x) * 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define USB_ETDDMABUFPTR(x) (0xa00 + ((x) * 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define USB_EPDMABUFPTR(x) (0xa80 + ((x) * 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define USB_ETD_DWORD(x, w) (0x200 + ((x) * 16) + ((w) * 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define DW0_ADDRESS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define DW0_ENDPNT 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define DW0_DIRECT 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define DW0_SPEED 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define DW0_FORMAT 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define DW0_MAXPKTSIZ 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define DW0_HALTED 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define DW0_TOGCRY 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define DW0_SNDNAK 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define DW1_XBUFSRTAD 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define DW1_YBUFSRTAD 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define DW2_RTRYDELAY 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define DW2_POLINTERV 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define DW2_STARTFRM 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define DW2_RELPOLPOS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define DW2_DIRPID 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define DW2_BUFROUND 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define DW2_DELAYINT 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define DW2_DATATOG 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define DW2_ERRORCNT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define DW2_COMPCODE 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define DW3_TOTBYECNT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define DW3_PKTLEN0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define DW3_COMPCODE0 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define DW3_PKTLEN1 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define DW3_BUFSIZE 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define DW3_COMPCODE1 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define USBCTRL 0x600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define USBCTRL_I2C_WU_INT_STAT (1 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define USBCTRL_OTG_WU_INT_STAT (1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define USBCTRL_HOST_WU_INT_STAT (1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define USBCTRL_FNT_WU_INT_STAT (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define USBCTRL_I2C_WU_INT_EN (1 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define USBCTRL_OTG_WU_INT_EN (1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define USBCTRL_HOST_WU_INT_EN (1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define USBCTRL_FNT_WU_INT_EN (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define USBCTRL_OTC_RCV_RXDP (1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define USBCTRL_HOST1_BYP_TLL (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define USBCTRL_OTG_BYP_VAL(x) ((x) << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define USBCTRL_HOST1_BYP_VAL(x) ((x) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define USBCTRL_OTG_PWR_MASK (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define USBCTRL_HOST1_PWR_MASK (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define USBCTRL_HOST2_PWR_MASK (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define USBCTRL_USB_BYP (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define USBCTRL_HOST1_TXEN_OE (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define USBOTG_DMEM 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) /* Values in TD blocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define TD_DIR_SETUP 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define TD_DIR_OUT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define TD_DIR_IN 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define TD_FORMAT_CONTROL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define TD_FORMAT_ISO 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define TD_FORMAT_BULK 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define TD_FORMAT_INT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define TD_TOGGLE_CARRY 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define TD_TOGGLE_DATA0 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define TD_TOGGLE_DATA1 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) /* control transfer states */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define US_CTRL_SETUP 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define US_CTRL_DATA 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define US_CTRL_ACK 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) /* bulk transfer main state and 0-length packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define US_BULK 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define US_BULK0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) /*ETD format description*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define IMX_FMT_CTRL 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define IMX_FMT_ISO 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define IMX_FMT_BULK 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define IMX_FMT_INT 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) static char fmt_urb_to_etd[4] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) /*PIPE_ISOCHRONOUS*/ IMX_FMT_ISO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) /*PIPE_INTERRUPT*/ IMX_FMT_INT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) /*PIPE_CONTROL*/ IMX_FMT_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) /*PIPE_BULK*/ IMX_FMT_BULK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) /* condition (error) CC codes and mapping (OHCI like) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define TD_CC_NOERROR 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define TD_CC_CRC 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define TD_CC_BITSTUFFING 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define TD_CC_DATATOGGLEM 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define TD_CC_STALL 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define TD_DEVNOTRESP 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define TD_PIDCHECKFAIL 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) /*#define TD_UNEXPECTEDPID 0x07 - reserved, not active on MX2*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define TD_DATAOVERRUN 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define TD_DATAUNDERRUN 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define TD_BUFFEROVERRUN 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define TD_BUFFERUNDERRUN 0x0D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define TD_SCHEDULEOVERRUN 0x0E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define TD_NOTACCESSED 0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) static const int cc_to_error[16] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) /* No Error */ 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) /* CRC Error */ -EILSEQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) /* Bit Stuff */ -EPROTO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) /* Data Togg */ -EILSEQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) /* Stall */ -EPIPE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) /* DevNotResp */ -ETIMEDOUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) /* PIDCheck */ -EPROTO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) /* UnExpPID */ -EPROTO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) /* DataOver */ -EOVERFLOW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) /* DataUnder */ -EREMOTEIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) /* (for hw) */ -EIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) /* (for hw) */ -EIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) /* BufferOver */ -ECOMM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) /* BuffUnder */ -ENOSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) /* (for HCD) */ -ENOSPC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) /* (for HCD) */ -EALREADY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) /* HCD data associated with a usb core URB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) struct urb_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) struct urb *urb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) struct usb_host_endpoint *ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) int active;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) int state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) struct td *isoc_td;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) int isoc_remaining;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) int isoc_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) /* HCD data associated with a usb core endpoint */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) struct ep_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) struct usb_host_endpoint *ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) struct list_head td_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) struct list_head queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) int etd[NUM_ISO_ETDS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) int waiting_etd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) /* isoc packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) struct td {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) struct list_head list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) struct urb *urb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) struct usb_host_endpoint *ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) dma_addr_t dma_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) void *cpu_buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) int len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) int frame;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) int isoc_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) /* HCD data associated with a hardware ETD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) struct etd_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) struct usb_host_endpoint *ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) struct urb *urb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) struct td *td;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) struct list_head queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) dma_addr_t dma_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) void *cpu_buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) void *bounce_buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) int alloc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) int len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) int dmem_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) int dmem_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) int active_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #ifdef DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) int activated_frame;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) int disactivated_frame;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) int last_int_frame;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) int last_req_frame;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) u32 submitted_dwords[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) /* Hardware data memory info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) struct imx21_dmem_area {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) struct usb_host_endpoint *ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) unsigned int offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) unsigned int size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) struct list_head list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #ifdef DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) struct debug_usage_stats {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) unsigned int value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) unsigned int maximum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) struct debug_stats {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) unsigned long submitted;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) unsigned long completed_ok;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) unsigned long completed_failed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) unsigned long unlinked;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) unsigned long queue_etd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) unsigned long queue_dmem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) struct debug_isoc_trace {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) int schedule_frame;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) int submit_frame;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) int request_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) int done_frame;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) int done_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) int cc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) struct td *td;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) /* HCD data structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) struct imx21 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) struct usb_hcd *hcd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) struct mx21_usbh_platform_data *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) struct list_head dmem_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) struct list_head queue_for_etd; /* eps queued due to etd shortage */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) struct list_head queue_for_dmem; /* etds queued due to dmem shortage */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) struct etd_priv etd[USB_NUM_ETD];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) #ifdef DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) struct dentry *debug_root;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) struct debug_stats nonisoc_stats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) struct debug_stats isoc_stats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) struct debug_usage_stats etd_usage;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) struct debug_usage_stats dmem_usage;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) struct debug_isoc_trace isoc_trace[20];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) struct debug_isoc_trace isoc_trace_failed[20];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) unsigned long debug_unblocks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) int isoc_trace_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) int isoc_trace_index_failed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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