^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * USB Host Controller Driver for IMX21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2006 Loping Dog Embedded Systems
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2009 Martin Fuzzey
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Originally written by Jay Monkman <jtm@lopingdog.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Ported to 2.6.30, debugged and enhanced by Martin Fuzzey
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * The i.MX21 USB hardware contains
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * * 32 transfer descriptors (called ETDs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * * 4Kb of Data memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * The data memory is shared between the host and function controllers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * (but this driver only supports the host controller)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * So setting up a transfer involves:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * * Allocating a ETD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * * Fill in ETD with appropriate information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * * Allocating data memory (and putting the offset in the ETD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * * Activate the ETD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * * Get interrupt when done.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * An ETD is assigned to each active endpoint.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * Low resource (ETD and Data memory) situations are handled differently for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * isochronous and non insosynchronous transactions :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * Non ISOC transfers are queued if either ETDs or Data memory are unavailable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * ISOC transfers use 2 ETDs per endpoint to achieve double buffering.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * They allocate both ETDs and Data memory during URB submission
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * (and fail if unavailable).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #include <linux/list.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #include <linux/usb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #include <linux/usb/hcd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #include "imx21-hcd.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #ifdef CONFIG_DYNAMIC_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #ifdef DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define DEBUG_LOG_FRAME(imx21, etd, event) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) (etd)->event##_frame = readl((imx21)->regs + USBH_FRMNUB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define DEBUG_LOG_FRAME(imx21, etd, event) do { } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) static const char hcd_name[] = "imx21-hcd";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) static inline struct imx21 *hcd_to_imx21(struct usb_hcd *hcd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) return (struct imx21 *)hcd->hcd_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /* =========================================== */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* Hardware access helpers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /* =========================================== */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) static inline void set_register_bits(struct imx21 *imx21, u32 offset, u32 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) void __iomem *reg = imx21->regs + offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) writel(readl(reg) | mask, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) static inline void clear_register_bits(struct imx21 *imx21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) u32 offset, u32 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) void __iomem *reg = imx21->regs + offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) writel(readl(reg) & ~mask, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) static inline void clear_toggle_bit(struct imx21 *imx21, u32 offset, u32 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) void __iomem *reg = imx21->regs + offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) if (readl(reg) & mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) writel(mask, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) static inline void set_toggle_bit(struct imx21 *imx21, u32 offset, u32 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) void __iomem *reg = imx21->regs + offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) if (!(readl(reg) & mask))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) writel(mask, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static void etd_writel(struct imx21 *imx21, int etd_num, int dword, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) writel(value, imx21->regs + USB_ETD_DWORD(etd_num, dword));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static u32 etd_readl(struct imx21 *imx21, int etd_num, int dword)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) return readl(imx21->regs + USB_ETD_DWORD(etd_num, dword));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static inline int wrap_frame(int counter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) return counter & 0xFFFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static inline int frame_after(int frame, int after)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /* handle wrapping like jiffies time_afer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) return (s16)((s16)after - (s16)frame) < 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static int imx21_hc_get_frame(struct usb_hcd *hcd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) struct imx21 *imx21 = hcd_to_imx21(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) return wrap_frame(readl(imx21->regs + USBH_FRMNUB));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static inline bool unsuitable_for_dma(dma_addr_t addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) return (addr & 3) != 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #include "imx21-dbg.c"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static void nonisoc_urb_completed_for_etd(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) struct imx21 *imx21, struct etd_priv *etd, int status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static void schedule_nonisoc_etd(struct imx21 *imx21, struct urb *urb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static void free_dmem(struct imx21 *imx21, struct etd_priv *etd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /* =========================================== */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) /* ETD management */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /* =========================================== */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) static int alloc_etd(struct imx21 *imx21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) struct etd_priv *etd = imx21->etd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) for (i = 0; i < USB_NUM_ETD; i++, etd++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) if (etd->alloc == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) memset(etd, 0, sizeof(imx21->etd[0]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) etd->alloc = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) debug_etd_allocated(imx21);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) return i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static void disactivate_etd(struct imx21 *imx21, int num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) int etd_mask = (1 << num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) struct etd_priv *etd = &imx21->etd[num];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) writel(etd_mask, imx21->regs + USBH_ETDENCLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) clear_register_bits(imx21, USBH_ETDDONEEN, etd_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) writel(etd_mask, imx21->regs + USB_ETDDMACHANLCLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) clear_toggle_bit(imx21, USBH_ETDDONESTAT, etd_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) etd->active_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) DEBUG_LOG_FRAME(imx21, etd, disactivated);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static void reset_etd(struct imx21 *imx21, int num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) struct etd_priv *etd = imx21->etd + num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) disactivate_etd(imx21, num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) for (i = 0; i < 4; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) etd_writel(imx21, num, i, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) etd->urb = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) etd->ep = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) etd->td = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) etd->bounce_buffer = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static void free_etd(struct imx21 *imx21, int num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) if (num < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) if (num >= USB_NUM_ETD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) dev_err(imx21->dev, "BAD etd=%d!\n", num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) if (imx21->etd[num].alloc == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) dev_err(imx21->dev, "ETD %d already free!\n", num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) debug_etd_freed(imx21);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) reset_etd(imx21, num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) memset(&imx21->etd[num], 0, sizeof(imx21->etd[0]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) static void setup_etd_dword0(struct imx21 *imx21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) int etd_num, struct urb *urb, u8 dir, u16 maxpacket)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) etd_writel(imx21, etd_num, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) ((u32) usb_pipedevice(urb->pipe)) << DW0_ADDRESS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) ((u32) usb_pipeendpoint(urb->pipe) << DW0_ENDPNT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) ((u32) dir << DW0_DIRECT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) ((u32) ((urb->dev->speed == USB_SPEED_LOW) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 1 : 0) << DW0_SPEED) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) ((u32) fmt_urb_to_etd[usb_pipetype(urb->pipe)] << DW0_FORMAT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) ((u32) maxpacket << DW0_MAXPKTSIZ));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) * Copy buffer to data controller data memory.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) * We cannot use memcpy_toio() because the hardware requires 32bit writes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) static void copy_to_dmem(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) struct imx21 *imx21, int dmem_offset, void *src, int count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) void __iomem *dmem = imx21->regs + USBOTG_DMEM + dmem_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) u32 word = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) u8 *p = src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) int byte = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) for (i = 0; i < count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) byte = i % 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) word += (*p++ << (byte * 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) if (byte == 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) writel(word, dmem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) dmem += 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) word = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) if (count && byte != 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) writel(word, dmem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) static void activate_etd(struct imx21 *imx21, int etd_num, u8 dir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) u32 etd_mask = 1 << etd_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) struct etd_priv *etd = &imx21->etd[etd_num];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) if (etd->dma_handle && unsuitable_for_dma(etd->dma_handle)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) /* For non aligned isoc the condition below is always true */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) if (etd->len <= etd->dmem_size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) /* Fits into data memory, use PIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) if (dir != TD_DIR_IN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) copy_to_dmem(imx21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) etd->dmem_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) etd->cpu_buffer, etd->len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) etd->dma_handle = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) /* Too big for data memory, use bounce buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) enum dma_data_direction dmadir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) if (dir == TD_DIR_IN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) dmadir = DMA_FROM_DEVICE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) etd->bounce_buffer = kmalloc(etd->len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) GFP_ATOMIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) dmadir = DMA_TO_DEVICE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) etd->bounce_buffer = kmemdup(etd->cpu_buffer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) etd->len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) GFP_ATOMIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) if (!etd->bounce_buffer) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) dev_err(imx21->dev, "failed bounce alloc\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) goto err_bounce_alloc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) etd->dma_handle =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) dma_map_single(imx21->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) etd->bounce_buffer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) etd->len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) dmadir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) if (dma_mapping_error(imx21->dev, etd->dma_handle)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) dev_err(imx21->dev, "failed bounce map\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) goto err_bounce_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) clear_toggle_bit(imx21, USBH_ETDDONESTAT, etd_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) set_register_bits(imx21, USBH_ETDDONEEN, etd_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) clear_toggle_bit(imx21, USBH_XFILLSTAT, etd_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) clear_toggle_bit(imx21, USBH_YFILLSTAT, etd_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) if (etd->dma_handle) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) set_register_bits(imx21, USB_ETDDMACHANLCLR, etd_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) clear_toggle_bit(imx21, USBH_XBUFSTAT, etd_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) clear_toggle_bit(imx21, USBH_YBUFSTAT, etd_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) writel(etd->dma_handle, imx21->regs + USB_ETDSMSA(etd_num));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) set_register_bits(imx21, USB_ETDDMAEN, etd_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) if (dir != TD_DIR_IN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) /* need to set for ZLP and PIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) set_toggle_bit(imx21, USBH_XFILLSTAT, etd_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) set_toggle_bit(imx21, USBH_YFILLSTAT, etd_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) DEBUG_LOG_FRAME(imx21, etd, activated);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #ifdef DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) if (!etd->active_count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) etd->activated_frame = readl(imx21->regs + USBH_FRMNUB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) etd->disactivated_frame = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) etd->last_int_frame = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) etd->last_req_frame = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) for (i = 0; i < 4; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) etd->submitted_dwords[i] = etd_readl(imx21, etd_num, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) etd->active_count = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) writel(etd_mask, imx21->regs + USBH_ETDENSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) err_bounce_map:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) kfree(etd->bounce_buffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) err_bounce_alloc:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) free_dmem(imx21, etd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) nonisoc_urb_completed_for_etd(imx21, etd, -ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) /* =========================================== */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) /* Data memory management */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) /* =========================================== */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) static int alloc_dmem(struct imx21 *imx21, unsigned int size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) struct usb_host_endpoint *ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) unsigned int offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) struct imx21_dmem_area *area;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) struct imx21_dmem_area *tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) size += (~size + 1) & 0x3; /* Round to 4 byte multiple */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) if (size > DMEM_SIZE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) dev_err(imx21->dev, "size=%d > DMEM_SIZE(%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) size, DMEM_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) list_for_each_entry(tmp, &imx21->dmem_list, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) if ((size + offset) < offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) if ((size + offset) <= tmp->offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) offset = tmp->size + tmp->offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) if ((offset + size) > DMEM_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) area = kmalloc(sizeof(struct imx21_dmem_area), GFP_ATOMIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) if (area == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) area->ep = ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) area->offset = offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) area->size = size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) list_add_tail(&area->list, &tmp->list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) debug_dmem_allocated(imx21, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) return offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) /* Memory now available for a queued ETD - activate it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) static void activate_queued_etd(struct imx21 *imx21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) struct etd_priv *etd, u32 dmem_offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) struct urb_priv *urb_priv = etd->urb->hcpriv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) int etd_num = etd - &imx21->etd[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) u32 maxpacket = etd_readl(imx21, etd_num, 1) >> DW1_YBUFSRTAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) u8 dir = (etd_readl(imx21, etd_num, 2) >> DW2_DIRPID) & 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) dev_dbg(imx21->dev, "activating queued ETD %d now DMEM available\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) etd_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) etd_writel(imx21, etd_num, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) ((dmem_offset + maxpacket) << DW1_YBUFSRTAD) | dmem_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) etd->dmem_offset = dmem_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) urb_priv->active = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) activate_etd(imx21, etd_num, dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) static void free_dmem(struct imx21 *imx21, struct etd_priv *etd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) struct imx21_dmem_area *area;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) struct etd_priv *tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) int found = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) int offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) if (!etd->dmem_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) etd->dmem_size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) offset = etd->dmem_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) list_for_each_entry(area, &imx21->dmem_list, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) if (area->offset == offset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) debug_dmem_freed(imx21, area->size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) list_del(&area->list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) kfree(area);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) found = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) if (!found) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) dev_err(imx21->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) "Trying to free unallocated DMEM %d\n", offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) /* Try again to allocate memory for anything we've queued */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) list_for_each_entry_safe(etd, tmp, &imx21->queue_for_dmem, queue) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) offset = alloc_dmem(imx21, etd->dmem_size, etd->ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) if (offset >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) list_del(&etd->queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) activate_queued_etd(imx21, etd, (u32)offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) static void free_epdmem(struct imx21 *imx21, struct usb_host_endpoint *ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) struct imx21_dmem_area *area, *tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) list_for_each_entry_safe(area, tmp, &imx21->dmem_list, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) if (area->ep == ep) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) dev_err(imx21->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) "Active DMEM %d for disabled ep=%p\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) area->offset, ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) list_del(&area->list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) kfree(area);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) /* =========================================== */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) /* End handling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) /* =========================================== */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) /* Endpoint now idle - release its ETD(s) or assign to queued request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) static void ep_idle(struct imx21 *imx21, struct ep_priv *ep_priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) for (i = 0; i < NUM_ISO_ETDS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) int etd_num = ep_priv->etd[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) struct etd_priv *etd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) if (etd_num < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) etd = &imx21->etd[etd_num];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) ep_priv->etd[i] = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) free_dmem(imx21, etd); /* for isoc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) if (list_empty(&imx21->queue_for_etd)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) free_etd(imx21, etd_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) dev_dbg(imx21->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) "assigning idle etd %d for queued request\n", etd_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) ep_priv = list_first_entry(&imx21->queue_for_etd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) struct ep_priv, queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) list_del(&ep_priv->queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) reset_etd(imx21, etd_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) ep_priv->waiting_etd = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) ep_priv->etd[i] = etd_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) if (list_empty(&ep_priv->ep->urb_list)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) dev_err(imx21->dev, "No urb for queued ep!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) schedule_nonisoc_etd(imx21, list_first_entry(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) &ep_priv->ep->urb_list, struct urb, urb_list));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) static void urb_done(struct usb_hcd *hcd, struct urb *urb, int status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) __releases(imx21->lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) __acquires(imx21->lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) struct imx21 *imx21 = hcd_to_imx21(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) struct ep_priv *ep_priv = urb->ep->hcpriv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) struct urb_priv *urb_priv = urb->hcpriv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) debug_urb_completed(imx21, urb, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) dev_vdbg(imx21->dev, "urb %p done %d\n", urb, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) kfree(urb_priv->isoc_td);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) kfree(urb->hcpriv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) urb->hcpriv = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) usb_hcd_unlink_urb_from_ep(hcd, urb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) spin_unlock(&imx21->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) usb_hcd_giveback_urb(hcd, urb, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) spin_lock(&imx21->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) if (list_empty(&ep_priv->ep->urb_list))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) ep_idle(imx21, ep_priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) static void nonisoc_urb_completed_for_etd(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) struct imx21 *imx21, struct etd_priv *etd, int status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) struct usb_host_endpoint *ep = etd->ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) urb_done(imx21->hcd, etd->urb, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) etd->urb = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) if (!list_empty(&ep->urb_list)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) struct urb *urb = list_first_entry(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) &ep->urb_list, struct urb, urb_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) dev_vdbg(imx21->dev, "next URB %p\n", urb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) schedule_nonisoc_etd(imx21, urb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) /* =========================================== */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) /* ISOC Handling ... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) /* =========================================== */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) static void schedule_isoc_etds(struct usb_hcd *hcd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) struct usb_host_endpoint *ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) struct imx21 *imx21 = hcd_to_imx21(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) struct ep_priv *ep_priv = ep->hcpriv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) struct etd_priv *etd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) struct urb_priv *urb_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) struct td *td;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) int etd_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) int cur_frame;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) u8 dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) for (i = 0; i < NUM_ISO_ETDS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) too_late:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) if (list_empty(&ep_priv->td_list))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) etd_num = ep_priv->etd[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) if (etd_num < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) etd = &imx21->etd[etd_num];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) if (etd->urb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) td = list_entry(ep_priv->td_list.next, struct td, list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) list_del(&td->list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) urb_priv = td->urb->hcpriv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) cur_frame = imx21_hc_get_frame(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) if (frame_after(cur_frame, td->frame)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) dev_dbg(imx21->dev, "isoc too late frame %d > %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) cur_frame, td->frame);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) urb_priv->isoc_status = -EXDEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) td->urb->iso_frame_desc[
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) td->isoc_index].actual_length = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) td->urb->iso_frame_desc[td->isoc_index].status = -EXDEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) if (--urb_priv->isoc_remaining == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) urb_done(hcd, td->urb, urb_priv->isoc_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) goto too_late;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) urb_priv->active = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) etd->td = td;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) etd->ep = td->ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) etd->urb = td->urb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) etd->len = td->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) etd->dma_handle = td->dma_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) etd->cpu_buffer = td->cpu_buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) debug_isoc_submitted(imx21, cur_frame, td);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) dir = usb_pipeout(td->urb->pipe) ? TD_DIR_OUT : TD_DIR_IN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) setup_etd_dword0(imx21, etd_num, td->urb, dir, etd->dmem_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) etd_writel(imx21, etd_num, 1, etd->dmem_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) etd_writel(imx21, etd_num, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) (TD_NOTACCESSED << DW2_COMPCODE) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) ((td->frame & 0xFFFF) << DW2_STARTFRM));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) etd_writel(imx21, etd_num, 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) (TD_NOTACCESSED << DW3_COMPCODE0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) (td->len << DW3_PKTLEN0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) activate_etd(imx21, etd_num, dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) static void isoc_etd_done(struct usb_hcd *hcd, int etd_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) struct imx21 *imx21 = hcd_to_imx21(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) int etd_mask = 1 << etd_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) struct etd_priv *etd = imx21->etd + etd_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) struct urb *urb = etd->urb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) struct urb_priv *urb_priv = urb->hcpriv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) struct td *td = etd->td;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) struct usb_host_endpoint *ep = etd->ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) int isoc_index = td->isoc_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) unsigned int pipe = urb->pipe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) int dir_in = usb_pipein(pipe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) int cc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) int bytes_xfrd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) disactivate_etd(imx21, etd_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) cc = (etd_readl(imx21, etd_num, 3) >> DW3_COMPCODE0) & 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) bytes_xfrd = etd_readl(imx21, etd_num, 3) & 0x3ff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) /* Input doesn't always fill the buffer, don't generate an error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) * when this happens.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) if (dir_in && (cc == TD_DATAUNDERRUN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) cc = TD_CC_NOERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) if (cc == TD_NOTACCESSED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) bytes_xfrd = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) debug_isoc_completed(imx21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) imx21_hc_get_frame(hcd), td, cc, bytes_xfrd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) if (cc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) urb_priv->isoc_status = -EXDEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) dev_dbg(imx21->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) "bad iso cc=0x%X frame=%d sched frame=%d "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) "cnt=%d len=%d urb=%p etd=%d index=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) cc, imx21_hc_get_frame(hcd), td->frame,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) bytes_xfrd, td->len, urb, etd_num, isoc_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) if (dir_in) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) clear_toggle_bit(imx21, USBH_XFILLSTAT, etd_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) if (!etd->dma_handle)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) memcpy_fromio(etd->cpu_buffer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) imx21->regs + USBOTG_DMEM + etd->dmem_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) bytes_xfrd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) urb->actual_length += bytes_xfrd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) urb->iso_frame_desc[isoc_index].actual_length = bytes_xfrd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) urb->iso_frame_desc[isoc_index].status = cc_to_error[cc];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) etd->td = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) etd->urb = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) etd->ep = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) if (--urb_priv->isoc_remaining == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) urb_done(hcd, urb, urb_priv->isoc_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) schedule_isoc_etds(hcd, ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) static struct ep_priv *alloc_isoc_ep(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) struct imx21 *imx21, struct usb_host_endpoint *ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) struct ep_priv *ep_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) ep_priv = kzalloc(sizeof(struct ep_priv), GFP_ATOMIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) if (!ep_priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) for (i = 0; i < NUM_ISO_ETDS; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) ep_priv->etd[i] = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) INIT_LIST_HEAD(&ep_priv->td_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) ep_priv->ep = ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) ep->hcpriv = ep_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) return ep_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) static int alloc_isoc_etds(struct imx21 *imx21, struct ep_priv *ep_priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) int i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) int etd_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) /* Allocate the ETDs if required */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) for (i = 0; i < NUM_ISO_ETDS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) if (ep_priv->etd[i] < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) etd_num = alloc_etd(imx21);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) if (etd_num < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) goto alloc_etd_failed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) ep_priv->etd[i] = etd_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) imx21->etd[etd_num].ep = ep_priv->ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) alloc_etd_failed:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) dev_err(imx21->dev, "isoc: Couldn't allocate etd\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) for (j = 0; j < i; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) free_etd(imx21, ep_priv->etd[j]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) ep_priv->etd[j] = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) static int imx21_hc_urb_enqueue_isoc(struct usb_hcd *hcd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) struct usb_host_endpoint *ep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) struct urb *urb, gfp_t mem_flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) struct imx21 *imx21 = hcd_to_imx21(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) struct urb_priv *urb_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) struct ep_priv *ep_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) struct td *td = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) int cur_frame;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) u16 maxpacket;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) urb_priv = kzalloc(sizeof(struct urb_priv), mem_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) if (urb_priv == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) urb_priv->isoc_td = kcalloc(urb->number_of_packets, sizeof(struct td),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) mem_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) if (urb_priv->isoc_td == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) goto alloc_td_failed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) spin_lock_irqsave(&imx21->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) if (ep->hcpriv == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) ep_priv = alloc_isoc_ep(imx21, ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) if (ep_priv == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) goto alloc_ep_failed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) ep_priv = ep->hcpriv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) ret = alloc_isoc_etds(imx21, ep_priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) goto alloc_etd_failed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) ret = usb_hcd_link_urb_to_ep(hcd, urb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) goto link_failed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) urb->status = -EINPROGRESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) urb->actual_length = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) urb->error_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) urb->hcpriv = urb_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) urb_priv->ep = ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) /* allocate data memory for largest packets if not already done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) maxpacket = usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) for (i = 0; i < NUM_ISO_ETDS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) struct etd_priv *etd = &imx21->etd[ep_priv->etd[i]];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) if (etd->dmem_size > 0 && etd->dmem_size < maxpacket) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) /* not sure if this can really occur.... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) dev_err(imx21->dev, "increasing isoc buffer %d->%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) etd->dmem_size, maxpacket);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) ret = -EMSGSIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) goto alloc_dmem_failed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) if (etd->dmem_size == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) etd->dmem_offset = alloc_dmem(imx21, maxpacket, ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) if (etd->dmem_offset < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) dev_dbg(imx21->dev, "failed alloc isoc dmem\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) ret = -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) goto alloc_dmem_failed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) etd->dmem_size = maxpacket;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) /* calculate frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) cur_frame = imx21_hc_get_frame(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) if (list_empty(&ep_priv->td_list)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) urb->start_frame = wrap_frame(cur_frame + 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) urb->start_frame = wrap_frame(list_entry(ep_priv->td_list.prev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) struct td, list)->frame + urb->interval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) if (frame_after(cur_frame, urb->start_frame)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) dev_dbg(imx21->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) "enqueue: adjusting iso start %d (cur=%d) asap=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) urb->start_frame, cur_frame,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) (urb->transfer_flags & URB_ISO_ASAP) != 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) i = DIV_ROUND_UP(wrap_frame(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) cur_frame - urb->start_frame),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) urb->interval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) /* Treat underruns as if URB_ISO_ASAP was set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) if ((urb->transfer_flags & URB_ISO_ASAP) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) i >= urb->number_of_packets) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) urb->start_frame = wrap_frame(urb->start_frame
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) + i * urb->interval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) /* set up transfers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) urb_priv->isoc_remaining = urb->number_of_packets - i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) td = urb_priv->isoc_td;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) for (; i < urb->number_of_packets; i++, td++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) unsigned int offset = urb->iso_frame_desc[i].offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) td->ep = ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) td->urb = urb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) td->len = urb->iso_frame_desc[i].length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) td->isoc_index = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) td->frame = wrap_frame(urb->start_frame + urb->interval * i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) td->dma_handle = urb->transfer_dma + offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) td->cpu_buffer = urb->transfer_buffer + offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) list_add_tail(&td->list, &ep_priv->td_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) dev_vdbg(imx21->dev, "setup %d packets for iso frame %d->%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) urb->number_of_packets, urb->start_frame, td->frame);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) debug_urb_submitted(imx21, urb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) schedule_isoc_etds(hcd, ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) spin_unlock_irqrestore(&imx21->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) alloc_dmem_failed:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) usb_hcd_unlink_urb_from_ep(hcd, urb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) link_failed:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) alloc_etd_failed:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) alloc_ep_failed:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) spin_unlock_irqrestore(&imx21->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) kfree(urb_priv->isoc_td);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) alloc_td_failed:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) kfree(urb_priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) static void dequeue_isoc_urb(struct imx21 *imx21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) struct urb *urb, struct ep_priv *ep_priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) struct urb_priv *urb_priv = urb->hcpriv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) struct td *td, *tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) if (urb_priv->active) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) for (i = 0; i < NUM_ISO_ETDS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) int etd_num = ep_priv->etd[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) if (etd_num != -1 && imx21->etd[etd_num].urb == urb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) struct etd_priv *etd = imx21->etd + etd_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) reset_etd(imx21, etd_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) free_dmem(imx21, etd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) list_for_each_entry_safe(td, tmp, &ep_priv->td_list, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) if (td->urb == urb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) dev_vdbg(imx21->dev, "removing td %p\n", td);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) list_del(&td->list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) /* =========================================== */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) /* NON ISOC Handling ... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) /* =========================================== */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) static void schedule_nonisoc_etd(struct imx21 *imx21, struct urb *urb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) unsigned int pipe = urb->pipe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) struct urb_priv *urb_priv = urb->hcpriv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) struct ep_priv *ep_priv = urb_priv->ep->hcpriv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) int state = urb_priv->state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) int etd_num = ep_priv->etd[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) struct etd_priv *etd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) u32 count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) u16 etd_buf_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) u16 maxpacket;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) u8 dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) u8 bufround;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) u8 datatoggle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) u8 interval = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) u8 relpolpos = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) if (etd_num < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) dev_err(imx21->dev, "No valid ETD\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) if (readl(imx21->regs + USBH_ETDENSET) & (1 << etd_num))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) dev_err(imx21->dev, "submitting to active ETD %d\n", etd_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) etd = &imx21->etd[etd_num];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) maxpacket = usb_maxpacket(urb->dev, pipe, usb_pipeout(pipe));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) if (!maxpacket)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) maxpacket = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) if (usb_pipecontrol(pipe) && (state != US_CTRL_DATA)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) if (state == US_CTRL_SETUP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) dir = TD_DIR_SETUP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) if (unsuitable_for_dma(urb->setup_dma))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) usb_hcd_unmap_urb_setup_for_dma(imx21->hcd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) urb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) etd->dma_handle = urb->setup_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) etd->cpu_buffer = urb->setup_packet;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) bufround = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) count = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) datatoggle = TD_TOGGLE_DATA0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) } else { /* US_CTRL_ACK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) dir = usb_pipeout(pipe) ? TD_DIR_IN : TD_DIR_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) bufround = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) datatoggle = TD_TOGGLE_DATA1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) dir = usb_pipeout(pipe) ? TD_DIR_OUT : TD_DIR_IN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) bufround = (dir == TD_DIR_IN) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) if (unsuitable_for_dma(urb->transfer_dma))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) usb_hcd_unmap_urb_for_dma(imx21->hcd, urb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) etd->dma_handle = urb->transfer_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) etd->cpu_buffer = urb->transfer_buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) if (usb_pipebulk(pipe) && (state == US_BULK0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) count = urb->transfer_buffer_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) if (usb_pipecontrol(pipe)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) datatoggle = TD_TOGGLE_DATA1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) if (usb_gettoggle(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) urb->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) usb_pipeendpoint(urb->pipe),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) usb_pipeout(urb->pipe)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) datatoggle = TD_TOGGLE_DATA1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) datatoggle = TD_TOGGLE_DATA0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) etd->urb = urb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) etd->ep = urb_priv->ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) etd->len = count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) if (usb_pipeint(pipe)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) interval = urb->interval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) relpolpos = (readl(imx21->regs + USBH_FRMNUB) + 1) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) /* Write ETD to device memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) setup_etd_dword0(imx21, etd_num, urb, dir, maxpacket);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) etd_writel(imx21, etd_num, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) (u32) interval << DW2_POLINTERV |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) ((u32) relpolpos << DW2_RELPOLPOS) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) ((u32) dir << DW2_DIRPID) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) ((u32) bufround << DW2_BUFROUND) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) ((u32) datatoggle << DW2_DATATOG) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) ((u32) TD_NOTACCESSED << DW2_COMPCODE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) /* DMA will always transfer buffer size even if TOBYCNT in DWORD3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) is smaller. Make sure we don't overrun the buffer!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) if (count && count < maxpacket)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) etd_buf_size = count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) etd_buf_size = maxpacket;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) etd_writel(imx21, etd_num, 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) ((u32) (etd_buf_size - 1) << DW3_BUFSIZE) | (u32) count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) if (!count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) etd->dma_handle = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) /* allocate x and y buffer space at once */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) etd->dmem_size = (count > maxpacket) ? maxpacket * 2 : maxpacket;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) etd->dmem_offset = alloc_dmem(imx21, etd->dmem_size, urb_priv->ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) if (etd->dmem_offset < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) /* Setup everything we can in HW and update when we get DMEM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) etd_writel(imx21, etd_num, 1, (u32)maxpacket << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) dev_dbg(imx21->dev, "Queuing etd %d for DMEM\n", etd_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) debug_urb_queued_for_dmem(imx21, urb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) list_add_tail(&etd->queue, &imx21->queue_for_dmem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) etd_writel(imx21, etd_num, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) (((u32) etd->dmem_offset + (u32) maxpacket) << DW1_YBUFSRTAD) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) (u32) etd->dmem_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) urb_priv->active = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) /* enable the ETD to kick off transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) dev_vdbg(imx21->dev, "Activating etd %d for %d bytes %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) etd_num, count, dir != TD_DIR_IN ? "out" : "in");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) activate_etd(imx21, etd_num, dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) static void nonisoc_etd_done(struct usb_hcd *hcd, int etd_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) struct imx21 *imx21 = hcd_to_imx21(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) struct etd_priv *etd = &imx21->etd[etd_num];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) struct urb *urb = etd->urb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) u32 etd_mask = 1 << etd_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) struct urb_priv *urb_priv = urb->hcpriv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) int dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) int cc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) u32 bytes_xfrd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) int etd_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) disactivate_etd(imx21, etd_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) dir = (etd_readl(imx21, etd_num, 0) >> DW0_DIRECT) & 0x3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) cc = (etd_readl(imx21, etd_num, 2) >> DW2_COMPCODE) & 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) bytes_xfrd = etd->len - (etd_readl(imx21, etd_num, 3) & 0x1fffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) /* save toggle carry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) usb_settoggle(urb->dev, usb_pipeendpoint(urb->pipe),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) usb_pipeout(urb->pipe),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) (etd_readl(imx21, etd_num, 0) >> DW0_TOGCRY) & 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) if (dir == TD_DIR_IN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) clear_toggle_bit(imx21, USBH_XFILLSTAT, etd_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) clear_toggle_bit(imx21, USBH_YFILLSTAT, etd_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) if (etd->bounce_buffer) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) memcpy(etd->cpu_buffer, etd->bounce_buffer, bytes_xfrd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) dma_unmap_single(imx21->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) etd->dma_handle, etd->len, DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) } else if (!etd->dma_handle && bytes_xfrd) {/* PIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) memcpy_fromio(etd->cpu_buffer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) imx21->regs + USBOTG_DMEM + etd->dmem_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) bytes_xfrd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) kfree(etd->bounce_buffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) etd->bounce_buffer = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) free_dmem(imx21, etd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) urb->error_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) if (!(urb->transfer_flags & URB_SHORT_NOT_OK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) && (cc == TD_DATAUNDERRUN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) cc = TD_CC_NOERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) if (cc != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) dev_vdbg(imx21->dev, "cc is 0x%x\n", cc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) etd_done = (cc_to_error[cc] != 0); /* stop if error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) switch (usb_pipetype(urb->pipe)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) case PIPE_CONTROL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) switch (urb_priv->state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) case US_CTRL_SETUP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) if (urb->transfer_buffer_length > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) urb_priv->state = US_CTRL_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) urb_priv->state = US_CTRL_ACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) case US_CTRL_DATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) urb->actual_length += bytes_xfrd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) urb_priv->state = US_CTRL_ACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) case US_CTRL_ACK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) etd_done = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) dev_err(imx21->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) "Invalid pipe state %d\n", urb_priv->state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) etd_done = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) case PIPE_BULK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) urb->actual_length += bytes_xfrd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) if ((urb_priv->state == US_BULK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) && (urb->transfer_flags & URB_ZERO_PACKET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) && urb->transfer_buffer_length > 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) && ((urb->transfer_buffer_length %
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) usb_maxpacket(urb->dev, urb->pipe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) usb_pipeout(urb->pipe))) == 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) /* need a 0-packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) urb_priv->state = US_BULK0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) etd_done = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) case PIPE_INTERRUPT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) urb->actual_length += bytes_xfrd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) etd_done = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) if (etd_done)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) nonisoc_urb_completed_for_etd(imx21, etd, cc_to_error[cc]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) dev_vdbg(imx21->dev, "next state=%d\n", urb_priv->state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) schedule_nonisoc_etd(imx21, urb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) static struct ep_priv *alloc_ep(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) struct ep_priv *ep_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) ep_priv = kzalloc(sizeof(struct ep_priv), GFP_ATOMIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) if (!ep_priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) for (i = 0; i < NUM_ISO_ETDS; ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) ep_priv->etd[i] = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) return ep_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) static int imx21_hc_urb_enqueue(struct usb_hcd *hcd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) struct urb *urb, gfp_t mem_flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) struct imx21 *imx21 = hcd_to_imx21(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) struct usb_host_endpoint *ep = urb->ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) struct urb_priv *urb_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) struct ep_priv *ep_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) struct etd_priv *etd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) dev_vdbg(imx21->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) "enqueue urb=%p ep=%p len=%d "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) "buffer=%p dma=%pad setupBuf=%p setupDma=%pad\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) urb, ep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) urb->transfer_buffer_length,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) urb->transfer_buffer, &urb->transfer_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) urb->setup_packet, &urb->setup_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) if (usb_pipeisoc(urb->pipe))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) return imx21_hc_urb_enqueue_isoc(hcd, ep, urb, mem_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) urb_priv = kzalloc(sizeof(struct urb_priv), mem_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) if (!urb_priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) spin_lock_irqsave(&imx21->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) ep_priv = ep->hcpriv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) if (ep_priv == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) ep_priv = alloc_ep();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) if (!ep_priv) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) goto failed_alloc_ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) ep->hcpriv = ep_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) ep_priv->ep = ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) ret = usb_hcd_link_urb_to_ep(hcd, urb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) goto failed_link;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) urb->status = -EINPROGRESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) urb->actual_length = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) urb->error_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) urb->hcpriv = urb_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) urb_priv->ep = ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) switch (usb_pipetype(urb->pipe)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) case PIPE_CONTROL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) urb_priv->state = US_CTRL_SETUP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) case PIPE_BULK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) urb_priv->state = US_BULK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) debug_urb_submitted(imx21, urb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) if (ep_priv->etd[0] < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) if (ep_priv->waiting_etd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) dev_dbg(imx21->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) "no ETD available already queued %p\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) ep_priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) debug_urb_queued_for_etd(imx21, urb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) ep_priv->etd[0] = alloc_etd(imx21);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) if (ep_priv->etd[0] < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) dev_dbg(imx21->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) "no ETD available queueing %p\n", ep_priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) debug_urb_queued_for_etd(imx21, urb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) list_add_tail(&ep_priv->queue, &imx21->queue_for_etd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) ep_priv->waiting_etd = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) /* Schedule if no URB already active for this endpoint */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) etd = &imx21->etd[ep_priv->etd[0]];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) if (etd->urb == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) DEBUG_LOG_FRAME(imx21, etd, last_req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) schedule_nonisoc_etd(imx21, urb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) spin_unlock_irqrestore(&imx21->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) failed_link:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) failed_alloc_ep:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) spin_unlock_irqrestore(&imx21->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) kfree(urb_priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) static int imx21_hc_urb_dequeue(struct usb_hcd *hcd, struct urb *urb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) int status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) struct imx21 *imx21 = hcd_to_imx21(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) struct usb_host_endpoint *ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) struct ep_priv *ep_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) struct urb_priv *urb_priv = urb->hcpriv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) int ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) dev_vdbg(imx21->dev, "dequeue urb=%p iso=%d status=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) urb, usb_pipeisoc(urb->pipe), status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) spin_lock_irqsave(&imx21->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) ret = usb_hcd_check_unlink_urb(hcd, urb, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) ep = urb_priv->ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) ep_priv = ep->hcpriv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) debug_urb_unlinked(imx21, urb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) if (usb_pipeisoc(urb->pipe)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) dequeue_isoc_urb(imx21, urb, ep_priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) schedule_isoc_etds(hcd, ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) } else if (urb_priv->active) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) int etd_num = ep_priv->etd[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) if (etd_num != -1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) struct etd_priv *etd = &imx21->etd[etd_num];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) disactivate_etd(imx21, etd_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) free_dmem(imx21, etd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) etd->urb = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) kfree(etd->bounce_buffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) etd->bounce_buffer = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) urb_done(hcd, urb, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) spin_unlock_irqrestore(&imx21->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) spin_unlock_irqrestore(&imx21->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) /* =========================================== */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) /* Interrupt dispatch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) /* =========================================== */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) static void process_etds(struct usb_hcd *hcd, struct imx21 *imx21, int sof)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) int etd_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) int enable_sof_int = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) spin_lock_irqsave(&imx21->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) for (etd_num = 0; etd_num < USB_NUM_ETD; etd_num++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) u32 etd_mask = 1 << etd_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) u32 enabled = readl(imx21->regs + USBH_ETDENSET) & etd_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) u32 done = readl(imx21->regs + USBH_ETDDONESTAT) & etd_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) struct etd_priv *etd = &imx21->etd[etd_num];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) if (done) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) DEBUG_LOG_FRAME(imx21, etd, last_int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) * Kludge warning!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) * When multiple transfers are using the bus we sometimes get into a state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) * where the transfer has completed (the CC field of the ETD is != 0x0F),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) * the ETD has self disabled but the ETDDONESTAT flag is not set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) * (and hence no interrupt occurs).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) * This causes the transfer in question to hang.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) * The kludge below checks for this condition at each SOF and processes any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) * blocked ETDs (after an arbitrary 10 frame wait)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) * With a single active transfer the usbtest test suite will run for days
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) * without the kludge.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) * With other bus activity (eg mass storage) even just test1 will hang without
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) * the kludge.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) u32 dword0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) int cc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) if (etd->active_count && !enabled) /* suspicious... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) enable_sof_int = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) if (!sof || enabled || !etd->active_count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) cc = etd_readl(imx21, etd_num, 2) >> DW2_COMPCODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) if (cc == TD_NOTACCESSED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) if (++etd->active_count < 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) dword0 = etd_readl(imx21, etd_num, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) dev_dbg(imx21->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) "unblock ETD %d dev=0x%X ep=0x%X cc=0x%02X!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) etd_num, dword0 & 0x7F,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) (dword0 >> DW0_ENDPNT) & 0x0F,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) cc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) #ifdef DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) dev_dbg(imx21->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) "frame: act=%d disact=%d"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) " int=%d req=%d cur=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) etd->activated_frame,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) etd->disactivated_frame,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) etd->last_int_frame,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) etd->last_req_frame,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) readl(imx21->regs + USBH_FRMNUB));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) imx21->debug_unblocks++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) etd->active_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) /* End of kludge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) if (etd->ep == NULL || etd->urb == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) dev_dbg(imx21->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) "Interrupt for unexpected etd %d"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) " ep=%p urb=%p\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) etd_num, etd->ep, etd->urb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) disactivate_etd(imx21, etd_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) if (usb_pipeisoc(etd->urb->pipe))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) isoc_etd_done(hcd, etd_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) nonisoc_etd_done(hcd, etd_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) /* only enable SOF interrupt if it may be needed for the kludge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) if (enable_sof_int)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) set_register_bits(imx21, USBH_SYSIEN, USBH_SYSIEN_SOFINT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) clear_register_bits(imx21, USBH_SYSIEN, USBH_SYSIEN_SOFINT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) spin_unlock_irqrestore(&imx21->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) static irqreturn_t imx21_irq(struct usb_hcd *hcd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) struct imx21 *imx21 = hcd_to_imx21(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) u32 ints = readl(imx21->regs + USBH_SYSISR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) if (ints & USBH_SYSIEN_HERRINT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) dev_dbg(imx21->dev, "Scheduling error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) if (ints & USBH_SYSIEN_SORINT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) dev_dbg(imx21->dev, "Scheduling overrun\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) if (ints & (USBH_SYSISR_DONEINT | USBH_SYSISR_SOFINT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) process_etds(hcd, imx21, ints & USBH_SYSISR_SOFINT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) writel(ints, imx21->regs + USBH_SYSISR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) static void imx21_hc_endpoint_disable(struct usb_hcd *hcd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) struct usb_host_endpoint *ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) struct imx21 *imx21 = hcd_to_imx21(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) struct ep_priv *ep_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) if (ep == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) spin_lock_irqsave(&imx21->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) ep_priv = ep->hcpriv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) dev_vdbg(imx21->dev, "disable ep=%p, ep->hcpriv=%p\n", ep, ep_priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) if (!list_empty(&ep->urb_list))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) dev_dbg(imx21->dev, "ep's URB list is not empty\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) if (ep_priv != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) for (i = 0; i < NUM_ISO_ETDS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) if (ep_priv->etd[i] > -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) dev_dbg(imx21->dev, "free etd %d for disable\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) ep_priv->etd[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) free_etd(imx21, ep_priv->etd[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) kfree(ep_priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) ep->hcpriv = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) for (i = 0; i < USB_NUM_ETD; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) if (imx21->etd[i].alloc && imx21->etd[i].ep == ep) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) dev_err(imx21->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) "Active etd %d for disabled ep=%p!\n", i, ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) free_etd(imx21, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) free_epdmem(imx21, ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) spin_unlock_irqrestore(&imx21->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) /* =========================================== */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) /* Hub handling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) /* =========================================== */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) static int get_hub_descriptor(struct usb_hcd *hcd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) struct usb_hub_descriptor *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) struct imx21 *imx21 = hcd_to_imx21(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) desc->bDescriptorType = USB_DT_HUB; /* HUB descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) desc->bHubContrCurrent = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) desc->bNbrPorts = readl(imx21->regs + USBH_ROOTHUBA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) & USBH_ROOTHUBA_NDNSTMPRT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) desc->bDescLength = 9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) desc->bPwrOn2PwrGood = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) desc->wHubCharacteristics = (__force __u16) cpu_to_le16(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) HUB_CHAR_NO_LPSM | /* No power switching */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) HUB_CHAR_NO_OCPM); /* No over current protection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) desc->u.hs.DeviceRemovable[0] = 1 << 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) desc->u.hs.DeviceRemovable[1] = ~0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) static int imx21_hc_hub_status_data(struct usb_hcd *hcd, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) struct imx21 *imx21 = hcd_to_imx21(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) int ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) int changed = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) spin_lock_irqsave(&imx21->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) ports = readl(imx21->regs + USBH_ROOTHUBA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) & USBH_ROOTHUBA_NDNSTMPRT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) if (ports > 7) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) ports = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) dev_err(imx21->dev, "ports %d > 7\n", ports);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) for (i = 0; i < ports; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) if (readl(imx21->regs + USBH_PORTSTAT(i)) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) (USBH_PORTSTAT_CONNECTSC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) USBH_PORTSTAT_PRTENBLSC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) USBH_PORTSTAT_PRTSTATSC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) USBH_PORTSTAT_OVRCURIC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) USBH_PORTSTAT_PRTRSTSC)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) changed = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) buf[0] |= 1 << (i + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) spin_unlock_irqrestore(&imx21->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) if (changed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) dev_info(imx21->dev, "Hub status changed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) return changed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) static int imx21_hc_hub_control(struct usb_hcd *hcd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) u16 typeReq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) u16 wValue, u16 wIndex, char *buf, u16 wLength)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) struct imx21 *imx21 = hcd_to_imx21(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) int rc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) u32 status_write = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) switch (typeReq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) case ClearHubFeature:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) dev_dbg(imx21->dev, "ClearHubFeature\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) switch (wValue) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) case C_HUB_OVER_CURRENT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) dev_dbg(imx21->dev, " OVER_CURRENT\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) case C_HUB_LOCAL_POWER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) dev_dbg(imx21->dev, " LOCAL_POWER\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) dev_dbg(imx21->dev, " unknown\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) rc = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) case ClearPortFeature:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) dev_dbg(imx21->dev, "ClearPortFeature\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) switch (wValue) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) case USB_PORT_FEAT_ENABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) dev_dbg(imx21->dev, " ENABLE\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) status_write = USBH_PORTSTAT_CURCONST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) case USB_PORT_FEAT_SUSPEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) dev_dbg(imx21->dev, " SUSPEND\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) status_write = USBH_PORTSTAT_PRTOVRCURI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) case USB_PORT_FEAT_POWER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) dev_dbg(imx21->dev, " POWER\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) status_write = USBH_PORTSTAT_LSDEVCON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) case USB_PORT_FEAT_C_ENABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) dev_dbg(imx21->dev, " C_ENABLE\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) status_write = USBH_PORTSTAT_PRTENBLSC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) case USB_PORT_FEAT_C_SUSPEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) dev_dbg(imx21->dev, " C_SUSPEND\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) status_write = USBH_PORTSTAT_PRTSTATSC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) case USB_PORT_FEAT_C_CONNECTION:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) dev_dbg(imx21->dev, " C_CONNECTION\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) status_write = USBH_PORTSTAT_CONNECTSC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) case USB_PORT_FEAT_C_OVER_CURRENT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) dev_dbg(imx21->dev, " C_OVER_CURRENT\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) status_write = USBH_PORTSTAT_OVRCURIC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) case USB_PORT_FEAT_C_RESET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) dev_dbg(imx21->dev, " C_RESET\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) status_write = USBH_PORTSTAT_PRTRSTSC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) dev_dbg(imx21->dev, " unknown\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) rc = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) case GetHubDescriptor:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) dev_dbg(imx21->dev, "GetHubDescriptor\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) rc = get_hub_descriptor(hcd, (void *)buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) case GetHubStatus:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) dev_dbg(imx21->dev, " GetHubStatus\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) *(__le32 *) buf = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) case GetPortStatus:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) dev_dbg(imx21->dev, "GetPortStatus: port: %d, 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) wIndex, USBH_PORTSTAT(wIndex - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) *(__le32 *) buf = readl(imx21->regs +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) USBH_PORTSTAT(wIndex - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) case SetHubFeature:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) dev_dbg(imx21->dev, "SetHubFeature\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) switch (wValue) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) case C_HUB_OVER_CURRENT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) dev_dbg(imx21->dev, " OVER_CURRENT\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) case C_HUB_LOCAL_POWER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) dev_dbg(imx21->dev, " LOCAL_POWER\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) dev_dbg(imx21->dev, " unknown\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) rc = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) case SetPortFeature:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) dev_dbg(imx21->dev, "SetPortFeature\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) switch (wValue) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) case USB_PORT_FEAT_SUSPEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) dev_dbg(imx21->dev, " SUSPEND\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) status_write = USBH_PORTSTAT_PRTSUSPST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) case USB_PORT_FEAT_POWER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) dev_dbg(imx21->dev, " POWER\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) status_write = USBH_PORTSTAT_PRTPWRST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) case USB_PORT_FEAT_RESET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) dev_dbg(imx21->dev, " RESET\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) status_write = USBH_PORTSTAT_PRTRSTST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) dev_dbg(imx21->dev, " unknown\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) rc = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) dev_dbg(imx21->dev, " unknown\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) rc = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) if (status_write)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) writel(status_write, imx21->regs + USBH_PORTSTAT(wIndex - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) /* =========================================== */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) /* Host controller management */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) /* =========================================== */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) static int imx21_hc_reset(struct usb_hcd *hcd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) struct imx21 *imx21 = hcd_to_imx21(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) unsigned long timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) spin_lock_irqsave(&imx21->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) /* Reset the Host controller modules */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) writel(USBOTG_RST_RSTCTRL | USBOTG_RST_RSTRH |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) USBOTG_RST_RSTHSIE | USBOTG_RST_RSTHC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) imx21->regs + USBOTG_RST_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) /* Wait for reset to finish */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) timeout = jiffies + HZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) while (readl(imx21->regs + USBOTG_RST_CTRL) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) if (time_after(jiffies, timeout)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) spin_unlock_irqrestore(&imx21->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) dev_err(imx21->dev, "timeout waiting for reset\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) spin_unlock_irq(&imx21->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) schedule_timeout_uninterruptible(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) spin_lock_irq(&imx21->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) spin_unlock_irqrestore(&imx21->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) static int imx21_hc_start(struct usb_hcd *hcd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) struct imx21 *imx21 = hcd_to_imx21(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) int i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) u32 hw_mode = USBOTG_HWMODE_CRECFG_HOST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) u32 usb_control = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) hw_mode |= ((imx21->pdata->host_xcvr << USBOTG_HWMODE_HOSTXCVR_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) USBOTG_HWMODE_HOSTXCVR_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) hw_mode |= ((imx21->pdata->otg_xcvr << USBOTG_HWMODE_OTGXCVR_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) USBOTG_HWMODE_OTGXCVR_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) if (imx21->pdata->host1_txenoe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) usb_control |= USBCTRL_HOST1_TXEN_OE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) if (!imx21->pdata->host1_xcverless)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) usb_control |= USBCTRL_HOST1_BYP_TLL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) if (imx21->pdata->otg_ext_xcvr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) usb_control |= USBCTRL_OTC_RCV_RXDP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) spin_lock_irqsave(&imx21->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) writel((USBOTG_CLK_CTRL_HST | USBOTG_CLK_CTRL_MAIN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) imx21->regs + USBOTG_CLK_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) writel(hw_mode, imx21->regs + USBOTG_HWMODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) writel(usb_control, imx21->regs + USBCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) writel(USB_MISCCONTROL_SKPRTRY | USB_MISCCONTROL_ARBMODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) imx21->regs + USB_MISCCONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) /* Clear the ETDs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) for (i = 0; i < USB_NUM_ETD; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) for (j = 0; j < 4; j++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) etd_writel(imx21, i, j, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) /* Take the HC out of reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) writel(USBH_HOST_CTRL_HCUSBSTE_OPERATIONAL | USBH_HOST_CTRL_CTLBLKSR_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) imx21->regs + USBH_HOST_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) /* Enable ports */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) if (imx21->pdata->enable_otg_host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) writel(USBH_PORTSTAT_PRTPWRST | USBH_PORTSTAT_PRTENABST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) imx21->regs + USBH_PORTSTAT(0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) if (imx21->pdata->enable_host1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) writel(USBH_PORTSTAT_PRTPWRST | USBH_PORTSTAT_PRTENABST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) imx21->regs + USBH_PORTSTAT(1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) if (imx21->pdata->enable_host2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) writel(USBH_PORTSTAT_PRTPWRST | USBH_PORTSTAT_PRTENABST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) imx21->regs + USBH_PORTSTAT(2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) hcd->state = HC_STATE_RUNNING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) /* Enable host controller interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) set_register_bits(imx21, USBH_SYSIEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) USBH_SYSIEN_HERRINT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) USBH_SYSIEN_DONEINT | USBH_SYSIEN_SORINT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) set_register_bits(imx21, USBOTG_CINT_STEN, USBOTG_HCINT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) spin_unlock_irqrestore(&imx21->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) static void imx21_hc_stop(struct usb_hcd *hcd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) struct imx21 *imx21 = hcd_to_imx21(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) spin_lock_irqsave(&imx21->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) writel(0, imx21->regs + USBH_SYSIEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) clear_register_bits(imx21, USBOTG_CINT_STEN, USBOTG_HCINT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) clear_register_bits(imx21, USBOTG_CLK_CTRL_HST | USBOTG_CLK_CTRL_MAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) USBOTG_CLK_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) spin_unlock_irqrestore(&imx21->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) /* =========================================== */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) /* Driver glue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) /* =========================================== */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) static const struct hc_driver imx21_hc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) .description = hcd_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) .product_desc = "IMX21 USB Host Controller",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) .hcd_priv_size = sizeof(struct imx21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) .flags = HCD_DMA | HCD_USB11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) .irq = imx21_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) .reset = imx21_hc_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) .start = imx21_hc_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) .stop = imx21_hc_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) /* I/O requests */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) .urb_enqueue = imx21_hc_urb_enqueue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) .urb_dequeue = imx21_hc_urb_dequeue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) .endpoint_disable = imx21_hc_endpoint_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) /* scheduling support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) .get_frame_number = imx21_hc_get_frame,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) /* Root hub support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) .hub_status_data = imx21_hc_hub_status_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) .hub_control = imx21_hc_hub_control,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) static struct mx21_usbh_platform_data default_pdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) .host_xcvr = MX21_USBXCVR_TXDIF_RXDIF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) .otg_xcvr = MX21_USBXCVR_TXDIF_RXDIF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) .enable_host1 = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) .enable_host2 = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) .enable_otg_host = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) static int imx21_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) struct usb_hcd *hcd = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) struct imx21 *imx21 = hcd_to_imx21(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) remove_debug_files(imx21);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) usb_remove_hcd(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) if (res != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) clk_disable_unprepare(imx21->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) clk_put(imx21->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) iounmap(imx21->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) release_mem_region(res->start, resource_size(res));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) kfree(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) static int imx21_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) struct usb_hcd *hcd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) struct imx21 *imx21;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) printk(KERN_INFO "%s\n", imx21_hc_driver.product_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) if (!res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) if (irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) hcd = usb_create_hcd(&imx21_hc_driver,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) &pdev->dev, dev_name(&pdev->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) if (hcd == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) dev_err(&pdev->dev, "Cannot create hcd (%s)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) dev_name(&pdev->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) imx21 = hcd_to_imx21(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) imx21->hcd = hcd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) imx21->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) imx21->pdata = dev_get_platdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) if (!imx21->pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) imx21->pdata = &default_pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) spin_lock_init(&imx21->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) INIT_LIST_HEAD(&imx21->dmem_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) INIT_LIST_HEAD(&imx21->queue_for_etd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) INIT_LIST_HEAD(&imx21->queue_for_dmem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) create_debug_files(imx21);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) res = request_mem_region(res->start, resource_size(res), hcd_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) if (!res) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) ret = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) goto failed_request_mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) imx21->regs = ioremap(res->start, resource_size(res));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) if (imx21->regs == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) dev_err(imx21->dev, "Cannot map registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) goto failed_ioremap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) /* Enable clocks source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) imx21->clk = clk_get(imx21->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) if (IS_ERR(imx21->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) dev_err(imx21->dev, "no clock found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) ret = PTR_ERR(imx21->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) goto failed_clock_get;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) ret = clk_set_rate(imx21->clk, clk_round_rate(imx21->clk, 48000000));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) goto failed_clock_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) ret = clk_prepare_enable(imx21->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) goto failed_clock_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) dev_info(imx21->dev, "Hardware HC revision: 0x%02X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) (readl(imx21->regs + USBOTG_HWMODE) >> 16) & 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) ret = usb_add_hcd(hcd, irq, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) if (ret != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) dev_err(imx21->dev, "usb_add_hcd() returned %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) goto failed_add_hcd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) device_wakeup_enable(hcd->self.controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) failed_add_hcd:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) clk_disable_unprepare(imx21->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) failed_clock_enable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) failed_clock_set:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) clk_put(imx21->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) failed_clock_get:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) iounmap(imx21->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) failed_ioremap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) release_mem_region(res->start, resource_size(res));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) failed_request_mem:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) remove_debug_files(imx21);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) usb_put_hcd(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) static struct platform_driver imx21_hcd_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) .name = hcd_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) .probe = imx21_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) .remove = imx21_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) .suspend = NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) .resume = NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) module_platform_driver(imx21_hcd_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) MODULE_DESCRIPTION("i.MX21 USB Host controller");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) MODULE_AUTHOR("Martin Fuzzey");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) MODULE_ALIAS("platform:imx21-hcd");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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