^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #ifndef __LINUX_FOTG210_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #define __LINUX_FOTG210_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <linux/usb/ehci-dbgp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) /* definitions used for the EHCI driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * __hc32 and __hc16 are "Host Controller" types, they may be equivalent to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * __leXX (normally) or __beXX (given FOTG210_BIG_ENDIAN_DESC), depending on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * the host controller implementation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * To facilitate the strongest possible byte-order checking from "sparse"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * and so on, we use __leXX unless that's not practical.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define __hc32 __le32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define __hc16 __le16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /* statistics can be kept for tuning/monitoring */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) struct fotg210_stats {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /* irq usage */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) unsigned long normal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) unsigned long error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) unsigned long iaa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) unsigned long lost_iaa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /* termination of urbs from core */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) unsigned long complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) unsigned long unlink;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /* fotg210_hcd->lock guards shared data against other CPUs:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * fotg210_hcd: async, unlink, periodic (and shadow), ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * usb_host_endpoint: hcpriv
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * fotg210_qh: qh_next, qtd_list
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * fotg210_qtd: qtd_list
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * Also, hold this lock when talking to HC registers or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * when updating hw_* fields in shared qh/qtd/... structures.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define FOTG210_MAX_ROOT_PORTS 1 /* see HCS_N_PORTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * fotg210_rh_state values of FOTG210_RH_RUNNING or above mean that the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * controller may be doing DMA. Lower values mean there's no DMA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) enum fotg210_rh_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) FOTG210_RH_HALTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) FOTG210_RH_SUSPENDED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) FOTG210_RH_RUNNING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) FOTG210_RH_STOPPING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * Timer events, ordered by increasing delay length.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * Always update event_delays_ns[] and event_handlers[] (defined in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * ehci-timer.c) in parallel with this list.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) enum fotg210_hrtimer_event {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) FOTG210_HRTIMER_POLL_ASS, /* Poll for async schedule off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) FOTG210_HRTIMER_POLL_PSS, /* Poll for periodic schedule off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) FOTG210_HRTIMER_POLL_DEAD, /* Wait for dead controller to stop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) FOTG210_HRTIMER_UNLINK_INTR, /* Wait for interrupt QH unlink */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) FOTG210_HRTIMER_FREE_ITDS, /* Wait for unused iTDs and siTDs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) FOTG210_HRTIMER_ASYNC_UNLINKS, /* Unlink empty async QHs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) FOTG210_HRTIMER_IAA_WATCHDOG, /* Handle lost IAA interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) FOTG210_HRTIMER_DISABLE_PERIODIC, /* Wait to disable periodic sched */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) FOTG210_HRTIMER_DISABLE_ASYNC, /* Wait to disable async sched */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) FOTG210_HRTIMER_IO_WATCHDOG, /* Check for missing IRQs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) FOTG210_HRTIMER_NUM_EVENTS /* Must come last */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define FOTG210_HRTIMER_NO_EVENT 99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct fotg210_hcd { /* one per controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* timing support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) enum fotg210_hrtimer_event next_hrtimer_event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) unsigned enabled_hrtimer_events;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) ktime_t hr_timeouts[FOTG210_HRTIMER_NUM_EVENTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct hrtimer hrtimer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) int PSS_poll_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) int ASS_poll_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) int died_poll_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* glue to PCI and HCD framework */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) struct fotg210_caps __iomem *caps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct fotg210_regs __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) struct ehci_dbg_port __iomem *debug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) __u32 hcs_params; /* cached register copy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) enum fotg210_rh_state rh_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /* general schedule support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) bool scanning:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) bool need_rescan:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) bool intr_unlinking:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) bool async_unlinking:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) bool shutdown:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) struct fotg210_qh *qh_scan_next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /* async schedule support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) struct fotg210_qh *async;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) struct fotg210_qh *dummy; /* For AMD quirk use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) struct fotg210_qh *async_unlink;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) struct fotg210_qh *async_unlink_last;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) struct fotg210_qh *async_iaa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) unsigned async_unlink_cycle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) unsigned async_count; /* async activity count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /* periodic schedule support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define DEFAULT_I_TDPS 1024 /* some HCs can do less */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) unsigned periodic_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) __hc32 *periodic; /* hw periodic table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) dma_addr_t periodic_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) struct list_head intr_qh_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) unsigned i_thresh; /* uframes HC might cache */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) union fotg210_shadow *pshadow; /* mirror hw periodic table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) struct fotg210_qh *intr_unlink;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) struct fotg210_qh *intr_unlink_last;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) unsigned intr_unlink_cycle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) unsigned now_frame; /* frame from HC hardware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) unsigned next_frame; /* scan periodic, start here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) unsigned intr_count; /* intr activity count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) unsigned isoc_count; /* isoc activity count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) unsigned periodic_count; /* periodic activity count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /* max periodic time per uframe */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) unsigned uframe_periodic_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /* list of itds completed while now_frame was still active */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct list_head cached_itd_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) struct fotg210_itd *last_itd_to_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /* per root hub port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) unsigned long reset_done[FOTG210_MAX_ROOT_PORTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /* bit vectors (one bit per port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) * which ports were already suspended at the start of a bus suspend
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) unsigned long bus_suspended;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /* which ports are edicated to the companion controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) unsigned long companion_ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /* which ports are owned by the companion during a bus suspend */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) unsigned long owned_ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /* which ports have the change-suspend feature turned on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) unsigned long port_c_suspend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /* which ports are suspended */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) unsigned long suspended_ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /* which ports have started to resume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) unsigned long resuming_ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /* per-HC memory pools (could be per-bus, but ...) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) struct dma_pool *qh_pool; /* qh per active urb */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) struct dma_pool *qtd_pool; /* one or more per qh */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) struct dma_pool *itd_pool; /* itd per iso urb */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) unsigned random_frame;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) unsigned long next_statechange;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) ktime_t last_periodic_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) u32 command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /* SILICON QUIRKS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) unsigned need_io_watchdog:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) unsigned fs_i_thresh:1; /* Intel iso scheduling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) u8 sbrn; /* packed release number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /* irq statistics */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #ifdef FOTG210_STATS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) struct fotg210_stats stats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) # define INCR(x) ((x)++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) # define INCR(x) do {} while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /* silicon clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) struct clk *pclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /* debug files */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) struct dentry *debug_dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /* convert between an HCD pointer and the corresponding FOTG210_HCD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) static inline struct fotg210_hcd *hcd_to_fotg210(struct usb_hcd *hcd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) return (struct fotg210_hcd *)(hcd->hcd_priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static inline struct usb_hcd *fotg210_to_hcd(struct fotg210_hcd *fotg210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) return container_of((void *) fotg210, struct usb_hcd, hcd_priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) /*-------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) /* EHCI register interface, corresponds to EHCI Revision 0.95 specification */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) /* Section 2.2 Host Controller Capability Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) struct fotg210_caps {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) /* these fields are specified as 8 and 16 bit registers,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) * but some hosts can't perform 8 or 16 bit PCI accesses.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) * some hosts treat caplength and hciversion as parts of a 32-bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) * register, others treat them as two separate registers, this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) * affects the memory map for big endian controllers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) u32 hc_capbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define HC_LENGTH(fotg210, p) (0x00ff&((p) >> /* bits 7:0 / offset 00h */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) (fotg210_big_endian_capbase(fotg210) ? 24 : 0)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define HC_VERSION(fotg210, p) (0xffff&((p) >> /* bits 31:16 / offset 02h */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) (fotg210_big_endian_capbase(fotg210) ? 0 : 16)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) u32 hcs_params; /* HCSPARAMS - offset 0x4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define HCS_N_PORTS(p) (((p)>>0)&0xf) /* bits 3:0, ports on HC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) u32 hcc_params; /* HCCPARAMS - offset 0x8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define HCC_CANPARK(p) ((p)&(1 << 2)) /* true: can park on async qh */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define HCC_PGM_FRAMELISTLEN(p) ((p)&(1 << 1)) /* true: periodic_size changes*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) u8 portroute[8]; /* nibbles for routing - offset 0xC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) /* Section 2.3 Host Controller Operational Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) struct fotg210_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) /* USBCMD: offset 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) u32 command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) /* EHCI 1.1 addendum */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) /* 23:16 is r/w intr rate, in microframes; default "8" == 1/msec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define CMD_PARK (1<<11) /* enable "park" on async qh */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define CMD_PARK_CNT(c) (((c)>>8)&3) /* how many transfers to park for */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define CMD_IAAD (1<<6) /* "doorbell" interrupt async advance */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define CMD_ASE (1<<5) /* async schedule enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define CMD_PSE (1<<4) /* periodic schedule enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) /* 3:2 is periodic frame list size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define CMD_RESET (1<<1) /* reset HC not bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define CMD_RUN (1<<0) /* start/stop HC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) /* USBSTS: offset 0x04 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define STS_ASS (1<<15) /* Async Schedule Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define STS_PSS (1<<14) /* Periodic Schedule Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define STS_RECL (1<<13) /* Reclamation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define STS_HALT (1<<12) /* Not running (any reason) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) /* some bits reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) /* these STS_* flags are also intr_enable bits (USBINTR) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define STS_IAA (1<<5) /* Interrupted on async advance */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define STS_FATAL (1<<4) /* such as some PCI access errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define STS_FLR (1<<3) /* frame list rolled over */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define STS_PCD (1<<2) /* port change detect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define STS_ERR (1<<1) /* "error" completion (overflow, ...) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define STS_INT (1<<0) /* "normal" completion (short, ...) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) /* USBINTR: offset 0x08 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) u32 intr_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) /* FRINDEX: offset 0x0C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) u32 frame_index; /* current microframe number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) /* CTRLDSSEGMENT: offset 0x10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) u32 segment; /* address bits 63:32 if needed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) /* PERIODICLISTBASE: offset 0x14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) u32 frame_list; /* points to periodic list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) /* ASYNCLISTADDR: offset 0x18 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) u32 async_next; /* address of next async queue head */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) u32 reserved1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) /* PORTSC: offset 0x20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) u32 port_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) /* 31:23 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define PORT_USB11(x) (((x)&(3<<10)) == (1<<10)) /* USB 1.1 device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define PORT_RESET (1<<8) /* reset port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define PORT_SUSPEND (1<<7) /* suspend port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define PORT_RESUME (1<<6) /* resume it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define PORT_PEC (1<<3) /* port enable change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define PORT_PE (1<<2) /* port enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define PORT_CSC (1<<1) /* connect status change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define PORT_CONNECT (1<<0) /* device connected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define PORT_RWC_BITS (PORT_CSC | PORT_PEC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) u32 reserved2[19];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) /* OTGCSR: offet 0x70 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) u32 otgcsr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define OTGCSR_HOST_SPD_TYP (3 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define OTGCSR_A_BUS_DROP (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define OTGCSR_A_BUS_REQ (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) /* OTGISR: offset 0x74 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) u32 otgisr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define OTGISR_OVC (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) u32 reserved3[15];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) /* GMIR: offset 0xB4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) u32 gmir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define GMIR_INT_POLARITY (1 << 3) /*Active High*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define GMIR_MHC_INT (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define GMIR_MOTG_INT (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define GMIR_MDEV_INT (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) /*-------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define QTD_NEXT(fotg210, dma) cpu_to_hc32(fotg210, (u32)dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) * EHCI Specification 0.95 Section 3.5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) * QTD: describe data transfer components (buffer, direction, ...)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) * See Fig 3-6 "Queue Element Transfer Descriptor Block Diagram".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) * These are associated only with "QH" (Queue Head) structures,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) * used with control, bulk, and interrupt transfers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) struct fotg210_qtd {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) /* first part defined by EHCI spec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) __hc32 hw_next; /* see EHCI 3.5.1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) __hc32 hw_alt_next; /* see EHCI 3.5.2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) __hc32 hw_token; /* see EHCI 3.5.3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define QTD_TOGGLE (1 << 31) /* data toggle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define QTD_LENGTH(tok) (((tok)>>16) & 0x7fff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define QTD_IOC (1 << 15) /* interrupt on complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define QTD_CERR(tok) (((tok)>>10) & 0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define QTD_PID(tok) (((tok)>>8) & 0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define QTD_STS_ACTIVE (1 << 7) /* HC may execute this */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define QTD_STS_HALT (1 << 6) /* halted on error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define QTD_STS_DBE (1 << 5) /* data buffer error (in HC) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define QTD_STS_BABBLE (1 << 4) /* device was babbling (qtd halted) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define QTD_STS_XACT (1 << 3) /* device gave illegal response */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define QTD_STS_MMF (1 << 2) /* incomplete split transaction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define QTD_STS_STS (1 << 1) /* split transaction state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define QTD_STS_PING (1 << 0) /* issue PING? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define ACTIVE_BIT(fotg210) cpu_to_hc32(fotg210, QTD_STS_ACTIVE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define HALT_BIT(fotg210) cpu_to_hc32(fotg210, QTD_STS_HALT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define STATUS_BIT(fotg210) cpu_to_hc32(fotg210, QTD_STS_STS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) __hc32 hw_buf[5]; /* see EHCI 3.5.4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) __hc32 hw_buf_hi[5]; /* Appendix B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) /* the rest is HCD-private */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) dma_addr_t qtd_dma; /* qtd address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) struct list_head qtd_list; /* sw qtd list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) struct urb *urb; /* qtd's urb */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) size_t length; /* length of buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) } __aligned(32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) /* mask NakCnt+T in qh->hw_alt_next */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define QTD_MASK(fotg210) cpu_to_hc32(fotg210, ~0x1f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define IS_SHORT_READ(token) (QTD_LENGTH(token) != 0 && QTD_PID(token) == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) /*-------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) /* type tag from {qh,itd,fstn}->hw_next */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define Q_NEXT_TYPE(fotg210, dma) ((dma) & cpu_to_hc32(fotg210, 3 << 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) * Now the following defines are not converted using the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) * cpu_to_le32() macro anymore, since we have to support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) * "dynamic" switching between be and le support, so that the driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) * can be used on one system with SoC EHCI controller using big-endian
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) * descriptors as well as a normal little-endian PCI EHCI controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) /* values for that type tag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define Q_TYPE_ITD (0 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define Q_TYPE_QH (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define Q_TYPE_SITD (2 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define Q_TYPE_FSTN (3 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) /* next async queue entry, or pointer to interrupt/periodic QH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define QH_NEXT(fotg210, dma) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) (cpu_to_hc32(fotg210, (((u32)dma)&~0x01f)|Q_TYPE_QH))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) /* for periodic/async schedules and qtd lists, mark end of list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define FOTG210_LIST_END(fotg210) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) cpu_to_hc32(fotg210, 1) /* "null pointer" to hw */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) * Entries in periodic shadow table are pointers to one of four kinds
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) * of data structure. That's dictated by the hardware; a type tag is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) * encoded in the low bits of the hardware's periodic schedule. Use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) * Q_NEXT_TYPE to get the tag.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) * For entries in the async schedule, the type tag always says "qh".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) union fotg210_shadow {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) struct fotg210_qh *qh; /* Q_TYPE_QH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) struct fotg210_itd *itd; /* Q_TYPE_ITD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) struct fotg210_fstn *fstn; /* Q_TYPE_FSTN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) __hc32 *hw_next; /* (all types) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) void *ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) /*-------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) * EHCI Specification 0.95 Section 3.6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) * QH: describes control/bulk/interrupt endpoints
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) * See Fig 3-7 "Queue Head Structure Layout".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) * These appear in both the async and (for interrupt) periodic schedules.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) /* first part defined by EHCI spec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) struct fotg210_qh_hw {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) __hc32 hw_next; /* see EHCI 3.6.1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) __hc32 hw_info1; /* see EHCI 3.6.2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) #define QH_CONTROL_EP (1 << 27) /* FS/LS control endpoint */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #define QH_HEAD (1 << 15) /* Head of async reclamation list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) #define QH_TOGGLE_CTL (1 << 14) /* Data toggle control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) #define QH_HIGH_SPEED (2 << 12) /* Endpoint speed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) #define QH_LOW_SPEED (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) #define QH_FULL_SPEED (0 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) #define QH_INACTIVATE (1 << 7) /* Inactivate on next transaction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) __hc32 hw_info2; /* see EHCI 3.6.2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #define QH_SMASK 0x000000ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #define QH_CMASK 0x0000ff00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) #define QH_HUBADDR 0x007f0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) #define QH_HUBPORT 0x3f800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) #define QH_MULT 0xc0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) __hc32 hw_current; /* qtd list - see EHCI 3.6.4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) /* qtd overlay (hardware parts of a struct fotg210_qtd) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) __hc32 hw_qtd_next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) __hc32 hw_alt_next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) __hc32 hw_token;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) __hc32 hw_buf[5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) __hc32 hw_buf_hi[5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) } __aligned(32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) struct fotg210_qh {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) struct fotg210_qh_hw *hw; /* Must come first */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) /* the rest is HCD-private */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) dma_addr_t qh_dma; /* address of qh */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) union fotg210_shadow qh_next; /* ptr to qh; or periodic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) struct list_head qtd_list; /* sw qtd list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) struct list_head intr_node; /* list of intr QHs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) struct fotg210_qtd *dummy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) struct fotg210_qh *unlink_next; /* next on unlink list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) unsigned unlink_cycle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) u8 needs_rescan; /* Dequeue during giveback */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) u8 qh_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) #define QH_STATE_LINKED 1 /* HC sees this */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) #define QH_STATE_UNLINK 2 /* HC may still see this */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) #define QH_STATE_IDLE 3 /* HC doesn't see this */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) #define QH_STATE_UNLINK_WAIT 4 /* LINKED and on unlink q */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) #define QH_STATE_COMPLETING 5 /* don't touch token.HALT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) u8 xacterrs; /* XactErr retry counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) #define QH_XACTERR_MAX 32 /* XactErr retry limit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) /* periodic schedule info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) u8 usecs; /* intr bandwidth */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) u8 gap_uf; /* uframes split/csplit gap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) u8 c_usecs; /* ... split completion bw */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) u16 tt_usecs; /* tt downstream bandwidth */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) unsigned short period; /* polling interval */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) unsigned short start; /* where polling starts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) #define NO_FRAME ((unsigned short)~0) /* pick new start */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) struct usb_device *dev; /* access to TT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) unsigned is_out:1; /* bulk or intr OUT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) unsigned clearing_tt:1; /* Clear-TT-Buf in progress */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) /*-------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) /* description of one iso transaction (up to 3 KB data if highspeed) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) struct fotg210_iso_packet {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) /* These will be copied to iTD when scheduling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) u64 bufp; /* itd->hw_bufp{,_hi}[pg] |= */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) __hc32 transaction; /* itd->hw_transaction[i] |= */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) u8 cross; /* buf crosses pages */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) /* for full speed OUT splits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) u32 buf1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) /* temporary schedule data for packets from iso urbs (both speeds)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) * each packet is one logical usb transaction to the device (not TT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) * beginning at stream->next_uframe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) struct fotg210_iso_sched {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) struct list_head td_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) unsigned span;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) struct fotg210_iso_packet packet[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) * fotg210_iso_stream - groups all (s)itds for this endpoint.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) * acts like a qh would, if EHCI had them for ISO.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) struct fotg210_iso_stream {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) /* first field matches fotg210_hq, but is NULL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) struct fotg210_qh_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) u8 bEndpointAddress;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) u8 highspeed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) struct list_head td_list; /* queued itds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) struct list_head free_list; /* list of unused itds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) struct usb_device *udev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) struct usb_host_endpoint *ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) /* output of (re)scheduling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) int next_uframe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) __hc32 splits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) /* the rest is derived from the endpoint descriptor,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) * trusting urb->interval == f(epdesc->bInterval) and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) * including the extra info for hw_bufp[0..2]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) u8 usecs, c_usecs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) u16 interval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) u16 tt_usecs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) u16 maxp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) u16 raw_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) unsigned bandwidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) /* This is used to initialize iTD's hw_bufp fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) __hc32 buf0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) __hc32 buf1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) __hc32 buf2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) /* this is used to initialize sITD's tt info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) __hc32 address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) /*-------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) * EHCI Specification 0.95 Section 3.3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) * Fig 3-4 "Isochronous Transaction Descriptor (iTD)"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) * Schedule records for high speed iso xfers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) struct fotg210_itd {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) /* first part defined by EHCI spec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) __hc32 hw_next; /* see EHCI 3.3.1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) __hc32 hw_transaction[8]; /* see EHCI 3.3.2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) #define FOTG210_ISOC_ACTIVE (1<<31) /* activate transfer this slot */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) #define FOTG210_ISOC_BUF_ERR (1<<30) /* Data buffer error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) #define FOTG210_ISOC_BABBLE (1<<29) /* babble detected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) #define FOTG210_ISOC_XACTERR (1<<28) /* XactErr - transaction error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) #define FOTG210_ITD_LENGTH(tok) (((tok)>>16) & 0x0fff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) #define FOTG210_ITD_IOC (1 << 15) /* interrupt on complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) #define ITD_ACTIVE(fotg210) cpu_to_hc32(fotg210, FOTG210_ISOC_ACTIVE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) __hc32 hw_bufp[7]; /* see EHCI 3.3.3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) __hc32 hw_bufp_hi[7]; /* Appendix B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) /* the rest is HCD-private */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) dma_addr_t itd_dma; /* for this itd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) union fotg210_shadow itd_next; /* ptr to periodic q entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) struct urb *urb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) struct fotg210_iso_stream *stream; /* endpoint's queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) struct list_head itd_list; /* list of stream's itds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) /* any/all hw_transactions here may be used by that urb */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) unsigned frame; /* where scheduled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) unsigned pg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) unsigned index[8]; /* in urb->iso_frame_desc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) } __aligned(32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) /*-------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) * EHCI Specification 0.96 Section 3.7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) * Periodic Frame Span Traversal Node (FSTN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) * Manages split interrupt transactions (using TT) that span frame boundaries
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) * into uframes 0/1; see 4.12.2.2. In those uframes, a "save place" FSTN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) * makes the HC jump (back) to a QH to scan for fs/ls QH completions until
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) * it hits a "restore" FSTN; then it returns to finish other uframe 0/1 work.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) struct fotg210_fstn {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) __hc32 hw_next; /* any periodic q entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) __hc32 hw_prev; /* qh or FOTG210_LIST_END */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) /* the rest is HCD-private */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) dma_addr_t fstn_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) union fotg210_shadow fstn_next; /* ptr to periodic q entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) } __aligned(32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) /*-------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) /* Prepare the PORTSC wakeup flags during controller suspend/resume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) #define fotg210_prepare_ports_for_controller_suspend(fotg210, do_wakeup) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) fotg210_adjust_port_wakeup_flags(fotg210, true, do_wakeup)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) #define fotg210_prepare_ports_for_controller_resume(fotg210) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) fotg210_adjust_port_wakeup_flags(fotg210, false, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) /*-------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) * Some EHCI controllers have a Transaction Translator built into the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) * root hub. This is a non-standard feature. Each controller will need
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) * to add code to the following inline functions, and call them as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) * needed (mostly in root hub code).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) static inline unsigned int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) fotg210_get_speed(struct fotg210_hcd *fotg210, unsigned int portsc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) return (readl(&fotg210->regs->otgcsr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) & OTGCSR_HOST_SPD_TYP) >> 22;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) /* Returns the speed of a device attached to a port on the root hub. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) static inline unsigned int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) fotg210_port_speed(struct fotg210_hcd *fotg210, unsigned int portsc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) switch (fotg210_get_speed(fotg210, portsc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) return USB_PORT_STAT_LOW_SPEED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) return USB_PORT_STAT_HIGH_SPEED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) /*-------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) #define fotg210_has_fsl_portno_bug(e) (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) * While most USB host controllers implement their registers in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) * little-endian format, a minority (celleb companion chip) implement
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) * them in big endian format.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) * This attempts to support either format at compile time without a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) * runtime penalty, or both formats with the additional overhead
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) * of checking a flag bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) #define fotg210_big_endian_mmio(e) 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) #define fotg210_big_endian_capbase(e) 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) static inline unsigned int fotg210_readl(const struct fotg210_hcd *fotg210,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) __u32 __iomem *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) return readl(regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) static inline void fotg210_writel(const struct fotg210_hcd *fotg210,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) const unsigned int val, __u32 __iomem *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) writel(val, regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) /* cpu to fotg210 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) static inline __hc32 cpu_to_hc32(const struct fotg210_hcd *fotg210, const u32 x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) return cpu_to_le32(x);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) /* fotg210 to cpu */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) static inline u32 hc32_to_cpu(const struct fotg210_hcd *fotg210, const __hc32 x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) return le32_to_cpu(x);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) static inline u32 hc32_to_cpup(const struct fotg210_hcd *fotg210,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) const __hc32 *x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) return le32_to_cpup(x);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) /*-------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) static inline unsigned fotg210_read_frame_index(struct fotg210_hcd *fotg210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) return fotg210_readl(fotg210, &fotg210->regs->frame_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) /*-------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) #endif /* __LINUX_FOTG210_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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