^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0+ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Freescale QUICC Engine USB Host Controller Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) Freescale Semicondutor, Inc. 2006.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Shlomi Gridish <gridish@freescale.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Jerry Huang <Chang-Ming.Huang@freescale.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (c) Logic Product Development, Inc. 2007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Peter Barada <peterb@logicpd.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Copyright (c) MontaVista Software, Inc. 2008.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Anton Vorontsov <avorontsov@ru.mvista.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #ifndef __FHCI_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define __FHCI_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/bug.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/kfifo.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/usb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/usb/hcd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <soc/fsl/qe/qe.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <soc/fsl/qe/immap_qe.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define USB_CLOCK 48000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define FHCI_PRAM_SIZE 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define MAX_EDS 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define MAX_TDS 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /* CRC16 field size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define CRC_SIZE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /* USB protocol overhead for each frame transmitted from the host */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define PROTOCOL_OVERHEAD 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* Packet structure, info field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define PKT_PID_DATA0 0x80000000 /* PID - Data toggle zero */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define PKT_PID_DATA1 0x40000000 /* PID - Data toggle one */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define PKT_PID_SETUP 0x20000000 /* PID - Setup bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define PKT_SETUP_STATUS 0x10000000 /* Setup status bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define PKT_SETADDR_STATUS 0x08000000 /* Set address status bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define PKT_SET_HOST_LAST 0x04000000 /* Last data packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define PKT_HOST_DATA 0x02000000 /* Data packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define PKT_FIRST_IN_FRAME 0x01000000 /* First packet in the frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define PKT_TOKEN_FRAME 0x00800000 /* Token packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define PKT_ZLP 0x00400000 /* Zero length packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define PKT_IN_TOKEN_FRAME 0x00200000 /* IN token packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define PKT_OUT_TOKEN_FRAME 0x00100000 /* OUT token packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define PKT_SETUP_TOKEN_FRAME 0x00080000 /* SETUP token packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define PKT_STALL_FRAME 0x00040000 /* STALL packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define PKT_NACK_FRAME 0x00020000 /* NACK packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define PKT_NO_PID 0x00010000 /* No PID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define PKT_NO_CRC 0x00008000 /* don't append CRC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define PKT_HOST_COMMAND 0x00004000 /* Host command packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define PKT_DUMMY_PACKET 0x00002000 /* Dummy packet, used for mmm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define PKT_LOW_SPEED_PACKET 0x00001000 /* Low-Speed packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define TRANS_OK (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define TRANS_INPROGRESS (-1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define TRANS_DISCARD (-2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define TRANS_FAIL (-3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define PS_INT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define PS_DISCONNECTED 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define PS_CONNECTED 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define PS_READY 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define PS_MISSING 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /* Transfer Descriptor status field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define USB_TD_OK 0x00000000 /* TD transmited or received ok */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define USB_TD_INPROGRESS 0x80000000 /* TD is being transmitted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define USB_TD_RX_ER_NONOCT 0x40000000 /* Tx Non Octet Aligned Packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define USB_TD_RX_ER_BITSTUFF 0x20000000 /* Frame Aborted-Received pkt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define USB_TD_RX_ER_CRC 0x10000000 /* CRC error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define USB_TD_RX_ER_OVERUN 0x08000000 /* Over - run occurred */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define USB_TD_RX_ER_PID 0x04000000 /* wrong PID received */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define USB_TD_RX_DATA_UNDERUN 0x02000000 /* shorter than expected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define USB_TD_RX_DATA_OVERUN 0x01000000 /* longer than expected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define USB_TD_TX_ER_NAK 0x00800000 /* NAK handshake */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define USB_TD_TX_ER_STALL 0x00400000 /* STALL handshake */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define USB_TD_TX_ER_TIMEOUT 0x00200000 /* transmit time out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define USB_TD_TX_ER_UNDERUN 0x00100000 /* transmit underrun */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define USB_TD_ERROR (USB_TD_RX_ER_NONOCT | USB_TD_RX_ER_BITSTUFF | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) USB_TD_RX_ER_CRC | USB_TD_RX_ER_OVERUN | USB_TD_RX_ER_PID | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) USB_TD_RX_DATA_UNDERUN | USB_TD_RX_DATA_OVERUN | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) USB_TD_TX_ER_NAK | USB_TD_TX_ER_STALL | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) USB_TD_TX_ER_TIMEOUT | USB_TD_TX_ER_UNDERUN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /* Transfer Descriptor toggle field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define USB_TD_TOGGLE_DATA0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define USB_TD_TOGGLE_DATA1 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define USB_TD_TOGGLE_CARRY 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /* #define MULTI_DATA_BUS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /* Bus mode register RBMR/TBMR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define BUS_MODE_GBL 0x20 /* Global snooping */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define BUS_MODE_BO 0x18 /* Byte ordering */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define BUS_MODE_BO_BE 0x10 /* Byte ordering - Big-endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define BUS_MODE_DTB 0x02 /* Data bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /* FHCI QE USB Register Description */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /* USB Mode Register bit define */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define USB_MODE_EN 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define USB_MODE_HOST 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define USB_MODE_TEST 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define USB_MODE_SFTE 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define USB_MODE_RESUME 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define USB_MODE_LSS 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /* USB Slave Address Register Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define USB_SLVADDR_MASK 0x7F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /* USB Endpoint register define */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define USB_EPNUM_MASK 0xF000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define USB_EPNUM_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define USB_TRANS_MODE_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define USB_TRANS_CTR 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define USB_TRANS_INT 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define USB_TRANS_BULK 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define USB_TRANS_ISO 0x0300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define USB_EP_MF 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define USB_EP_RTE 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define USB_THS_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define USB_THS_MASK 0x000c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define USB_THS_NORMAL 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define USB_THS_IGNORE_IN 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define USB_THS_NACK 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define USB_THS_STALL 0x000c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define USB_RHS_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define USB_RHS_MASK 0x0003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define USB_RHS_NORMAL 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define USB_RHS_IGNORE_OUT 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define USB_RHS_NACK 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define USB_RHS_STALL 0x0003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define USB_RTHS_MASK 0x000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /* USB Command Register define */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define USB_CMD_STR_FIFO 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define USB_CMD_FLUSH_FIFO 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define USB_CMD_ISFT 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define USB_CMD_DSFT 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define USB_CMD_EP_MASK 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /* USB Event and Mask Register define */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define USB_E_MSF_MASK 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define USB_E_SFT_MASK 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define USB_E_RESET_MASK 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define USB_E_IDLE_MASK 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define USB_E_TXE4_MASK 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define USB_E_TXE3_MASK 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define USB_E_TXE2_MASK 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define USB_E_TXE1_MASK 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define USB_E_SOF_MASK 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define USB_E_BSY_MASK 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define USB_E_TXB_MASK 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define USB_E_RXB_MASK 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) /* Freescale USB HOST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) struct fhci_pram {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) __be16 ep_ptr[4]; /* Endpoint porter reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) __be32 rx_state; /* Rx internal state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) __be32 rx_ptr; /* Rx internal data pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) __be16 frame_num; /* Frame number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) __be16 rx_cnt; /* Rx byte count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) __be32 rx_temp; /* Rx temp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) __be32 rx_data_temp; /* Rx data temp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) __be16 rx_u_ptr; /* Rx microcode return address temp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) u8 reserved1[2]; /* reserved area */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) __be32 sof_tbl; /* SOF lookup table pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) u8 sof_u_crc_temp; /* SOF micorcode CRC5 temp reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) u8 reserved2[0xdb];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /* Freescale USB Endpoint*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) struct fhci_ep_pram {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) __be16 rx_base; /* Rx BD base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) __be16 tx_base; /* Tx BD base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) u8 rx_func_code; /* Rx function code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) u8 tx_func_code; /* Tx function code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) __be16 rx_buff_len; /* Rx buffer length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) __be16 rx_bd_ptr; /* Rx BD pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) __be16 tx_bd_ptr; /* Tx BD pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) __be32 tx_state; /* Tx internal state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) __be32 tx_ptr; /* Tx internal data pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) __be16 tx_crc; /* temp transmit CRC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) __be16 tx_cnt; /* Tx byte count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) __be32 tx_temp; /* Tx temp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) __be16 tx_u_ptr; /* Tx microcode return address temp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) __be16 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) struct fhci_controller_list {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) struct list_head ctrl_list; /* control endpoints */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) struct list_head bulk_list; /* bulk endpoints */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) struct list_head iso_list; /* isochronous endpoints */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) struct list_head intr_list; /* interruput endpoints */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) struct list_head done_list; /* done transfers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) struct virtual_root_hub {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) int dev_num; /* USB address of the root hub */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) u32 feature; /* indicates what feature has been set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) struct usb_hub_status hub;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) struct usb_port_status port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) enum fhci_gpios {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) GPIO_USBOE = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) GPIO_USBTP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) GPIO_USBTN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) GPIO_USBRP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) GPIO_USBRN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) /* these are optional */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) GPIO_SPEED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) GPIO_POWER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) NUM_GPIOS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) enum fhci_pins {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) PIN_USBOE = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) PIN_USBTP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) PIN_USBTN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) NUM_PINS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) struct fhci_hcd {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) enum qe_clock fullspeed_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) enum qe_clock lowspeed_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) struct qe_pin *pins[NUM_PINS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) int gpios[NUM_GPIOS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) bool alow_gpios[NUM_GPIOS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) struct qe_usb_ctlr __iomem *regs; /* I/O memory used to communicate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) struct fhci_pram __iomem *pram; /* Parameter RAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) struct gtm_timer *timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) struct fhci_usb *usb_lld; /* Low-level driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) struct virtual_root_hub *vroot_hub; /* the virtual root hub */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) int active_urbs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) struct fhci_controller_list *hc_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) struct tasklet_struct *process_done_task; /* tasklet for done list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) struct list_head empty_eds;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) struct list_head empty_tds;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #ifdef CONFIG_FHCI_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) int usb_irq_stat[13];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) struct dentry *dfs_root;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define USB_FRAME_USAGE 90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define FRAME_TIME_USAGE (USB_FRAME_USAGE*10) /* frame time usage */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define SW_FIX_TIME_BETWEEN_TRANSACTION 150 /* SW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define MAX_BYTES_PER_FRAME (USB_FRAME_USAGE*15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define MAX_PERIODIC_FRAME_USAGE 90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) /* transaction type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) enum fhci_ta_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) FHCI_TA_IN = 0, /* input transaction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) FHCI_TA_OUT, /* output transaction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) FHCI_TA_SETUP, /* setup transaction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) /* transfer mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) enum fhci_tf_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) FHCI_TF_CTRL = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) FHCI_TF_ISO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) FHCI_TF_BULK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) FHCI_TF_INTR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) enum fhci_speed {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) FHCI_FULL_SPEED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) FHCI_LOW_SPEED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) /* endpoint state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) enum fhci_ed_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) FHCI_ED_NEW = 0, /* pipe is new */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) FHCI_ED_OPER, /* pipe is operating */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) FHCI_ED_URB_DEL, /* pipe is in hold because urb is being deleted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) FHCI_ED_SKIP, /* skip this pipe */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) FHCI_ED_HALTED, /* pipe is halted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) enum fhci_port_status {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) FHCI_PORT_POWER_OFF = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) FHCI_PORT_DISABLED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) FHCI_PORT_DISCONNECTING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) FHCI_PORT_WAITING, /* waiting for connection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) FHCI_PORT_FULL, /* full speed connected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) FHCI_PORT_LOW, /* low speed connected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) enum fhci_mem_alloc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) MEM_CACHABLE_SYS = 0x00000001, /* primary DDR,cachable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) MEM_NOCACHE_SYS = 0x00000004, /* primary DDR,non-cachable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) MEM_SECONDARY = 0x00000002, /* either secondary DDR or SDRAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) MEM_PRAM = 0x00000008, /* multi-user RAM identifier */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) /* USB default parameters*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define DEFAULT_RING_LEN 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define DEFAULT_DATA_MEM MEM_CACHABLE_SYS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) struct ed {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) u8 dev_addr; /* device address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) u8 ep_addr; /* endpoint address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) enum fhci_tf_mode mode; /* USB transfer mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) enum fhci_speed speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) unsigned int max_pkt_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) enum fhci_ed_state state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) struct list_head td_list; /* a list of all queued TD to this pipe */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) struct list_head node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) /* read only parameters, should be cleared upon initialization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) u8 toggle_carry; /* toggle carry from the last TD submitted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) u16 next_iso; /* time stamp of next queued ISO transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) struct td *td_head; /* a pointer to the current TD handled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) struct td {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) void *data; /* a pointer to the data buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) unsigned int len; /* length of the data to be submitted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) unsigned int actual_len; /* actual bytes transferred on this td */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) enum fhci_ta_type type; /* transaction type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) u8 toggle; /* toggle for next trans. within this TD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) u16 iso_index; /* ISO transaction index */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) u16 start_frame; /* start frame time stamp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) u16 interval; /* interval between trans. (for ISO/Intr) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) u32 status; /* status of the TD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) struct ed *ed; /* a handle to the corresponding ED */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) struct urb *urb; /* a handle to the corresponding URB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) bool ioc; /* Inform On Completion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) struct list_head node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) /* read only parameters should be cleared upon initialization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) struct packet *pkt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) int nak_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) int error_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) struct list_head frame_lh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) struct packet {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) u8 *data; /* packet data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) u32 len; /* packet length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) u32 status; /* status of the packet - equivalent to the status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) * field for the corresponding structure td */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) u32 info; /* packet information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) void __iomem *priv_data; /* private data of the driver (TDs or BDs) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) /* struct for each URB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define URB_INPROGRESS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define URB_DEL 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) /* URB states (state field) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define US_BULK 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define US_BULK0 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) /* three setup states */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define US_CTRL_SETUP 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define US_CTRL_DATA 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define US_CTRL_ACK 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define EP_ZERO 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) struct urb_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) int num_of_tds;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) int tds_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) int state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) struct td **tds;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) struct ed *ed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) struct timer_list time_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) struct endpoint {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) /* Pointer to ep parameter RAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) struct fhci_ep_pram __iomem *ep_pram_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) /* Host transactions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) struct usb_td __iomem *td_base; /* first TD in the ring */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) struct usb_td __iomem *conf_td; /* next TD for confirm after transac */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) struct usb_td __iomem *empty_td;/* next TD for new transaction req. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) struct kfifo empty_frame_Q; /* Empty frames list to use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) struct kfifo conf_frame_Q; /* frames passed to TDs,waiting for tx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) struct kfifo dummy_packets_Q;/* dummy packets for the CRC overun */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) bool already_pushed_dummy_bd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) /* struct for each 1mSec frame time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #define FRAME_IS_TRANSMITTED 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #define FRAME_TIMER_END_TRANSMISSION 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #define FRAME_DATA_END_TRANSMISSION 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) #define FRAME_END_TRANSMISSION 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #define FRAME_IS_PREPARED 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) struct fhci_time_frame {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) u16 frame_num; /* frame number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) u16 total_bytes; /* total bytes submitted within this frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) u8 frame_status; /* flag that indicates to stop fill this frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) struct list_head tds_list; /* all tds of this frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) /* internal driver structure*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) struct fhci_usb {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) u16 saved_msk; /* saving of the USB mask register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) struct endpoint *ep0; /* pointer for endpoint0 structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) int intr_nesting_cnt; /* interrupt nesting counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) u16 max_frame_usage; /* max frame time usage,in micro-sec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) u16 max_bytes_per_frame; /* max byte can be tx in one time frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) u32 sw_transaction_time; /* sw complete trans time,in micro-sec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) struct fhci_time_frame *actual_frame;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) struct fhci_controller_list *hc_list; /* main structure for hc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) struct virtual_root_hub *vroot_hub;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) enum fhci_port_status port_status; /* v_rh port status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) u32 (*transfer_confirm)(struct fhci_hcd *fhci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) struct fhci_hcd *fhci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) * Various helpers and prototypes below.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) static inline u16 get_frame_num(struct fhci_hcd *fhci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) return in_be16(&fhci->pram->frame_num) & 0x07ff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) #define fhci_dbg(fhci, fmt, args...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) dev_dbg(fhci_to_hcd(fhci)->self.controller, fmt, ##args)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) #define fhci_vdbg(fhci, fmt, args...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) dev_vdbg(fhci_to_hcd(fhci)->self.controller, fmt, ##args)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) #define fhci_err(fhci, fmt, args...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) dev_err(fhci_to_hcd(fhci)->self.controller, fmt, ##args)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) #define fhci_info(fhci, fmt, args...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) dev_info(fhci_to_hcd(fhci)->self.controller, fmt, ##args)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) #define fhci_warn(fhci, fmt, args...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) dev_warn(fhci_to_hcd(fhci)->self.controller, fmt, ##args)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) static inline struct fhci_hcd *hcd_to_fhci(struct usb_hcd *hcd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) return (struct fhci_hcd *)hcd->hcd_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) static inline struct usb_hcd *fhci_to_hcd(struct fhci_hcd *fhci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) return container_of((void *)fhci, struct usb_hcd, hcd_priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) /* fifo of pointers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) static inline int cq_new(struct kfifo *fifo, int size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) return kfifo_alloc(fifo, size * sizeof(void *), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) static inline void cq_delete(struct kfifo *kfifo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) kfifo_free(kfifo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) static inline unsigned int cq_howmany(struct kfifo *kfifo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) return kfifo_len(kfifo) / sizeof(void *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) static inline int cq_put(struct kfifo *kfifo, void *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) return kfifo_in(kfifo, (void *)&p, sizeof(p));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) static inline void *cq_get(struct kfifo *kfifo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) unsigned int sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) void *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) sz = kfifo_out(kfifo, (void *)&p, sizeof(p));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) if (sz != sizeof(p))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) return p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) /* fhci-hcd.c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) void fhci_start_sof_timer(struct fhci_hcd *fhci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) void fhci_stop_sof_timer(struct fhci_hcd *fhci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) u16 fhci_get_sof_timer_count(struct fhci_usb *usb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) void fhci_usb_enable_interrupt(struct fhci_usb *usb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) void fhci_usb_disable_interrupt(struct fhci_usb *usb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) int fhci_ioports_check_bus_state(struct fhci_hcd *fhci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) /* fhci-mem.c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) void fhci_recycle_empty_td(struct fhci_hcd *fhci, struct td *td);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) void fhci_recycle_empty_ed(struct fhci_hcd *fhci, struct ed *ed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) struct ed *fhci_get_empty_ed(struct fhci_hcd *fhci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) struct td *fhci_td_fill(struct fhci_hcd *fhci, struct urb *urb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) struct urb_priv *urb_priv, struct ed *ed, u16 index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) enum fhci_ta_type type, int toggle, u8 *data, u32 len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) u16 interval, u16 start_frame, bool ioc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) void fhci_add_tds_to_ed(struct ed *ed, struct td **td_list, int number);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) /* fhci-hub.c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) void fhci_config_transceiver(struct fhci_hcd *fhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) enum fhci_port_status status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) void fhci_port_disable(struct fhci_hcd *fhci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) void fhci_port_enable(void *lld);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) void fhci_io_port_generate_reset(struct fhci_hcd *fhci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) void fhci_port_reset(void *lld);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) int fhci_hub_status_data(struct usb_hcd *hcd, char *buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) int fhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) u16 wIndex, char *buf, u16 wLength);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) /* fhci-tds.c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) void fhci_flush_bds(struct fhci_usb *usb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) void fhci_flush_actual_frame(struct fhci_usb *usb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) u32 fhci_host_transaction(struct fhci_usb *usb, struct packet *pkt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) enum fhci_ta_type trans_type, u8 dest_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) u8 dest_ep, enum fhci_tf_mode trans_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) enum fhci_speed dest_speed, u8 data_toggle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) void fhci_host_transmit_actual_frame(struct fhci_usb *usb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) void fhci_tx_conf_interrupt(struct fhci_usb *usb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) void fhci_push_dummy_bd(struct endpoint *ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) u32 fhci_create_ep(struct fhci_usb *usb, enum fhci_mem_alloc data_mem,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) u32 ring_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) void fhci_init_ep_registers(struct fhci_usb *usb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) struct endpoint *ep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) enum fhci_mem_alloc data_mem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) void fhci_ep0_free(struct fhci_usb *usb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) /* fhci-sched.c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) extern struct tasklet_struct fhci_tasklet;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) void fhci_transaction_confirm(struct fhci_usb *usb, struct packet *pkt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) void fhci_flush_all_transmissions(struct fhci_usb *usb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) void fhci_schedule_transactions(struct fhci_usb *usb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) void fhci_device_connected_interrupt(struct fhci_hcd *fhci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) void fhci_device_disconnected_interrupt(struct fhci_hcd *fhci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) void fhci_queue_urb(struct fhci_hcd *fhci, struct urb *urb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) u32 fhci_transfer_confirm_callback(struct fhci_hcd *fhci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) irqreturn_t fhci_irq(struct usb_hcd *hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) irqreturn_t fhci_frame_limit_timer_irq(int irq, void *_hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) /* fhci-q.h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) void fhci_urb_complete_free(struct fhci_hcd *fhci, struct urb *urb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) struct td *fhci_remove_td_from_ed(struct ed *ed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) struct td *fhci_remove_td_from_frame(struct fhci_time_frame *frame);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) void fhci_move_td_from_ed_to_done_list(struct fhci_usb *usb, struct ed *ed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) struct td *fhci_peek_td_from_frame(struct fhci_time_frame *frame);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) void fhci_add_td_to_frame(struct fhci_time_frame *frame, struct td *td);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) struct td *fhci_remove_td_from_done_list(struct fhci_controller_list *p_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) void fhci_done_td(struct urb *urb, struct td *td);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) void fhci_del_ed_list(struct fhci_hcd *fhci, struct ed *ed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) #ifdef CONFIG_FHCI_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) void fhci_dbg_isr(struct fhci_hcd *fhci, int usb_er);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) void fhci_dfs_destroy(struct fhci_hcd *fhci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) void fhci_dfs_create(struct fhci_hcd *fhci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) static inline void fhci_dbg_isr(struct fhci_hcd *fhci, int usb_er) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) static inline void fhci_dfs_destroy(struct fhci_hcd *fhci) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) static inline void fhci_dfs_create(struct fhci_hcd *fhci) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) #endif /* CONFIG_FHCI_DEBUG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) #endif /* __FHCI_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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