^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0+ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2001-2002 by David Brownell
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #ifndef __LINUX_EHCI_HCD_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define __LINUX_EHCI_HCD_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) /* definitions used for the EHCI driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * __hc32 and __hc16 are "Host Controller" types, they may be equivalent to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * __leXX (normally) or __beXX (given EHCI_BIG_ENDIAN_DESC), depending on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * the host controller implementation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * To facilitate the strongest possible byte-order checking from "sparse"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * and so on, we use __leXX unless that's not practical.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) typedef __u32 __bitwise __hc32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) typedef __u16 __bitwise __hc16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define __hc32 __le32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define __hc16 __le16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /* statistics can be kept for tuning/monitoring */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #ifdef CONFIG_DYNAMIC_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define EHCI_STATS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) struct ehci_stats {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /* irq usage */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) unsigned long normal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) unsigned long error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) unsigned long iaa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) unsigned long lost_iaa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /* termination of urbs from core */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) unsigned long complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) unsigned long unlink;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * Scheduling and budgeting information for periodic transfers, for both
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * high-speed devices and full/low-speed devices lying behind a TT.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) struct ehci_per_sched {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) struct usb_device *udev; /* access to the TT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) struct usb_host_endpoint *ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) struct list_head ps_list; /* node on ehci_tt's ps_list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) u16 tt_usecs; /* time on the FS/LS bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) u16 cs_mask; /* C-mask and S-mask bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) u16 period; /* actual period in frames */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) u16 phase; /* actual phase, frame part */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) u8 bw_phase; /* same, for bandwidth
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) reservation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) u8 phase_uf; /* uframe part of the phase */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) u8 usecs, c_usecs; /* times on the HS bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) u8 bw_uperiod; /* period in microframes, for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) bandwidth reservation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) u8 bw_period; /* same, in frames */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define NO_FRAME 29999 /* frame not assigned yet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /* ehci_hcd->lock guards shared data against other CPUs:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * ehci_hcd: async, unlink, periodic (and shadow), ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * usb_host_endpoint: hcpriv
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * ehci_qh: qh_next, qtd_list
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * ehci_qtd: qtd_list
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * Also, hold this lock when talking to HC registers or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * when updating hw_* fields in shared qh/qtd/... structures.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define EHCI_MAX_ROOT_PORTS 15 /* see HCS_N_PORTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * ehci_rh_state values of EHCI_RH_RUNNING or above mean that the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * controller may be doing DMA. Lower values mean there's no DMA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) enum ehci_rh_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) EHCI_RH_HALTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) EHCI_RH_SUSPENDED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) EHCI_RH_RUNNING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) EHCI_RH_STOPPING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * Timer events, ordered by increasing delay length.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * Always update event_delays_ns[] and event_handlers[] (defined in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * ehci-timer.c) in parallel with this list.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) enum ehci_hrtimer_event {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) EHCI_HRTIMER_POLL_ASS, /* Poll for async schedule off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) EHCI_HRTIMER_POLL_PSS, /* Poll for periodic schedule off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) EHCI_HRTIMER_POLL_DEAD, /* Wait for dead controller to stop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) EHCI_HRTIMER_UNLINK_INTR, /* Wait for interrupt QH unlink */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) EHCI_HRTIMER_FREE_ITDS, /* Wait for unused iTDs and siTDs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) EHCI_HRTIMER_ACTIVE_UNLINK, /* Wait while unlinking an active QH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) EHCI_HRTIMER_START_UNLINK_INTR, /* Unlink empty interrupt QHs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) EHCI_HRTIMER_ASYNC_UNLINKS, /* Unlink empty async QHs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) EHCI_HRTIMER_IAA_WATCHDOG, /* Handle lost IAA interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) EHCI_HRTIMER_DISABLE_PERIODIC, /* Wait to disable periodic sched */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) EHCI_HRTIMER_DISABLE_ASYNC, /* Wait to disable async sched */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) EHCI_HRTIMER_IO_WATCHDOG, /* Check for missing IRQs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) EHCI_HRTIMER_NUM_EVENTS /* Must come last */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define EHCI_HRTIMER_NO_EVENT 99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) struct ehci_hcd { /* one per controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /* timing support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) enum ehci_hrtimer_event next_hrtimer_event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) unsigned enabled_hrtimer_events;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) ktime_t hr_timeouts[EHCI_HRTIMER_NUM_EVENTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) struct hrtimer hrtimer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) int PSS_poll_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) int ASS_poll_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) int died_poll_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) /* glue to PCI and HCD framework */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) struct ehci_caps __iomem *caps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) struct ehci_regs __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) struct ehci_dbg_port __iomem *debug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) __u32 hcs_params; /* cached register copy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) enum ehci_rh_state rh_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /* general schedule support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) bool scanning:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) bool need_rescan:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) bool intr_unlinking:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) bool iaa_in_progress:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) bool async_unlinking:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) bool shutdown:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) struct ehci_qh *qh_scan_next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) /* async schedule support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) struct ehci_qh *async;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) struct ehci_qh *dummy; /* For AMD quirk use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) struct list_head async_unlink;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct list_head async_idle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) unsigned async_unlink_cycle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) unsigned async_count; /* async activity count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) __hc32 old_current; /* Test for QH becoming */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) __hc32 old_token; /* inactive during unlink */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) /* periodic schedule support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define DEFAULT_I_TDPS 1024 /* some HCs can do less */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) unsigned periodic_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) __hc32 *periodic; /* hw periodic table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) dma_addr_t periodic_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) struct list_head intr_qh_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) unsigned i_thresh; /* uframes HC might cache */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) union ehci_shadow *pshadow; /* mirror hw periodic table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) struct list_head intr_unlink_wait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) struct list_head intr_unlink;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) unsigned intr_unlink_wait_cycle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) unsigned intr_unlink_cycle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) unsigned now_frame; /* frame from HC hardware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) unsigned last_iso_frame; /* last frame scanned for iso */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) unsigned intr_count; /* intr activity count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) unsigned isoc_count; /* isoc activity count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) unsigned periodic_count; /* periodic activity count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) unsigned uframe_periodic_max; /* max periodic time per uframe */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /* list of itds & sitds completed while now_frame was still active */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) struct list_head cached_itd_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) struct ehci_itd *last_itd_to_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) struct list_head cached_sitd_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) struct ehci_sitd *last_sitd_to_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /* per root hub port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) unsigned long reset_done[EHCI_MAX_ROOT_PORTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) /* bit vectors (one bit per port) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) unsigned long bus_suspended; /* which ports were
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) already suspended at the start of a bus suspend */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) unsigned long companion_ports; /* which ports are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) dedicated to the companion controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) unsigned long owned_ports; /* which ports are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) owned by the companion during a bus suspend */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) unsigned long port_c_suspend; /* which ports have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) the change-suspend feature turned on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) unsigned long suspended_ports; /* which ports are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) suspended */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) unsigned long resuming_ports; /* which ports have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) started to resume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) /* per-HC memory pools (could be per-bus, but ...) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) struct dma_pool *qh_pool; /* qh per active urb */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) struct dma_pool *qtd_pool; /* one or more per qh */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) struct dma_pool *itd_pool; /* itd per iso urb */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) struct dma_pool *sitd_pool; /* sitd per split iso urb */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) unsigned random_frame;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) unsigned long next_statechange;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) ktime_t last_periodic_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) u32 command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) /* SILICON QUIRKS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) unsigned no_selective_suspend:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) unsigned has_fsl_port_bug:1; /* FreeScale */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) unsigned has_fsl_hs_errata:1; /* Freescale HS quirk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) unsigned has_fsl_susp_errata:1; /* NXP SUSP quirk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) unsigned big_endian_mmio:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) unsigned big_endian_desc:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) unsigned big_endian_capbase:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) unsigned has_amcc_usb23:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) unsigned need_io_watchdog:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) unsigned amd_pll_fix:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) unsigned use_dummy_qh:1; /* AMD Frame List table quirk*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) unsigned has_synopsys_hc_bug:1; /* Synopsys HC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) unsigned frame_index_bug:1; /* MosChip (AKA NetMos) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) unsigned need_oc_pp_cycle:1; /* MPC834X port power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) unsigned imx28_write_fix:1; /* For Freescale i.MX28 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) * __GENKSYMS__ test is an abi workaround for commit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) * 7f2d73788d90 ("usb: ehci: handshake CMD_RUN * instead of STS_HALT")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #ifndef __GENKSYMS__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) unsigned is_aspeed:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) /* required for usb32 quirk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define OHCI_CTRL_HCFS (3 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define OHCI_USB_OPER (2 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define OHCI_USB_SUSPEND (3 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define OHCI_HCCTRL_OFFSET 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define OHCI_HCCTRL_LEN 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) __hc32 *ohci_hcctrl_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) unsigned has_hostpc:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) unsigned has_tdi_phy_lpm:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) unsigned has_ppcd:1; /* support per-port change bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) u8 sbrn; /* packed release number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) /* irq statistics */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #ifdef EHCI_STATS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) struct ehci_stats stats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) # define INCR(x) ((x)++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) # define INCR(x) do {} while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) /* debug files */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #ifdef CONFIG_DYNAMIC_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) struct dentry *debug_dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) /* bandwidth usage */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define EHCI_BANDWIDTH_SIZE 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define EHCI_BANDWIDTH_FRAMES (EHCI_BANDWIDTH_SIZE >> 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) u8 bandwidth[EHCI_BANDWIDTH_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) /* us allocated per uframe */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) u8 tt_budget[EHCI_BANDWIDTH_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) /* us budgeted per uframe */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) struct list_head tt_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) /* platform-specific data -- must come last */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) unsigned long priv[] __aligned(sizeof(s64));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) /* convert between an HCD pointer and the corresponding EHCI_HCD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) static inline struct ehci_hcd *hcd_to_ehci(struct usb_hcd *hcd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) return (struct ehci_hcd *) (hcd->hcd_priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) static inline struct usb_hcd *ehci_to_hcd(struct ehci_hcd *ehci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) return container_of((void *) ehci, struct usb_hcd, hcd_priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) /*-------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #include <linux/usb/ehci_def.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) /*-------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define QTD_NEXT(ehci, dma) cpu_to_hc32(ehci, (u32)dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) * EHCI Specification 0.95 Section 3.5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) * QTD: describe data transfer components (buffer, direction, ...)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) * See Fig 3-6 "Queue Element Transfer Descriptor Block Diagram".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) * These are associated only with "QH" (Queue Head) structures,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) * used with control, bulk, and interrupt transfers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) struct ehci_qtd {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) /* first part defined by EHCI spec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) __hc32 hw_next; /* see EHCI 3.5.1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) __hc32 hw_alt_next; /* see EHCI 3.5.2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) __hc32 hw_token; /* see EHCI 3.5.3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define QTD_TOGGLE (1 << 31) /* data toggle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define QTD_LENGTH(tok) (((tok)>>16) & 0x7fff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define QTD_IOC (1 << 15) /* interrupt on complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define QTD_CERR(tok) (((tok)>>10) & 0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define QTD_PID(tok) (((tok)>>8) & 0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define QTD_STS_ACTIVE (1 << 7) /* HC may execute this */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define QTD_STS_HALT (1 << 6) /* halted on error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define QTD_STS_DBE (1 << 5) /* data buffer error (in HC) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define QTD_STS_BABBLE (1 << 4) /* device was babbling (qtd halted) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define QTD_STS_XACT (1 << 3) /* device gave illegal response */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define QTD_STS_MMF (1 << 2) /* incomplete split transaction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define QTD_STS_STS (1 << 1) /* split transaction state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define QTD_STS_PING (1 << 0) /* issue PING? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define ACTIVE_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_ACTIVE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define HALT_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_HALT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define STATUS_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_STS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) __hc32 hw_buf[5]; /* see EHCI 3.5.4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) __hc32 hw_buf_hi[5]; /* Appendix B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) /* the rest is HCD-private */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) dma_addr_t qtd_dma; /* qtd address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) struct list_head qtd_list; /* sw qtd list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) struct urb *urb; /* qtd's urb */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) size_t length; /* length of buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) } __aligned(32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) /* mask NakCnt+T in qh->hw_alt_next */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define QTD_MASK(ehci) cpu_to_hc32(ehci, ~0x1f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define IS_SHORT_READ(token) (QTD_LENGTH(token) != 0 && QTD_PID(token) == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) /*-------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) /* type tag from {qh,itd,sitd,fstn}->hw_next */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define Q_NEXT_TYPE(ehci, dma) ((dma) & cpu_to_hc32(ehci, 3 << 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) * Now the following defines are not converted using the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) * cpu_to_le32() macro anymore, since we have to support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) * "dynamic" switching between be and le support, so that the driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) * can be used on one system with SoC EHCI controller using big-endian
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) * descriptors as well as a normal little-endian PCI EHCI controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) /* values for that type tag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define Q_TYPE_ITD (0 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define Q_TYPE_QH (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define Q_TYPE_SITD (2 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define Q_TYPE_FSTN (3 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) /* next async queue entry, or pointer to interrupt/periodic QH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define QH_NEXT(ehci, dma) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) (cpu_to_hc32(ehci, (((u32) dma) & ~0x01f) | Q_TYPE_QH))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) /* for periodic/async schedules and qtd lists, mark end of list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define EHCI_LIST_END(ehci) cpu_to_hc32(ehci, 1) /* "null pointer" to hw */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) * Entries in periodic shadow table are pointers to one of four kinds
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) * of data structure. That's dictated by the hardware; a type tag is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) * encoded in the low bits of the hardware's periodic schedule. Use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) * Q_NEXT_TYPE to get the tag.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) * For entries in the async schedule, the type tag always says "qh".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) union ehci_shadow {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) struct ehci_qh *qh; /* Q_TYPE_QH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) struct ehci_itd *itd; /* Q_TYPE_ITD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) struct ehci_sitd *sitd; /* Q_TYPE_SITD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) struct ehci_fstn *fstn; /* Q_TYPE_FSTN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) __hc32 *hw_next; /* (all types) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) void *ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) /*-------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) * EHCI Specification 0.95 Section 3.6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) * QH: describes control/bulk/interrupt endpoints
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) * See Fig 3-7 "Queue Head Structure Layout".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) * These appear in both the async and (for interrupt) periodic schedules.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) /* first part defined by EHCI spec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) struct ehci_qh_hw {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) __hc32 hw_next; /* see EHCI 3.6.1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) __hc32 hw_info1; /* see EHCI 3.6.2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define QH_CONTROL_EP (1 << 27) /* FS/LS control endpoint */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define QH_HEAD (1 << 15) /* Head of async reclamation list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define QH_TOGGLE_CTL (1 << 14) /* Data toggle control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define QH_HIGH_SPEED (2 << 12) /* Endpoint speed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define QH_LOW_SPEED (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define QH_FULL_SPEED (0 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define QH_INACTIVATE (1 << 7) /* Inactivate on next transaction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) __hc32 hw_info2; /* see EHCI 3.6.2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #define QH_SMASK 0x000000ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #define QH_CMASK 0x0000ff00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define QH_HUBADDR 0x007f0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define QH_HUBPORT 0x3f800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define QH_MULT 0xc0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) __hc32 hw_current; /* qtd list - see EHCI 3.6.4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) /* qtd overlay (hardware parts of a struct ehci_qtd) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) __hc32 hw_qtd_next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) __hc32 hw_alt_next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) __hc32 hw_token;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) __hc32 hw_buf[5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) __hc32 hw_buf_hi[5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) } __aligned(32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) struct ehci_qh {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) struct ehci_qh_hw *hw; /* Must come first */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) /* the rest is HCD-private */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) dma_addr_t qh_dma; /* address of qh */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) union ehci_shadow qh_next; /* ptr to qh; or periodic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) struct list_head qtd_list; /* sw qtd list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) struct list_head intr_node; /* list of intr QHs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) struct ehci_qtd *dummy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) struct list_head unlink_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) struct ehci_per_sched ps; /* scheduling info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) unsigned unlink_cycle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) u8 qh_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) #define QH_STATE_LINKED 1 /* HC sees this */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) #define QH_STATE_UNLINK 2 /* HC may still see this */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) #define QH_STATE_IDLE 3 /* HC doesn't see this */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) #define QH_STATE_UNLINK_WAIT 4 /* LINKED and on unlink q */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) #define QH_STATE_COMPLETING 5 /* don't touch token.HALT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) u8 xacterrs; /* XactErr retry counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) #define QH_XACTERR_MAX 32 /* XactErr retry limit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) u8 unlink_reason;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) #define QH_UNLINK_HALTED 0x01 /* Halt flag is set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) #define QH_UNLINK_SHORT_READ 0x02 /* Recover from a short read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) #define QH_UNLINK_DUMMY_OVERLAY 0x04 /* QH overlayed the dummy TD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) #define QH_UNLINK_SHUTDOWN 0x08 /* The HC isn't running */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) #define QH_UNLINK_QUEUE_EMPTY 0x10 /* Reached end of the queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) #define QH_UNLINK_REQUESTED 0x20 /* Disable, reset, or dequeue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) u8 gap_uf; /* uframes split/csplit gap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) unsigned is_out:1; /* bulk or intr OUT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) unsigned clearing_tt:1; /* Clear-TT-Buf in progress */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) unsigned dequeue_during_giveback:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) unsigned should_be_inactive:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) /*-------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) /* description of one iso transaction (up to 3 KB data if highspeed) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) struct ehci_iso_packet {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) /* These will be copied to iTD when scheduling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) u64 bufp; /* itd->hw_bufp{,_hi}[pg] |= */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) __hc32 transaction; /* itd->hw_transaction[i] |= */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) u8 cross; /* buf crosses pages */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) /* for full speed OUT splits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) u32 buf1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) /* temporary schedule data for packets from iso urbs (both speeds)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) * each packet is one logical usb transaction to the device (not TT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) * beginning at stream->next_uframe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) struct ehci_iso_sched {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) struct list_head td_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) unsigned span;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) unsigned first_packet;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) struct ehci_iso_packet packet[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) * ehci_iso_stream - groups all (s)itds for this endpoint.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) * acts like a qh would, if EHCI had them for ISO.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) struct ehci_iso_stream {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) /* first field matches ehci_hq, but is NULL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) struct ehci_qh_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) u8 bEndpointAddress;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) u8 highspeed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) struct list_head td_list; /* queued itds/sitds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) struct list_head free_list; /* list of unused itds/sitds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) /* output of (re)scheduling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) struct ehci_per_sched ps; /* scheduling info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) unsigned next_uframe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) __hc32 splits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) /* the rest is derived from the endpoint descriptor,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) * including the extra info for hw_bufp[0..2]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) u16 uperiod; /* period in uframes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) u16 maxp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) unsigned bandwidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) /* This is used to initialize iTD's hw_bufp fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) __hc32 buf0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) __hc32 buf1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) __hc32 buf2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) /* this is used to initialize sITD's tt info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) __hc32 address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) /*-------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) * EHCI Specification 0.95 Section 3.3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) * Fig 3-4 "Isochronous Transaction Descriptor (iTD)"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) * Schedule records for high speed iso xfers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) struct ehci_itd {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) /* first part defined by EHCI spec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) __hc32 hw_next; /* see EHCI 3.3.1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) __hc32 hw_transaction[8]; /* see EHCI 3.3.2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) #define EHCI_ISOC_ACTIVE (1<<31) /* activate transfer this slot */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) #define EHCI_ISOC_BUF_ERR (1<<30) /* Data buffer error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) #define EHCI_ISOC_BABBLE (1<<29) /* babble detected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) #define EHCI_ISOC_XACTERR (1<<28) /* XactErr - transaction error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) #define EHCI_ITD_LENGTH(tok) (((tok)>>16) & 0x0fff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) #define EHCI_ITD_IOC (1 << 15) /* interrupt on complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) #define ITD_ACTIVE(ehci) cpu_to_hc32(ehci, EHCI_ISOC_ACTIVE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) __hc32 hw_bufp[7]; /* see EHCI 3.3.3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) __hc32 hw_bufp_hi[7]; /* Appendix B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) /* the rest is HCD-private */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) dma_addr_t itd_dma; /* for this itd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) union ehci_shadow itd_next; /* ptr to periodic q entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) struct urb *urb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) struct ehci_iso_stream *stream; /* endpoint's queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) struct list_head itd_list; /* list of stream's itds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) /* any/all hw_transactions here may be used by that urb */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) unsigned frame; /* where scheduled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) unsigned pg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) unsigned index[8]; /* in urb->iso_frame_desc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) } __aligned(32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) /*-------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) * EHCI Specification 0.95 Section 3.4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) * siTD, aka split-transaction isochronous Transfer Descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) * ... describe full speed iso xfers through TT in hubs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) * see Figure 3-5 "Split-transaction Isochronous Transaction Descriptor (siTD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) struct ehci_sitd {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) /* first part defined by EHCI spec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) __hc32 hw_next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) /* uses bit field macros above - see EHCI 0.95 Table 3-8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) __hc32 hw_fullspeed_ep; /* EHCI table 3-9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) __hc32 hw_uframe; /* EHCI table 3-10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) __hc32 hw_results; /* EHCI table 3-11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) #define SITD_IOC (1 << 31) /* interrupt on completion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) #define SITD_PAGE (1 << 30) /* buffer 0/1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) #define SITD_LENGTH(x) (((x) >> 16) & 0x3ff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) #define SITD_STS_ACTIVE (1 << 7) /* HC may execute this */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) #define SITD_STS_ERR (1 << 6) /* error from TT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) #define SITD_STS_DBE (1 << 5) /* data buffer error (in HC) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) #define SITD_STS_BABBLE (1 << 4) /* device was babbling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) #define SITD_STS_XACT (1 << 3) /* illegal IN response */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) #define SITD_STS_MMF (1 << 2) /* incomplete split transaction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) #define SITD_STS_STS (1 << 1) /* split transaction state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) #define SITD_ACTIVE(ehci) cpu_to_hc32(ehci, SITD_STS_ACTIVE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) __hc32 hw_buf[2]; /* EHCI table 3-12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) __hc32 hw_backpointer; /* EHCI table 3-13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) __hc32 hw_buf_hi[2]; /* Appendix B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) /* the rest is HCD-private */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) dma_addr_t sitd_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) union ehci_shadow sitd_next; /* ptr to periodic q entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) struct urb *urb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) struct ehci_iso_stream *stream; /* endpoint's queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) struct list_head sitd_list; /* list of stream's sitds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) unsigned frame;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) unsigned index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) } __aligned(32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) /*-------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) * EHCI Specification 0.96 Section 3.7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) * Periodic Frame Span Traversal Node (FSTN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) * Manages split interrupt transactions (using TT) that span frame boundaries
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) * into uframes 0/1; see 4.12.2.2. In those uframes, a "save place" FSTN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) * makes the HC jump (back) to a QH to scan for fs/ls QH completions until
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) * it hits a "restore" FSTN; then it returns to finish other uframe 0/1 work.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) struct ehci_fstn {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) __hc32 hw_next; /* any periodic q entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) __hc32 hw_prev; /* qh or EHCI_LIST_END */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) /* the rest is HCD-private */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) dma_addr_t fstn_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) union ehci_shadow fstn_next; /* ptr to periodic q entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) } __aligned(32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) /*-------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) * USB-2.0 Specification Sections 11.14 and 11.18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) * Scheduling and budgeting split transactions using TTs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) * A hub can have a single TT for all its ports, or multiple TTs (one for each
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) * port). The bandwidth and budgeting information for the full/low-speed bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) * below each TT is self-contained and independent of the other TTs or the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) * high-speed bus.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) * "Bandwidth" refers to the number of microseconds on the FS/LS bus allocated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) * to an interrupt or isochronous endpoint for each frame. "Budget" refers to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) * the best-case estimate of the number of full-speed bytes allocated to an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) * endpoint for each microframe within an allocated frame.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) * Removal of an endpoint invalidates a TT's budget. Instead of trying to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) * keep an up-to-date record, we recompute the budget when it is needed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) struct ehci_tt {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) u16 bandwidth[EHCI_BANDWIDTH_FRAMES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) struct list_head tt_list; /* List of all ehci_tt's */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) struct list_head ps_list; /* Items using this TT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) struct usb_tt *usb_tt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) int tt_port; /* TT port number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) /*-------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) /* Prepare the PORTSC wakeup flags during controller suspend/resume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) #define ehci_prepare_ports_for_controller_suspend(ehci, do_wakeup) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) ehci_adjust_port_wakeup_flags(ehci, true, do_wakeup)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) #define ehci_prepare_ports_for_controller_resume(ehci) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) ehci_adjust_port_wakeup_flags(ehci, false, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) /*-------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) #ifdef CONFIG_USB_EHCI_ROOT_HUB_TT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) * Some EHCI controllers have a Transaction Translator built into the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) * root hub. This is a non-standard feature. Each controller will need
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) * to add code to the following inline functions, and call them as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) * needed (mostly in root hub code).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) #define ehci_is_TDI(e) (ehci_to_hcd(e)->has_tt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) /* Returns the speed of a device attached to a port on the root hub. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) static inline unsigned int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) ehci_port_speed(struct ehci_hcd *ehci, unsigned int portsc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) if (ehci_is_TDI(ehci)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) switch ((portsc >> (ehci->has_hostpc ? 25 : 26)) & 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) return USB_PORT_STAT_LOW_SPEED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) return USB_PORT_STAT_HIGH_SPEED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) return USB_PORT_STAT_HIGH_SPEED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) #define ehci_is_TDI(e) (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) #define ehci_port_speed(ehci, portsc) USB_PORT_STAT_HIGH_SPEED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) /*-------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) #ifdef CONFIG_PPC_83xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) /* Some Freescale processors have an erratum in which the TT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) * port number in the queue head was 0..N-1 instead of 1..N.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) #define ehci_has_fsl_portno_bug(e) ((e)->has_fsl_port_bug)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) #define ehci_has_fsl_portno_bug(e) (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) #define PORTSC_FSL_PFSC 24 /* Port Force Full-Speed Connect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) #if defined(CONFIG_PPC_85xx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) /* Some Freescale processors have an erratum (USB A-005275) in which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) * incoming packets get corrupted in HS mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) #define ehci_has_fsl_hs_errata(e) ((e)->has_fsl_hs_errata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) #define ehci_has_fsl_hs_errata(e) (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) * Some Freescale/NXP processors have an erratum (USB A-005697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) * in which we need to wait for 10ms for bus to enter suspend mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) * after setting SUSP bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) #define ehci_has_fsl_susp_errata(e) ((e)->has_fsl_susp_errata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) * While most USB host controllers implement their registers in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) * little-endian format, a minority (celleb companion chip) implement
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) * them in big endian format.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) * This attempts to support either format at compile time without a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) * runtime penalty, or both formats with the additional overhead
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) * of checking a flag bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) * ehci_big_endian_capbase is a special quirk for controllers that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) * implement the HC capability registers as separate registers and not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) * as fields of a 32-bit register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) #define ehci_big_endian_mmio(e) ((e)->big_endian_mmio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) #define ehci_big_endian_capbase(e) ((e)->big_endian_capbase)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) #define ehci_big_endian_mmio(e) 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) #define ehci_big_endian_capbase(e) 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) * Big-endian read/write functions are arch-specific.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) * Other arches can be added if/when they're needed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) #if defined(CONFIG_ARM) && defined(CONFIG_ARCH_IXP4XX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) #define readl_be(addr) __raw_readl((__force unsigned *)addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) #define writel_be(val, addr) __raw_writel(val, (__force unsigned *)addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) static inline unsigned int ehci_readl(const struct ehci_hcd *ehci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) __u32 __iomem *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) return ehci_big_endian_mmio(ehci) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) readl_be(regs) :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) readl(regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) return readl(regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) #ifdef CONFIG_SOC_IMX28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) static inline void imx28_ehci_writel(const unsigned int val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) volatile __u32 __iomem *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) __asm__ ("swp %0, %0, [%1]" : : "r"(val), "r"(addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) static inline void imx28_ehci_writel(const unsigned int val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) volatile __u32 __iomem *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) static inline void ehci_writel(const struct ehci_hcd *ehci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) const unsigned int val, __u32 __iomem *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) ehci_big_endian_mmio(ehci) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) writel_be(val, regs) :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) writel(val, regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) if (ehci->imx28_write_fix)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) imx28_ehci_writel(val, regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) writel(val, regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) * On certain ppc-44x SoC there is a HW issue, that could only worked around with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) * explicit suspend/operate of OHCI. This function hereby makes sense only on that arch.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) * Other common bits are dependent on has_amcc_usb23 quirk flag.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) #ifdef CONFIG_44x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) static inline void set_ohci_hcfs(struct ehci_hcd *ehci, int operational)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) u32 hc_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) hc_control = (readl_be(ehci->ohci_hcctrl_reg) & ~OHCI_CTRL_HCFS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) if (operational)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) hc_control |= OHCI_USB_OPER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) hc_control |= OHCI_USB_SUSPEND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) writel_be(hc_control, ehci->ohci_hcctrl_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) (void) readl_be(ehci->ohci_hcctrl_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) static inline void set_ohci_hcfs(struct ehci_hcd *ehci, int operational)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) /*-------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) * The AMCC 440EPx not only implements its EHCI registers in big-endian
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) * format, but also its DMA data structures (descriptors).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) * EHCI controllers accessed through PCI work normally (little-endian
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) * everywhere), so we won't bother supporting a BE-only mode for now.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) #define ehci_big_endian_desc(e) ((e)->big_endian_desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) /* cpu to ehci */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) static inline __hc32 cpu_to_hc32(const struct ehci_hcd *ehci, const u32 x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) return ehci_big_endian_desc(ehci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) ? (__force __hc32)cpu_to_be32(x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) : (__force __hc32)cpu_to_le32(x);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) /* ehci to cpu */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) static inline u32 hc32_to_cpu(const struct ehci_hcd *ehci, const __hc32 x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) return ehci_big_endian_desc(ehci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) ? be32_to_cpu((__force __be32)x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) : le32_to_cpu((__force __le32)x);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) static inline u32 hc32_to_cpup(const struct ehci_hcd *ehci, const __hc32 *x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) return ehci_big_endian_desc(ehci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) ? be32_to_cpup((__force __be32 *)x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) : le32_to_cpup((__force __le32 *)x);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) /* cpu to ehci */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) static inline __hc32 cpu_to_hc32(const struct ehci_hcd *ehci, const u32 x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) return cpu_to_le32(x);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) /* ehci to cpu */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) static inline u32 hc32_to_cpu(const struct ehci_hcd *ehci, const __hc32 x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) return le32_to_cpu(x);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) static inline u32 hc32_to_cpup(const struct ehci_hcd *ehci, const __hc32 *x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) return le32_to_cpup(x);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) /*-------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) #define ehci_dbg(ehci, fmt, args...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) dev_dbg(ehci_to_hcd(ehci)->self.controller, fmt, ## args)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) #define ehci_err(ehci, fmt, args...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) dev_err(ehci_to_hcd(ehci)->self.controller, fmt, ## args)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) #define ehci_info(ehci, fmt, args...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) dev_info(ehci_to_hcd(ehci)->self.controller, fmt, ## args)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) #define ehci_warn(ehci, fmt, args...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) dev_warn(ehci_to_hcd(ehci)->self.controller, fmt, ## args)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) /*-------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) /* Declarations of things exported for use by ehci platform drivers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) struct ehci_driver_overrides {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) size_t extra_priv_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) int (*reset)(struct usb_hcd *hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) int (*port_power)(struct usb_hcd *hcd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) int portnum, bool enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) extern void ehci_init_driver(struct hc_driver *drv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) const struct ehci_driver_overrides *over);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) extern int ehci_setup(struct usb_hcd *hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) extern int ehci_handshake(struct ehci_hcd *ehci, void __iomem *ptr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) u32 mask, u32 done, int usec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) extern int ehci_reset(struct ehci_hcd *ehci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) extern int ehci_suspend(struct usb_hcd *hcd, bool do_wakeup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) extern int ehci_resume(struct usb_hcd *hcd, bool force_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) extern void ehci_adjust_port_wakeup_flags(struct ehci_hcd *ehci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) bool suspending, bool do_wakeup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) extern int ehci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) u16 wIndex, char *buf, u16 wLength);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) #endif /* __LINUX_EHCI_HCD_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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