^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * EHCI-compliant USB host controller driver for NVIDIA Tegra SoCs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2010 Google, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2009 - 2013 NVIDIA Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/of_gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/usb/ehci_def.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/usb/tegra_usb_phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/usb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/usb/hcd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/usb/otg.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include "ehci.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define PORT_WAKE_BITS (PORT_WKOC_E|PORT_WKDISC_E|PORT_WKCONN_E)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define TEGRA_USB_DMA_ALIGN 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define DRIVER_DESC "Tegra EHCI driver"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define DRV_NAME "tegra-ehci"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) static struct hc_driver __read_mostly tegra_ehci_hc_driver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) struct tegra_ehci_soc_config {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) bool has_hostpc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) struct tegra_ehci_hcd {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) struct reset_control *rst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) int port_resuming;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) bool needs_double_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) static int tegra_reset_usb_controller(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) struct device_node *phy_np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) struct usb_hcd *hcd = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) struct tegra_ehci_hcd *tegra =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) (struct tegra_ehci_hcd *)hcd_to_ehci(hcd)->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) struct reset_control *rst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) phy_np = of_parse_phandle(pdev->dev.of_node, "nvidia,phy", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) if (!phy_np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * The 1st USB controller contains some UTMI pad registers that are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * global for all the controllers on the chip. Those registers are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * also cleared when reset is asserted to the 1st controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) rst = of_reset_control_get_shared(phy_np, "utmi-pads");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) if (IS_ERR(rst)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) dev_warn(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) "can't get utmi-pads reset from the PHY\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) dev_warn(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) "continuing, but please update your DT\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * PHY driver performs UTMI-pads reset in a case of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * non-legacy DT.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) reset_control_put(rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) of_node_put(phy_np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /* reset control is shared, hence initialize it first */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) err = reset_control_deassert(tegra->rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) err = reset_control_assert(tegra->rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) err = reset_control_deassert(tegra->rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static int tegra_ehci_internal_port_reset(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) struct ehci_hcd *ehci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) u32 __iomem *portsc_reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) u32 temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) int retval = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) int i, tries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) u32 saved_usbintr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) spin_lock_irqsave(&ehci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) saved_usbintr = ehci_readl(ehci, &ehci->regs->intr_enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /* disable USB interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) ehci_writel(ehci, 0, &ehci->regs->intr_enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) spin_unlock_irqrestore(&ehci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) * Here we have to do Port Reset at most twice for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) * Port Enable bit to be set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) for (i = 0; i < 2; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) temp = ehci_readl(ehci, portsc_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) temp |= PORT_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) ehci_writel(ehci, temp, portsc_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) mdelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) temp &= ~PORT_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) ehci_writel(ehci, temp, portsc_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) mdelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) tries = 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) mdelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * Up to this point, Port Enable bit is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) * expected to be set after 2 ms waiting.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) * USB1 usually takes extra 45 ms, for safety,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) * we take 100 ms as timeout.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) temp = ehci_readl(ehci, portsc_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) } while (!(temp & PORT_PE) && tries--);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) if (temp & PORT_PE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) if (i == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) retval = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) * Clear Connect Status Change bit if it's set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) * We can't clear PORT_PEC. It will also cause PORT_PE to be cleared.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) if (temp & PORT_CSC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) ehci_writel(ehci, PORT_CSC, portsc_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) * Write to clear any interrupt status bits that might be set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) * during port reset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) temp = ehci_readl(ehci, &ehci->regs->status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) ehci_writel(ehci, temp, &ehci->regs->status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) /* restore original interrupt enable bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) ehci_writel(ehci, saved_usbintr, &ehci->regs->intr_enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static int tegra_ehci_hub_control(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) struct usb_hcd *hcd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) u16 typeReq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) u16 wValue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) u16 wIndex,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) char *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) u16 wLength
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) struct ehci_hcd *ehci = hcd_to_ehci(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) struct tegra_ehci_hcd *tegra = (struct tegra_ehci_hcd *)ehci->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) u32 __iomem *status_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) u32 temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) int retval = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) status_reg = &ehci->regs->port_status[(wIndex & 0xff) - 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) spin_lock_irqsave(&ehci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) if (typeReq == GetPortStatus) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) temp = ehci_readl(ehci, status_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) if (tegra->port_resuming && !(temp & PORT_SUSPEND)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) /* Resume completed, re-enable disconnect detection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) tegra->port_resuming = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) tegra_usb_phy_postresume(hcd->usb_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) else if (typeReq == SetPortFeature && wValue == USB_PORT_FEAT_SUSPEND) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) temp = ehci_readl(ehci, status_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) if ((temp & PORT_PE) == 0 || (temp & PORT_RESET) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) retval = -EPIPE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) temp &= ~(PORT_RWC_BITS | PORT_WKCONN_E);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) temp |= PORT_WKDISC_E | PORT_WKOC_E;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) ehci_writel(ehci, temp | PORT_SUSPEND, status_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) * If a transaction is in progress, there may be a delay in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) * suspending the port. Poll until the port is suspended.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) if (ehci_handshake(ehci, status_reg, PORT_SUSPEND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) PORT_SUSPEND, 5000))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) pr_err("%s: timeout waiting for SUSPEND\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) set_bit((wIndex & 0xff) - 1, &ehci->suspended_ports);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) /* For USB1 port we need to issue Port Reset twice internally */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) if (tegra->needs_double_reset &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) (typeReq == SetPortFeature && wValue == USB_PORT_FEAT_RESET)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) spin_unlock_irqrestore(&ehci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) return tegra_ehci_internal_port_reset(ehci, status_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) * Tegra host controller will time the resume operation to clear the bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) * when the port control state switches to HS or FS Idle. This behavior
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) * is different from EHCI where the host controller driver is required
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) * to set this bit to a zero after the resume duration is timed in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) * driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) else if (typeReq == ClearPortFeature &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) wValue == USB_PORT_FEAT_SUSPEND) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) temp = ehci_readl(ehci, status_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) if ((temp & PORT_RESET) || !(temp & PORT_PE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) retval = -EPIPE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) if (!(temp & PORT_SUSPEND))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) /* Disable disconnect detection during port resume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) tegra_usb_phy_preresume(hcd->usb_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) ehci->reset_done[wIndex-1] = jiffies + msecs_to_jiffies(25);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) temp &= ~(PORT_RWC_BITS | PORT_WAKE_BITS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) /* start resume signalling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) ehci_writel(ehci, temp | PORT_RESUME, status_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) set_bit(wIndex-1, &ehci->resuming_ports);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) spin_unlock_irqrestore(&ehci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) msleep(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) spin_lock_irqsave(&ehci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) /* Poll until the controller clears RESUME and SUSPEND */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) if (ehci_handshake(ehci, status_reg, PORT_RESUME, 0, 2000))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) pr_err("%s: timeout waiting for RESUME\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) if (ehci_handshake(ehci, status_reg, PORT_SUSPEND, 0, 2000))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) pr_err("%s: timeout waiting for SUSPEND\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) ehci->reset_done[wIndex-1] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) clear_bit(wIndex-1, &ehci->resuming_ports);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) tegra->port_resuming = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) spin_unlock_irqrestore(&ehci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) /* Handle the hub control events here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) return ehci_hub_control(hcd, typeReq, wValue, wIndex, buf, wLength);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) spin_unlock_irqrestore(&ehci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) struct dma_aligned_buffer {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) void *kmalloc_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) void *old_xfer_buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) u8 data[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) static void free_dma_aligned_buffer(struct urb *urb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) struct dma_aligned_buffer *temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) size_t length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) if (!(urb->transfer_flags & URB_ALIGNED_TEMP_BUFFER))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) temp = container_of(urb->transfer_buffer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) struct dma_aligned_buffer, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) if (usb_urb_dir_in(urb)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) if (usb_pipeisoc(urb->pipe))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) length = urb->transfer_buffer_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) length = urb->actual_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) memcpy(temp->old_xfer_buffer, temp->data, length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) urb->transfer_buffer = temp->old_xfer_buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) kfree(temp->kmalloc_ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) urb->transfer_flags &= ~URB_ALIGNED_TEMP_BUFFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) static int alloc_dma_aligned_buffer(struct urb *urb, gfp_t mem_flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) struct dma_aligned_buffer *temp, *kmalloc_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) size_t kmalloc_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) if (urb->num_sgs || urb->sg ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) urb->transfer_buffer_length == 0 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) !((uintptr_t)urb->transfer_buffer & (TEGRA_USB_DMA_ALIGN - 1)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) /* Allocate a buffer with enough padding for alignment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) kmalloc_size = urb->transfer_buffer_length +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) sizeof(struct dma_aligned_buffer) + TEGRA_USB_DMA_ALIGN - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) kmalloc_ptr = kmalloc(kmalloc_size, mem_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) if (!kmalloc_ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) /* Position our struct dma_aligned_buffer such that data is aligned */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) temp = PTR_ALIGN(kmalloc_ptr + 1, TEGRA_USB_DMA_ALIGN) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) temp->kmalloc_ptr = kmalloc_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) temp->old_xfer_buffer = urb->transfer_buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) if (usb_urb_dir_out(urb))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) memcpy(temp->data, urb->transfer_buffer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) urb->transfer_buffer_length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) urb->transfer_buffer = temp->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) urb->transfer_flags |= URB_ALIGNED_TEMP_BUFFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) static int tegra_ehci_map_urb_for_dma(struct usb_hcd *hcd, struct urb *urb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) gfp_t mem_flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) ret = alloc_dma_aligned_buffer(urb, mem_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) ret = usb_hcd_map_urb_for_dma(hcd, urb, mem_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) free_dma_aligned_buffer(urb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) static void tegra_ehci_unmap_urb_for_dma(struct usb_hcd *hcd, struct urb *urb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) usb_hcd_unmap_urb_for_dma(hcd, urb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) free_dma_aligned_buffer(urb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) static const struct tegra_ehci_soc_config tegra30_soc_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) .has_hostpc = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) static const struct tegra_ehci_soc_config tegra20_soc_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) .has_hostpc = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) static const struct of_device_id tegra_ehci_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) { .compatible = "nvidia,tegra30-ehci", .data = &tegra30_soc_config },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) { .compatible = "nvidia,tegra20-ehci", .data = &tegra20_soc_config },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) static int tegra_ehci_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) const struct tegra_ehci_soc_config *soc_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) struct usb_hcd *hcd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) struct ehci_hcd *ehci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) struct tegra_ehci_hcd *tegra;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) struct usb_phy *u_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) match = of_match_device(tegra_ehci_of_match, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) if (!match) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) dev_err(&pdev->dev, "Error: No device match found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) soc_config = match->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) /* Right now device-tree probed devices don't get dma_mask set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) * Since shared usb code relies on it, set it here for now.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) * Once we have dma capability bindings this can go away.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) err = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) hcd = usb_create_hcd(&tegra_ehci_hc_driver, &pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) dev_name(&pdev->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) if (!hcd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) dev_err(&pdev->dev, "Unable to create HCD\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) platform_set_drvdata(pdev, hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) ehci = hcd_to_ehci(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) tegra = (struct tegra_ehci_hcd *)ehci->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) hcd->has_tt = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) tegra->clk = devm_clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) if (IS_ERR(tegra->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) dev_err(&pdev->dev, "Can't get ehci clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) err = PTR_ERR(tegra->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) goto cleanup_hcd_create;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) tegra->rst = devm_reset_control_get_shared(&pdev->dev, "usb");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) if (IS_ERR(tegra->rst)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) dev_err(&pdev->dev, "Can't get ehci reset\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) err = PTR_ERR(tegra->rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) goto cleanup_hcd_create;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) err = clk_prepare_enable(tegra->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) goto cleanup_hcd_create;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) err = tegra_reset_usb_controller(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) dev_err(&pdev->dev, "Failed to reset controller\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) goto cleanup_clk_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) u_phy = devm_usb_get_phy_by_phandle(&pdev->dev, "nvidia,phy", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) if (IS_ERR(u_phy)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) err = -EPROBE_DEFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) goto cleanup_clk_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) hcd->usb_phy = u_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) hcd->skip_phy_initialization = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) tegra->needs_double_reset = of_property_read_bool(pdev->dev.of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) "nvidia,needs-double-reset");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) hcd->regs = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) if (IS_ERR(hcd->regs)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) err = PTR_ERR(hcd->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) goto cleanup_clk_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) hcd->rsrc_start = res->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) hcd->rsrc_len = resource_size(res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) ehci->caps = hcd->regs + 0x100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) ehci->has_hostpc = soc_config->has_hostpc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) err = usb_phy_init(hcd->usb_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) dev_err(&pdev->dev, "Failed to initialize phy\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) goto cleanup_clk_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) u_phy->otg = devm_kzalloc(&pdev->dev, sizeof(struct usb_otg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) if (!u_phy->otg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) goto cleanup_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) u_phy->otg->host = hcd_to_bus(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) if (irq < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) err = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) goto cleanup_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) otg_set_host(u_phy->otg, &hcd->self);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) err = usb_add_hcd(hcd, irq, IRQF_SHARED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) dev_err(&pdev->dev, "Failed to add USB HCD\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) goto cleanup_otg_set_host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) device_wakeup_enable(hcd->self.controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) cleanup_otg_set_host:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) otg_set_host(u_phy->otg, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) cleanup_phy:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) usb_phy_shutdown(hcd->usb_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) cleanup_clk_en:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) clk_disable_unprepare(tegra->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) cleanup_hcd_create:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) usb_put_hcd(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) static int tegra_ehci_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) struct usb_hcd *hcd = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) struct tegra_ehci_hcd *tegra =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) (struct tegra_ehci_hcd *)hcd_to_ehci(hcd)->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) usb_remove_hcd(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) otg_set_host(hcd->usb_phy->otg, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) usb_phy_shutdown(hcd->usb_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) clk_disable_unprepare(tegra->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) usb_put_hcd(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) static void tegra_ehci_hcd_shutdown(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) struct usb_hcd *hcd = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) if (hcd->driver->shutdown)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) hcd->driver->shutdown(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) static struct platform_driver tegra_ehci_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) .probe = tegra_ehci_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) .remove = tegra_ehci_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) .shutdown = tegra_ehci_hcd_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) .name = DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) .of_match_table = tegra_ehci_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) static int tegra_ehci_reset(struct usb_hcd *hcd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) struct ehci_hcd *ehci = hcd_to_ehci(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) int retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) int txfifothresh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) retval = ehci_setup(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) if (retval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) * We should really pull this value out of tegra_ehci_soc_config, but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) * to avoid needing access to it, make use of the fact that Tegra20 is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) * the only one so far that needs a value of 10, and Tegra20 is the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) * only one which doesn't set has_hostpc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) txfifothresh = ehci->has_hostpc ? 0x10 : 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) ehci_writel(ehci, txfifothresh << 16, &ehci->regs->txfill_tuning);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) static const struct ehci_driver_overrides tegra_overrides __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) .extra_priv_size = sizeof(struct tegra_ehci_hcd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) .reset = tegra_ehci_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) static int __init ehci_tegra_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) if (usb_disabled())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) pr_info(DRV_NAME ": " DRIVER_DESC "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) ehci_init_driver(&tegra_ehci_hc_driver, &tegra_overrides);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) * The Tegra HW has some unusual quirks, which require Tegra-specific
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) * workarounds. We override certain hc_driver functions here to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) * achieve that. We explicitly do not enhance ehci_driver_overrides to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) * allow this more easily, since this is an unusual case, and we don't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) * want to encourage others to override these functions by making it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) * too easy.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) tegra_ehci_hc_driver.map_urb_for_dma = tegra_ehci_map_urb_for_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) tegra_ehci_hc_driver.unmap_urb_for_dma = tegra_ehci_unmap_urb_for_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) tegra_ehci_hc_driver.hub_control = tegra_ehci_hub_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) return platform_driver_register(&tegra_ehci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) module_init(ehci_tegra_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) static void __exit ehci_tegra_cleanup(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) platform_driver_unregister(&tegra_ehci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) module_exit(ehci_tegra_cleanup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) MODULE_DESCRIPTION(DRIVER_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) MODULE_ALIAS("platform:" DRV_NAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) MODULE_DEVICE_TABLE(of, tegra_ehci_of_match);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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