^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * EHCI HCD (Host Controller Driver) PCI Bus Glue.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2000-2004 by David Brownell
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/usb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/usb/hcd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include "ehci.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "pci-quirks.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define DRIVER_DESC "EHCI PCI platform driver"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) static const char hcd_name[] = "ehci-pci";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /* defined here to avoid adding to pci_ids.h for single instance use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define PCI_DEVICE_ID_INTEL_CE4100_USB 0x2e70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /*-------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define PCI_DEVICE_ID_INTEL_QUARK_X1000_SOC 0x0939
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) static inline bool is_intel_quark_x1000(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) return pdev->vendor == PCI_VENDOR_ID_INTEL &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) pdev->device == PCI_DEVICE_ID_INTEL_QUARK_X1000_SOC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * This is the list of PCI IDs for the devices that have EHCI USB class and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * specific drivers for that. One of the example is a ChipIdea device installed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * on some Intel MID platforms.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) static const struct pci_device_id bypass_pci_id_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /* ChipIdea on Intel MID platform */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x0811), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x0829), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xe006), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) static inline bool is_bypassed_id(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) return !!pci_match_id(bypass_pci_id_table, pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * 0x84 is the offset of in/out threshold register,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * and it is the same offset as the register of 'hostpc'.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define intel_quark_x1000_insnreg01 hostpc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /* Maximum usable threshold value is 0x7f dwords for both IN and OUT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define INTEL_QUARK_X1000_EHCI_MAX_THRESHOLD 0x007f007f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /* called after powerup, by probe or system-pm "wakeup" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) static int ehci_pci_reinit(struct ehci_hcd *ehci, struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) int retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /* we expect static quirk code to handle the "extended capabilities"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * (currently just BIOS handoff) allowed starting with EHCI 0.96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) retval = pci_set_mwi(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) if (!retval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) ehci_dbg(ehci, "MWI active\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /* Reset the threshold limit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) if (is_intel_quark_x1000(pdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * For the Intel QUARK X1000, raise the I/O threshold to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * maximum usable value in order to improve performance.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) ehci_writel(ehci, INTEL_QUARK_X1000_EHCI_MAX_THRESHOLD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) ehci->regs->intel_quark_x1000_insnreg01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /* called during probe() after chip reset completes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) static int ehci_pci_setup(struct usb_hcd *hcd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct ehci_hcd *ehci = hcd_to_ehci(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) u32 temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) int retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) ehci->caps = hcd->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * ehci_init() causes memory for DMA transfers to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * allocated. Thus, any vendor-specific workarounds based on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * limiting the type of memory used for DMA transfers must
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * happen before ehci_setup() is called.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * Most other workarounds can be done either before or after
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * init and reset; they are located here too.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) switch (pdev->vendor) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) case PCI_VENDOR_ID_TOSHIBA_2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /* celleb's companion chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) if (pdev->device == 0x01b5) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) ehci->big_endian_mmio = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) ehci_warn(ehci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) "unsupported big endian Toshiba quirk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) case PCI_VENDOR_ID_NVIDIA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /* NVidia reports that certain chips don't handle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) * QH, ITD, or SITD addresses above 2GB. (But TD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * data buffer, and periodic schedule are normal.)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) switch (pdev->device) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) case 0x003c: /* MCP04 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) case 0x005b: /* CK804 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) case 0x00d8: /* CK8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) case 0x00e8: /* CK8S */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) if (dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(31)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) ehci_warn(ehci, "can't enable NVidia "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) "workaround for >2GB RAM\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) /* Some NForce2 chips have problems with selective suspend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * fixed in newer silicon.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) case 0x0068:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) if (pdev->revision < 0xa4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) ehci->no_selective_suspend = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) case PCI_VENDOR_ID_INTEL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) if (pdev->device == PCI_DEVICE_ID_INTEL_CE4100_USB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) hcd->has_tt = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) case PCI_VENDOR_ID_TDI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) if (pdev->device == PCI_DEVICE_ID_TDI_EHCI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) hcd->has_tt = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) case PCI_VENDOR_ID_AMD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) /* AMD PLL quirk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) if (usb_amd_quirk_pll_check())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) ehci->amd_pll_fix = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /* AMD8111 EHCI doesn't work, according to AMD errata */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) if (pdev->device == 0x7463) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) ehci_info(ehci, "ignoring AMD8111 (errata)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) retval = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) * EHCI controller on AMD SB700/SB800/Hudson-2/3 platforms may
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) * read/write memory space which does not belong to it when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * there is NULL pointer with T-bit set to 1 in the frame list
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) * table. To avoid the issue, the frame list link pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) * should always contain a valid pointer to a inactive qh.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) if (pdev->device == 0x7808) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) ehci->use_dummy_qh = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) ehci_info(ehci, "applying AMD SB700/SB800/Hudson-2/3 EHCI dummy qh workaround\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) case PCI_VENDOR_ID_VIA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) if (pdev->device == 0x3104 && (pdev->revision & 0xf0) == 0x60) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) u8 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) /* The VT6212 defaults to a 1 usec EHCI sleep time which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) * hogs the PCI bus *badly*. Setting bit 5 of 0x4B makes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) * that sleep time use the conventional 10 usec.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) pci_read_config_byte(pdev, 0x4b, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) if (tmp & 0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) pci_write_config_byte(pdev, 0x4b, tmp | 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) case PCI_VENDOR_ID_ATI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) /* AMD PLL quirk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) if (usb_amd_quirk_pll_check())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) ehci->amd_pll_fix = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) * EHCI controller on AMD SB700/SB800/Hudson-2/3 platforms may
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) * read/write memory space which does not belong to it when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) * there is NULL pointer with T-bit set to 1 in the frame list
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) * table. To avoid the issue, the frame list link pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) * should always contain a valid pointer to a inactive qh.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) if (pdev->device == 0x4396) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) ehci->use_dummy_qh = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) ehci_info(ehci, "applying AMD SB700/SB800/Hudson-2/3 EHCI dummy qh workaround\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) /* SB600 and old version of SB700 have a bug in EHCI controller,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) * which causes usb devices lose response in some cases.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) if ((pdev->device == 0x4386 || pdev->device == 0x4396) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) usb_amd_hang_symptom_quirk()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) u8 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) ehci_info(ehci, "applying AMD SB600/SB700 USB freeze workaround\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) pci_read_config_byte(pdev, 0x53, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) pci_write_config_byte(pdev, 0x53, tmp | (1<<3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) case PCI_VENDOR_ID_NETMOS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) /* MosChip frame-index-register bug */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) ehci_info(ehci, "applying MosChip frame-index workaround\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) ehci->frame_index_bug = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) case PCI_VENDOR_ID_HUAWEI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) /* Synopsys HC bug */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) if (pdev->device == 0xa239) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) ehci_info(ehci, "applying Synopsys HC workaround\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) ehci->has_synopsys_hc_bug = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) /* optional debug port, normally in the first BAR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) temp = pci_find_capability(pdev, PCI_CAP_ID_DBG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) if (temp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) pci_read_config_dword(pdev, temp, &temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) temp >>= 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) if (((temp >> 13) & 7) == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) u32 hcs_params = ehci_readl(ehci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) &ehci->caps->hcs_params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) temp &= 0x1fff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) ehci->debug = hcd->regs + temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) temp = ehci_readl(ehci, &ehci->debug->control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) ehci_info(ehci, "debug port %d%s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) HCS_DEBUG_PORT(hcs_params),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) (temp & DBGP_ENABLED) ? " IN USE" : "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) if (!(temp & DBGP_ENABLED))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) ehci->debug = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) retval = ehci_setup(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) if (retval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) /* These workarounds need to be applied after ehci_setup() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) switch (pdev->vendor) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) case PCI_VENDOR_ID_NEC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) case PCI_VENDOR_ID_INTEL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) case PCI_VENDOR_ID_AMD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) ehci->need_io_watchdog = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) case PCI_VENDOR_ID_NVIDIA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) switch (pdev->device) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) /* MCP89 chips on the MacBookAir3,1 give EPROTO when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) * fetching device descriptors unless LPM is disabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) * There are also intermittent problems enumerating
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) * devices with PPCD enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) case 0x0d9d:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) ehci_info(ehci, "disable ppcd for nvidia mcp89\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) ehci->has_ppcd = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) ehci->command &= ~CMD_PPCEE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) /* at least the Genesys GL880S needs fixup here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) temp = HCS_N_CC(ehci->hcs_params) * HCS_N_PCC(ehci->hcs_params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) temp &= 0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) if (temp && HCS_N_PORTS(ehci->hcs_params) > temp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) ehci_dbg(ehci, "bogus port configuration: "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) "cc=%d x pcc=%d < ports=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) HCS_N_CC(ehci->hcs_params),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) HCS_N_PCC(ehci->hcs_params),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) HCS_N_PORTS(ehci->hcs_params));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) switch (pdev->vendor) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) case 0x17a0: /* GENESYS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) /* GL880S: should be PORTS=2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) temp |= (ehci->hcs_params & ~0xf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) ehci->hcs_params = temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) case PCI_VENDOR_ID_NVIDIA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) /* NF4: should be PCC=10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) /* Serial Bus Release Number is at PCI 0x60 offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) if (pdev->vendor == PCI_VENDOR_ID_STMICRO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) && pdev->device == PCI_DEVICE_ID_STMICRO_USB_HOST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) ; /* ConneXT has no sbrn register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) else if (pdev->vendor == PCI_VENDOR_ID_HUAWEI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) && pdev->device == 0xa239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) ; /* HUAWEI Kunpeng920 USB EHCI has no sbrn register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) pci_read_config_byte(pdev, 0x60, &ehci->sbrn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) /* Keep this around for a while just in case some EHCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) * implementation uses legacy PCI PM support. This test
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) * can be removed on 17 Dec 2009 if the dev_warn() hasn't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) * been triggered by then.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) if (!device_can_wakeup(&pdev->dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) u16 port_wake;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) pci_read_config_word(pdev, 0x62, &port_wake);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) if (port_wake & 0x0001) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) dev_warn(&pdev->dev, "Enabling legacy PCI PM\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) device_set_wakeup_capable(&pdev->dev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) if (ehci->no_selective_suspend && device_can_wakeup(&pdev->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) ehci_warn(ehci, "selective suspend/wakeup unavailable\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) retval = ehci_pci_reinit(ehci, pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) /*-------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) /* suspend/resume, section 4.3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) /* These routines rely on the PCI bus glue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) * to handle powerdown and wakeup, and currently also on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) * transceivers that don't need any software attention to set up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) * the right sort of wakeup.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) * Also they depend on separate root hub suspend/resume.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) static int ehci_pci_resume(struct usb_hcd *hcd, bool hibernated)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) struct ehci_hcd *ehci = hcd_to_ehci(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) if (ehci_resume(hcd, hibernated) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) (void) ehci_pci_reinit(ehci, pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define ehci_suspend NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define ehci_pci_resume NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #endif /* CONFIG_PM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) static struct hc_driver __read_mostly ehci_pci_hc_driver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) static const struct ehci_driver_overrides pci_overrides __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) .reset = ehci_pci_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) /*-------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) static int ehci_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) if (is_bypassed_id(pdev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) return usb_hcd_pci_probe(pdev, id, &ehci_pci_hc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) static void ehci_pci_remove(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) pci_clear_mwi(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) usb_hcd_pci_remove(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) /* PCI driver selection metadata; PCI hotplugging uses this */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) static const struct pci_device_id pci_ids [] = { {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) /* handle any USB 2.0 EHCI controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_EHCI, ~0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) PCI_VDEVICE(STMICRO, PCI_DEVICE_ID_STMICRO_USB_HOST),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) { /* end: all zeroes */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) MODULE_DEVICE_TABLE(pci, pci_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) /* pci driver glue; this is a "new style" PCI driver module */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) static struct pci_driver ehci_pci_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) .name = hcd_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) .id_table = pci_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) .probe = ehci_pci_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) .remove = ehci_pci_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) .shutdown = usb_hcd_pci_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) .pm = &usb_hcd_pci_pm_ops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) static int __init ehci_pci_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) if (usb_disabled())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) pr_info("%s: " DRIVER_DESC "\n", hcd_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) ehci_init_driver(&ehci_pci_hc_driver, &pci_overrides);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) /* Entries for the PCI suspend/resume callbacks are special */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) ehci_pci_hc_driver.pci_suspend = ehci_suspend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) ehci_pci_hc_driver.pci_resume = ehci_pci_resume;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) return pci_register_driver(&ehci_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) module_init(ehci_pci_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) static void __exit ehci_pci_cleanup(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) pci_unregister_driver(&ehci_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) module_exit(ehci_pci_cleanup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) MODULE_DESCRIPTION(DRIVER_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) MODULE_AUTHOR("David Brownell");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) MODULE_AUTHOR("Alan Stern");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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