^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2001-2004 by David Brownell
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) /* this file is part of ehci-hcd.c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) /*-------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * EHCI Root Hub ... the nonsharable stuff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Registers don't need cpu_to_le32, that happens transparently
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) /*-------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define PORT_WAKE_BITS (PORT_WKOC_E|PORT_WKDISC_E|PORT_WKCONN_E)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) static void unlink_empty_async_suspended(struct ehci_hcd *ehci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) static int persist_enabled_on_companion(struct usb_device *udev, void *unused)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) return !udev->maxchild && udev->persist_enabled &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) udev->bus->root_hub->speed < USB_SPEED_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* After a power loss, ports that were owned by the companion must be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * reset so that the companion can still own them.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) static void ehci_handover_companion_ports(struct ehci_hcd *ehci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) u32 __iomem *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) int port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) __le32 buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) struct usb_hcd *hcd = ehci_to_hcd(ehci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) if (!ehci->owned_ports)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * USB 1.1 devices are mostly HIDs, which don't need to persist across
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * suspends. If we ensure that none of our companion's devices have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * persist_enabled (by looking through all USB 1.1 buses in the system),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * we can skip this and avoid slowing resume down. Devices without
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * persist will just get reenumerated shortly after resume anyway.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) if (!usb_for_each_dev(NULL, persist_enabled_on_companion))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* Make sure the ports are powered */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) port = HCS_N_PORTS(ehci->hcs_params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) while (port--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) if (test_bit(port, &ehci->owned_ports)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) reg = &ehci->regs->port_status[port];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) status = ehci_readl(ehci, reg) & ~PORT_RWC_BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) if (!(status & PORT_POWER))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) ehci_port_power(ehci, port, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /* Give the connections some time to appear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) msleep(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) spin_lock_irq(&ehci->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) port = HCS_N_PORTS(ehci->hcs_params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) while (port--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) if (test_bit(port, &ehci->owned_ports)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) reg = &ehci->regs->port_status[port];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) status = ehci_readl(ehci, reg) & ~PORT_RWC_BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* Port already owned by companion? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) if (status & PORT_OWNER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) clear_bit(port, &ehci->owned_ports);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) else if (test_bit(port, &ehci->companion_ports))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) ehci_writel(ehci, status & ~PORT_PE, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) spin_unlock_irq(&ehci->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) ehci_hub_control(hcd, SetPortFeature,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) USB_PORT_FEAT_RESET, port + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) spin_lock_irq(&ehci->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) spin_unlock_irq(&ehci->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) if (!ehci->owned_ports)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) msleep(90); /* Wait for resets to complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) spin_lock_irq(&ehci->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) port = HCS_N_PORTS(ehci->hcs_params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) while (port--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) if (test_bit(port, &ehci->owned_ports)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) spin_unlock_irq(&ehci->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) ehci_hub_control(hcd, GetPortStatus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 0, port + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) (char *) &buf, sizeof(buf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) spin_lock_irq(&ehci->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /* The companion should now own the port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * but if something went wrong the port must not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * remain enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) reg = &ehci->regs->port_status[port];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) status = ehci_readl(ehci, reg) & ~PORT_RWC_BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) if (status & PORT_OWNER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) ehci_writel(ehci, status | PORT_CSC, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) ehci_dbg(ehci, "failed handover port %d: %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) port + 1, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) ehci_writel(ehci, status & ~PORT_PE, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) ehci->owned_ports = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) spin_unlock_irq(&ehci->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static int ehci_port_change(struct ehci_hcd *ehci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) int i = HCS_N_PORTS(ehci->hcs_params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /* First check if the controller indicates a change event */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) if (ehci_readl(ehci, &ehci->regs->status) & STS_PCD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) * Not all controllers appear to update this while going from D3 to D0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * so check the individual port status registers as well
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) while (i--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) if (ehci_readl(ehci, &ehci->regs->port_status[i]) & PORT_CSC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) void ehci_adjust_port_wakeup_flags(struct ehci_hcd *ehci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) bool suspending, bool do_wakeup)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) int port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) u32 temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /* If remote wakeup is enabled for the root hub but disabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) * for the controller, we must adjust all the port wakeup flags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) * when the controller is suspended or resumed. In all other
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) * cases they don't need to be changed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) if (!ehci_to_hcd(ehci)->self.root_hub->do_remote_wakeup || do_wakeup)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) spin_lock_irq(&ehci->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /* clear phy low-power mode before changing wakeup flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) if (ehci->has_tdi_phy_lpm) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) port = HCS_N_PORTS(ehci->hcs_params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) while (port--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) u32 __iomem *hostpc_reg = &ehci->regs->hostpc[port];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) temp = ehci_readl(ehci, hostpc_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) ehci_writel(ehci, temp & ~HOSTPC_PHCD, hostpc_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) spin_unlock_irq(&ehci->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) msleep(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) spin_lock_irq(&ehci->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) port = HCS_N_PORTS(ehci->hcs_params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) while (port--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) u32 __iomem *reg = &ehci->regs->port_status[port];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) u32 t1 = ehci_readl(ehci, reg) & ~PORT_RWC_BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) u32 t2 = t1 & ~PORT_WAKE_BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /* If we are suspending the controller, clear the flags.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) * If we are resuming the controller, set the wakeup flags.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) if (!suspending) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) if (t1 & PORT_CONNECT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) t2 |= PORT_WKOC_E | PORT_WKDISC_E;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) t2 |= PORT_WKOC_E | PORT_WKCONN_E;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) ehci_writel(ehci, t2, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) /* enter phy low-power mode again */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) if (ehci->has_tdi_phy_lpm) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) port = HCS_N_PORTS(ehci->hcs_params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) while (port--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) u32 __iomem *hostpc_reg = &ehci->regs->hostpc[port];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) temp = ehci_readl(ehci, hostpc_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) ehci_writel(ehci, temp | HOSTPC_PHCD, hostpc_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) /* Does the root hub have a port wakeup pending? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) if (!suspending && ehci_port_change(ehci))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) usb_hcd_resume_root_hub(ehci_to_hcd(ehci));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) spin_unlock_irq(&ehci->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) EXPORT_SYMBOL_GPL(ehci_adjust_port_wakeup_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) static int ehci_bus_suspend (struct usb_hcd *hcd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) struct ehci_hcd *ehci = hcd_to_ehci (hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) int port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) int mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) int changed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) bool fs_idle_delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) ehci_dbg(ehci, "suspend root hub\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) if (time_before (jiffies, ehci->next_statechange))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) msleep(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) /* stop the schedules */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) ehci_quiesce(ehci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) spin_lock_irq (&ehci->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) if (ehci->rh_state < EHCI_RH_RUNNING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) /* Once the controller is stopped, port resumes that are already
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) * in progress won't complete. Hence if remote wakeup is enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) * for the root hub and any ports are in the middle of a resume or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) * remote wakeup, we must fail the suspend.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) if (hcd->self.root_hub->do_remote_wakeup) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) if (ehci->resuming_ports) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) spin_unlock_irq(&ehci->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) ehci_dbg(ehci, "suspend failed because a port is resuming\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) /* Unlike other USB host controller types, EHCI doesn't have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) * any notion of "global" or bus-wide suspend. The driver has
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) * to manually suspend all the active unsuspended ports, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) * then manually resume them in the bus_resume() routine.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) ehci->bus_suspended = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) ehci->owned_ports = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) changed = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) fs_idle_delay = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) port = HCS_N_PORTS(ehci->hcs_params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) while (port--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) u32 __iomem *reg = &ehci->regs->port_status [port];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) u32 t1 = ehci_readl(ehci, reg) & ~PORT_RWC_BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) u32 t2 = t1 & ~PORT_WAKE_BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) /* keep track of which ports we suspend */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) if (t1 & PORT_OWNER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) set_bit(port, &ehci->owned_ports);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) else if ((t1 & PORT_PE) && !(t1 & PORT_SUSPEND)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) t2 |= PORT_SUSPEND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) set_bit(port, &ehci->bus_suspended);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) /* enable remote wakeup on all ports, if told to do so */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) if (hcd->self.root_hub->do_remote_wakeup) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) /* only enable appropriate wake bits, otherwise the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) * hardware can not go phy low power mode. If a race
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) * condition happens here(connection change during bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) * set), the port change detection will finally fix it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) if (t1 & PORT_CONNECT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) t2 |= PORT_WKOC_E | PORT_WKDISC_E;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) t2 |= PORT_WKOC_E | PORT_WKCONN_E;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) if (t1 != t2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) * On some controllers, Wake-On-Disconnect will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) * generate false wakeup signals until the bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) * switches over to full-speed idle. For their
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) * sake, add a delay if we need one.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) if ((t2 & PORT_WKDISC_E) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) ehci_port_speed(ehci, t2) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) USB_PORT_STAT_HIGH_SPEED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) fs_idle_delay = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) ehci_writel(ehci, t2, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) changed = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) spin_unlock_irq(&ehci->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) if (changed && ehci_has_fsl_susp_errata(ehci))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) * Wait for at least 10 millisecondes to ensure the controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) * enter the suspend status before initiating a port resume
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) * using the Force Port Resume bit (Not-EHCI compatible).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) usleep_range(10000, 20000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) if ((changed && ehci->has_tdi_phy_lpm) || fs_idle_delay) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) * Wait for HCD to enter low-power mode or for the bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) * to switch to full-speed idle.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) usleep_range(5000, 5500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) if (changed && ehci->has_tdi_phy_lpm) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) spin_lock_irq(&ehci->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) port = HCS_N_PORTS(ehci->hcs_params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) while (port--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) u32 __iomem *hostpc_reg = &ehci->regs->hostpc[port];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) u32 t3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) t3 = ehci_readl(ehci, hostpc_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) ehci_writel(ehci, t3 | HOSTPC_PHCD, hostpc_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) t3 = ehci_readl(ehci, hostpc_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) ehci_dbg(ehci, "Port %d phy low-power mode %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) port, (t3 & HOSTPC_PHCD) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) "succeeded" : "failed");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) spin_unlock_irq(&ehci->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) /* Apparently some devices need a >= 1-uframe delay here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) if (ehci->bus_suspended)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) udelay(150);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) /* turn off now-idle HC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) ehci_halt (ehci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) spin_lock_irq(&ehci->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) if (ehci->enabled_hrtimer_events & BIT(EHCI_HRTIMER_POLL_DEAD))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) ehci_handle_controller_death(ehci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) if (ehci->rh_state != EHCI_RH_RUNNING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) ehci->rh_state = EHCI_RH_SUSPENDED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) unlink_empty_async_suspended(ehci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) /* Some Synopsys controllers mistakenly leave IAA turned on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) ehci_writel(ehci, STS_IAA, &ehci->regs->status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) /* Any IAA cycle that started before the suspend is now invalid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) end_iaa_cycle(ehci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) ehci_handle_start_intr_unlinks(ehci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) ehci_handle_intr_unlinks(ehci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) end_free_itds(ehci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) /* allow remote wakeup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) mask = INTR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) if (!hcd->self.root_hub->do_remote_wakeup)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) mask &= ~STS_PCD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) ehci_writel(ehci, mask, &ehci->regs->intr_enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) ehci_readl(ehci, &ehci->regs->intr_enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) ehci->next_statechange = jiffies + msecs_to_jiffies(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) ehci->enabled_hrtimer_events = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) ehci->next_hrtimer_event = EHCI_HRTIMER_NO_EVENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) spin_unlock_irq (&ehci->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) hrtimer_cancel(&ehci->hrtimer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) /* caller has locked the root hub, and should reset/reinit on error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) static int ehci_bus_resume (struct usb_hcd *hcd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) struct ehci_hcd *ehci = hcd_to_ehci (hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) u32 temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) u32 power_okay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) unsigned long resume_needed = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) if (time_before (jiffies, ehci->next_statechange))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) msleep(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) spin_lock_irq (&ehci->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) if (!HCD_HW_ACCESSIBLE(hcd) || ehci->shutdown)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) goto shutdown;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) if (unlikely(ehci->debug)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) if (!dbgp_reset_prep(hcd))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) ehci->debug = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) dbgp_external_startup(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) /* Ideally and we've got a real resume here, and no port's power
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) * was lost. (For PCI, that means Vaux was maintained.) But we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) * could instead be restoring a swsusp snapshot -- so that BIOS was
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) * the last user of the controller, not reset/pm hardware keeping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) * state we gave to it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) power_okay = ehci_readl(ehci, &ehci->regs->intr_enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) ehci_dbg(ehci, "resume root hub%s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) power_okay ? "" : " after power loss");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) /* at least some APM implementations will try to deliver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) * IRQs right away, so delay them until we're ready.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) ehci_writel(ehci, 0, &ehci->regs->intr_enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) /* re-init operational registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) ehci_writel(ehci, 0, &ehci->regs->segment);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) ehci_writel(ehci, ehci->periodic_dma, &ehci->regs->frame_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) ehci_writel(ehci, (u32) ehci->async->qh_dma, &ehci->regs->async_next);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) /* restore CMD_RUN, framelist size, and irq threshold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) ehci->command |= CMD_RUN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) ehci_writel(ehci, ehci->command, &ehci->regs->command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) ehci->rh_state = EHCI_RH_RUNNING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) * According to Bugzilla #8190, the port status for some controllers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) * will be wrong without a delay. At their wrong status, the port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) * is enabled, but not suspended neither resumed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) i = HCS_N_PORTS(ehci->hcs_params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) while (i--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) temp = ehci_readl(ehci, &ehci->regs->port_status[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) if ((temp & PORT_PE) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) !(temp & (PORT_SUSPEND | PORT_RESUME))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) ehci_dbg(ehci, "Port status(0x%x) is wrong\n", temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) spin_unlock_irq(&ehci->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) msleep(8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) spin_lock_irq(&ehci->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) if (ehci->shutdown)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) goto shutdown;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) /* clear phy low-power mode before resume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) if (ehci->bus_suspended && ehci->has_tdi_phy_lpm) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) i = HCS_N_PORTS(ehci->hcs_params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) while (i--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) if (test_bit(i, &ehci->bus_suspended)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) u32 __iomem *hostpc_reg =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) &ehci->regs->hostpc[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) temp = ehci_readl(ehci, hostpc_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) ehci_writel(ehci, temp & ~HOSTPC_PHCD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) hostpc_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) spin_unlock_irq(&ehci->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) msleep(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) spin_lock_irq(&ehci->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) if (ehci->shutdown)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) goto shutdown;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) /* manually resume the ports we suspended during bus_suspend() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) i = HCS_N_PORTS (ehci->hcs_params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) while (i--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) temp = ehci_readl(ehci, &ehci->regs->port_status [i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) temp &= ~(PORT_RWC_BITS | PORT_WAKE_BITS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) if (test_bit(i, &ehci->bus_suspended) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) (temp & PORT_SUSPEND)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) temp |= PORT_RESUME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) set_bit(i, &resume_needed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) ehci_writel(ehci, temp, &ehci->regs->port_status [i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) * msleep for USB_RESUME_TIMEOUT ms only if code is trying to resume
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) * port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) if (resume_needed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) spin_unlock_irq(&ehci->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) msleep(USB_RESUME_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) spin_lock_irq(&ehci->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) if (ehci->shutdown)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) goto shutdown;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) i = HCS_N_PORTS (ehci->hcs_params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) while (i--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) temp = ehci_readl(ehci, &ehci->regs->port_status [i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) if (test_bit(i, &resume_needed)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) temp &= ~(PORT_RWC_BITS | PORT_SUSPEND | PORT_RESUME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) ehci_writel(ehci, temp, &ehci->regs->port_status [i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) ehci->next_statechange = jiffies + msecs_to_jiffies(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) spin_unlock_irq(&ehci->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) ehci_handover_companion_ports(ehci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) /* Now we can safely re-enable irqs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) spin_lock_irq(&ehci->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) if (ehci->shutdown)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) goto shutdown;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) ehci_writel(ehci, INTR_MASK, &ehci->regs->intr_enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) (void) ehci_readl(ehci, &ehci->regs->intr_enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) spin_unlock_irq(&ehci->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) shutdown:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) spin_unlock_irq(&ehci->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) return -ESHUTDOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) static unsigned long ehci_get_resuming_ports(struct usb_hcd *hcd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) struct ehci_hcd *ehci = hcd_to_ehci(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) return ehci->resuming_ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) #define ehci_bus_suspend NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) #define ehci_bus_resume NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) #define ehci_get_resuming_ports NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) #endif /* CONFIG_PM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) /*-------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) * Sets the owner of a port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) static void set_owner(struct ehci_hcd *ehci, int portnum, int new_owner)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) u32 __iomem *status_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) u32 port_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) int try;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) status_reg = &ehci->regs->port_status[portnum];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) * The controller won't set the OWNER bit if the port is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) * enabled, so this loop will sometimes require at least two
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) * iterations: one to disable the port and one to set OWNER.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) for (try = 4; try > 0; --try) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) spin_lock_irq(&ehci->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) port_status = ehci_readl(ehci, status_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) if ((port_status & PORT_OWNER) == new_owner
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) || (port_status & (PORT_OWNER | PORT_CONNECT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) try = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) port_status ^= PORT_OWNER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) port_status &= ~(PORT_PE | PORT_RWC_BITS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) ehci_writel(ehci, port_status, status_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) spin_unlock_irq(&ehci->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) if (try > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) msleep(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) /*-------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) static int check_reset_complete (
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) struct ehci_hcd *ehci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) int index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) u32 __iomem *status_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) int port_status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) if (!(port_status & PORT_CONNECT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) return port_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) /* if reset finished and it's still not enabled -- handoff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) if (!(port_status & PORT_PE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) /* with integrated TT, there's nobody to hand it to! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) if (ehci_is_TDI(ehci)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) ehci_dbg (ehci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) "Failed to enable port %d on root hub TT\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) index+1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) return port_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) ehci_dbg (ehci, "port %d full speed --> companion\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) index + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) // what happens if HCS_N_CC(params) == 0 ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) port_status |= PORT_OWNER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) port_status &= ~PORT_RWC_BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) ehci_writel(ehci, port_status, status_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) /* ensure 440EPX ohci controller state is operational */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) if (ehci->has_amcc_usb23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) set_ohci_hcfs(ehci, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) ehci_dbg(ehci, "port %d reset complete, port enabled\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) index + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) /* ensure 440EPx ohci controller state is suspended */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) if (ehci->has_amcc_usb23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) set_ohci_hcfs(ehci, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) return port_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) /*-------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) /* build "status change" packet (one or two bytes) from HC registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) ehci_hub_status_data (struct usb_hcd *hcd, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) struct ehci_hcd *ehci = hcd_to_ehci (hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) u32 temp, status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) int ports, i, retval = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) u32 ppcd = ~0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) /* init status to no-changes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) buf [0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) ports = HCS_N_PORTS (ehci->hcs_params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) if (ports > 7) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) buf [1] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) retval++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) /* Inform the core about resumes-in-progress by returning
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) * a non-zero value even if there are no status changes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) status = ehci->resuming_ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) /* Some boards (mostly VIA?) report bogus overcurrent indications,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) * causing massive log spam unless we completely ignore them. It
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) * may be relevant that VIA VT8235 controllers, where PORT_POWER is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) * always set, seem to clear PORT_OCC and PORT_CSC when writing to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) * PORT_POWER; that's surprising, but maybe within-spec.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) if (!ignore_oc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) mask = PORT_CSC | PORT_PEC | PORT_OCC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) mask = PORT_CSC | PORT_PEC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) // PORT_RESUME from hardware ~= PORT_STAT_C_SUSPEND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) /* no hub change reports (bit 0) for now (power, ...) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) /* port N changes (bit N)? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) spin_lock_irqsave (&ehci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) /* get per-port change detect bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) if (ehci->has_ppcd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) ppcd = ehci_readl(ehci, &ehci->regs->status) >> 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) for (i = 0; i < ports; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) /* leverage per-port change bits feature */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) if (ppcd & (1 << i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) temp = ehci_readl(ehci, &ehci->regs->port_status[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) temp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) * Return status information even for ports with OWNER set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) * Otherwise hub_wq wouldn't see the disconnect event when a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) * high-speed device is switched over to the companion
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) * controller by the user.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) if ((temp & mask) != 0 || test_bit(i, &ehci->port_c_suspend)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) || (ehci->reset_done[i] && time_after_eq(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) jiffies, ehci->reset_done[i]))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) if (i < 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) buf [0] |= 1 << (i + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) buf [1] |= 1 << (i - 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) status = STS_PCD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) /* If a resume is in progress, make sure it can finish */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) if (ehci->resuming_ports)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) mod_timer(&hcd->rh_timer, jiffies + msecs_to_jiffies(25));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) spin_unlock_irqrestore (&ehci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) return status ? retval : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) /*-------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) ehci_hub_descriptor (
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) struct ehci_hcd *ehci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) struct usb_hub_descriptor *desc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) int ports = HCS_N_PORTS (ehci->hcs_params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) u16 temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) desc->bDescriptorType = USB_DT_HUB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) desc->bPwrOn2PwrGood = 10; /* ehci 1.0, 2.3.9 says 20ms max */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) desc->bHubContrCurrent = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) desc->bNbrPorts = ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) temp = 1 + (ports / 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) desc->bDescLength = 7 + 2 * temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) /* two bitmaps: ports removable, and usb 1.0 legacy PortPwrCtrlMask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) memset(&desc->u.hs.DeviceRemovable[0], 0, temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) memset(&desc->u.hs.DeviceRemovable[temp], 0xff, temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) temp = HUB_CHAR_INDV_PORT_OCPM; /* per-port overcurrent reporting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) if (HCS_PPC (ehci->hcs_params))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) temp |= HUB_CHAR_INDV_PORT_LPSM; /* per-port power control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) temp |= HUB_CHAR_NO_LPSM; /* no power switching */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) // re-enable when we support USB_PORT_FEAT_INDICATOR below.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) if (HCS_INDICATOR (ehci->hcs_params))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) temp |= HUB_CHAR_PORTIND; /* per-port indicators (LEDs) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) desc->wHubCharacteristics = cpu_to_le16(temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) /*-------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) #ifdef CONFIG_USB_HCD_TEST_MODE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) #define EHSET_TEST_SINGLE_STEP_SET_FEATURE 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) static void usb_ehset_completion(struct urb *urb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) struct completion *done = urb->context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) complete(done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) static int submit_single_step_set_feature(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) struct usb_hcd *hcd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) struct urb *urb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) int is_setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) * Allocate and initialize a control URB. This request will be used by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) * EHSET SINGLE_STEP_SET_FEATURE test in which the DATA and STATUS stages
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) * of the GetDescriptor request are sent 15 seconds after the SETUP stage.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) * Return NULL if failed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) static struct urb *request_single_step_set_feature_urb(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) struct usb_device *udev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) void *dr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) void *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) struct completion *done
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) struct urb *urb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) struct usb_hcd *hcd = bus_to_hcd(udev->bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) struct usb_host_endpoint *ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) urb = usb_alloc_urb(0, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) if (!urb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) urb->pipe = usb_rcvctrlpipe(udev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) ep = (usb_pipein(urb->pipe) ? udev->ep_in : udev->ep_out)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) [usb_pipeendpoint(urb->pipe)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) if (!ep) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) usb_free_urb(urb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) urb->ep = ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) urb->dev = udev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) urb->setup_packet = (void *)dr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) urb->transfer_buffer = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) urb->transfer_buffer_length = USB_DT_DEVICE_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) urb->complete = usb_ehset_completion;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) urb->status = -EINPROGRESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) urb->actual_length = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) urb->transfer_flags = URB_DIR_IN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) usb_get_urb(urb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) atomic_inc(&urb->use_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) atomic_inc(&urb->dev->urbnum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) urb->setup_dma = dma_map_single(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) hcd->self.sysdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) urb->setup_packet,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) sizeof(struct usb_ctrlrequest),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) urb->transfer_dma = dma_map_single(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) hcd->self.sysdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) urb->transfer_buffer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) urb->transfer_buffer_length,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) urb->context = done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) return urb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) static int ehset_single_step_set_feature(struct usb_hcd *hcd, int port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) int retval = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) struct usb_ctrlrequest *dr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) struct urb *urb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) struct usb_device *udev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) struct ehci_hcd *ehci = hcd_to_ehci(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) struct usb_device_descriptor *buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) DECLARE_COMPLETION_ONSTACK(done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) /* Obtain udev of the rhub's child port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) udev = usb_hub_find_child(hcd->self.root_hub, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) if (!udev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) ehci_err(ehci, "No device attached to the RootHub\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) buf = kmalloc(USB_DT_DEVICE_SIZE, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) if (!buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) dr = kmalloc(sizeof(struct usb_ctrlrequest), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) if (!dr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) kfree(buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) /* Fill Setup packet for GetDescriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) dr->bRequestType = USB_DIR_IN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) dr->bRequest = USB_REQ_GET_DESCRIPTOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) dr->wValue = cpu_to_le16(USB_DT_DEVICE << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) dr->wIndex = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) dr->wLength = cpu_to_le16(USB_DT_DEVICE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) urb = request_single_step_set_feature_urb(udev, dr, buf, &done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) if (!urb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) goto cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) /* Submit just the SETUP stage */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) retval = submit_single_step_set_feature(hcd, urb, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) if (retval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) goto out1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) if (!wait_for_completion_timeout(&done, msecs_to_jiffies(2000))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) usb_kill_urb(urb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) retval = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) ehci_err(ehci, "%s SETUP stage timed out on ep0\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) goto out1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) msleep(15 * 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) /* Complete remaining DATA and STATUS stages using the same URB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) urb->status = -EINPROGRESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) usb_get_urb(urb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) atomic_inc(&urb->use_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) atomic_inc(&urb->dev->urbnum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) retval = submit_single_step_set_feature(hcd, urb, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) if (!retval && !wait_for_completion_timeout(&done,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) msecs_to_jiffies(2000))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) usb_kill_urb(urb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) retval = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) ehci_err(ehci, "%s IN stage timed out on ep0\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) out1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) usb_free_urb(urb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) cleanup:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) kfree(dr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) kfree(buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) #endif /* CONFIG_USB_HCD_TEST_MODE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) /*-------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) int ehci_hub_control(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) struct usb_hcd *hcd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) u16 typeReq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) u16 wValue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) u16 wIndex,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) char *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) u16 wLength
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) struct ehci_hcd *ehci = hcd_to_ehci (hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) int ports = HCS_N_PORTS (ehci->hcs_params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) u32 __iomem *status_reg, *hostpc_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) u32 temp, temp1, status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) int retval = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) unsigned selector;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) * Avoid underflow while calculating (wIndex & 0xff) - 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) * The compiler might deduce that wIndex can never be 0 and then
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) * optimize away the tests for !wIndex below.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) temp = wIndex & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) temp -= (temp > 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) status_reg = &ehci->regs->port_status[temp];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) hostpc_reg = &ehci->regs->hostpc[temp];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) * FIXME: support SetPortFeatures USB_PORT_FEAT_INDICATOR.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) * HCS_INDICATOR may say we can change LEDs to off/amber/green.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) * (track current state ourselves) ... blink for diagnostics,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) * power, "this is the one", etc. EHCI spec supports this.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) spin_lock_irqsave (&ehci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) switch (typeReq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) case ClearHubFeature:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) switch (wValue) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) case C_HUB_LOCAL_POWER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) case C_HUB_OVER_CURRENT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) /* no hub-wide feature/status flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) case ClearPortFeature:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) if (!wIndex || wIndex > ports)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) wIndex--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) temp = ehci_readl(ehci, status_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) temp &= ~PORT_RWC_BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) * Even if OWNER is set, so the port is owned by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) * companion controller, hub_wq needs to be able to clear
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) * the port-change status bits (especially
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) * USB_PORT_STAT_C_CONNECTION).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) switch (wValue) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) case USB_PORT_FEAT_ENABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) ehci_writel(ehci, temp & ~PORT_PE, status_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) case USB_PORT_FEAT_C_ENABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) ehci_writel(ehci, temp | PORT_PEC, status_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) case USB_PORT_FEAT_SUSPEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) if (temp & PORT_RESET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) if (ehci->no_selective_suspend)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) #ifdef CONFIG_USB_OTG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) if ((hcd->self.otg_port == (wIndex + 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) && hcd->self.b_hnp_enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) otg_start_hnp(hcd->usb_phy->otg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) if (!(temp & PORT_SUSPEND))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) if ((temp & PORT_PE) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) /* clear phy low-power mode before resume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) if (ehci->has_tdi_phy_lpm) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) temp1 = ehci_readl(ehci, hostpc_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) ehci_writel(ehci, temp1 & ~HOSTPC_PHCD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) hostpc_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) spin_unlock_irqrestore(&ehci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) msleep(5);/* wait to leave low-power mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) spin_lock_irqsave(&ehci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) /* resume signaling for 20 msec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) temp &= ~PORT_WAKE_BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) ehci_writel(ehci, temp | PORT_RESUME, status_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) ehci->reset_done[wIndex] = jiffies
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) + msecs_to_jiffies(USB_RESUME_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) set_bit(wIndex, &ehci->resuming_ports);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) usb_hcd_start_port_resume(&hcd->self, wIndex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) case USB_PORT_FEAT_C_SUSPEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) clear_bit(wIndex, &ehci->port_c_suspend);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) case USB_PORT_FEAT_POWER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) if (HCS_PPC(ehci->hcs_params)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) spin_unlock_irqrestore(&ehci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) ehci_port_power(ehci, wIndex, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) spin_lock_irqsave(&ehci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) case USB_PORT_FEAT_C_CONNECTION:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) ehci_writel(ehci, temp | PORT_CSC, status_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) case USB_PORT_FEAT_C_OVER_CURRENT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) ehci_writel(ehci, temp | PORT_OCC, status_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) case USB_PORT_FEAT_C_RESET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) /* GetPortStatus clears reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) ehci_readl(ehci, &ehci->regs->command); /* unblock posted write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) case GetHubDescriptor:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) ehci_hub_descriptor (ehci, (struct usb_hub_descriptor *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) case GetHubStatus:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) /* no hub-wide feature/status flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) memset (buf, 0, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) //cpu_to_le32s ((u32 *) buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) case GetPortStatus:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) if (!wIndex || wIndex > ports)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) wIndex--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) temp = ehci_readl(ehci, status_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) // wPortChange bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) if (temp & PORT_CSC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) status |= USB_PORT_STAT_C_CONNECTION << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) if (temp & PORT_PEC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) status |= USB_PORT_STAT_C_ENABLE << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) if ((temp & PORT_OCC) && !ignore_oc){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) status |= USB_PORT_STAT_C_OVERCURRENT << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) * Hubs should disable port power on over-current.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) * However, not all EHCI implementations do this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) * automatically, even if they _do_ support per-port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) * power switching; they're allowed to just limit the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) * current. hub_wq will turn the power back on.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) if (((temp & PORT_OC) || (ehci->need_oc_pp_cycle))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) && HCS_PPC(ehci->hcs_params)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) spin_unlock_irqrestore(&ehci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) ehci_port_power(ehci, wIndex, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) spin_lock_irqsave(&ehci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) temp = ehci_readl(ehci, status_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) /* no reset or resume pending */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) if (!ehci->reset_done[wIndex]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) /* Remote Wakeup received? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) if (temp & PORT_RESUME) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) /* resume signaling for 20 msec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) ehci->reset_done[wIndex] = jiffies
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) + msecs_to_jiffies(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) usb_hcd_start_port_resume(&hcd->self, wIndex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) set_bit(wIndex, &ehci->resuming_ports);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) /* check the port again */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) mod_timer(&ehci_to_hcd(ehci)->rh_timer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) ehci->reset_done[wIndex]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) /* reset or resume not yet complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) } else if (!time_after_eq(jiffies, ehci->reset_done[wIndex])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) ; /* wait until it is complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) /* resume completed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) } else if (test_bit(wIndex, &ehci->resuming_ports)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) clear_bit(wIndex, &ehci->suspended_ports);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) set_bit(wIndex, &ehci->port_c_suspend);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) ehci->reset_done[wIndex] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) usb_hcd_end_port_resume(&hcd->self, wIndex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) /* stop resume signaling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) temp &= ~(PORT_RWC_BITS | PORT_SUSPEND | PORT_RESUME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) ehci_writel(ehci, temp, status_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) clear_bit(wIndex, &ehci->resuming_ports);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) retval = ehci_handshake(ehci, status_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) PORT_RESUME, 0, 2000 /* 2msec */);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) if (retval != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) ehci_err(ehci, "port %d resume error %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) wIndex + 1, retval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) temp = ehci_readl(ehci, status_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) /* whoever resets must GetPortStatus to complete it!! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) status |= USB_PORT_STAT_C_RESET << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) ehci->reset_done [wIndex] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) /* force reset to complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) ehci_writel(ehci, temp & ~(PORT_RWC_BITS | PORT_RESET),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) status_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) /* REVISIT: some hardware needs 550+ usec to clear
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) * this bit; seems too long to spin routinely...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) retval = ehci_handshake(ehci, status_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) PORT_RESET, 0, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) if (retval != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) ehci_err (ehci, "port %d reset error %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) wIndex + 1, retval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) /* see what we found out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) temp = check_reset_complete (ehci, wIndex, status_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) ehci_readl(ehci, status_reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) /* transfer dedicated ports to the companion hc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) if ((temp & PORT_CONNECT) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) test_bit(wIndex, &ehci->companion_ports)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) temp &= ~PORT_RWC_BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) temp |= PORT_OWNER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) ehci_writel(ehci, temp, status_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) ehci_dbg(ehci, "port %d --> companion\n", wIndex + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) temp = ehci_readl(ehci, status_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) * Even if OWNER is set, there's no harm letting hub_wq
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) * see the wPortStatus values (they should all be 0 except
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) * for PORT_POWER anyway).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) if (temp & PORT_CONNECT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) status |= USB_PORT_STAT_CONNECTION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) // status may be from integrated TT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) if (ehci->has_hostpc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) temp1 = ehci_readl(ehci, hostpc_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) status |= ehci_port_speed(ehci, temp1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) status |= ehci_port_speed(ehci, temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) if (temp & PORT_PE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) status |= USB_PORT_STAT_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) /* maybe the port was unsuspended without our knowledge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) if (temp & (PORT_SUSPEND|PORT_RESUME)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) status |= USB_PORT_STAT_SUSPEND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) } else if (test_bit(wIndex, &ehci->suspended_ports)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) clear_bit(wIndex, &ehci->suspended_ports);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) clear_bit(wIndex, &ehci->resuming_ports);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) ehci->reset_done[wIndex] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) if (temp & PORT_PE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) set_bit(wIndex, &ehci->port_c_suspend);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) usb_hcd_end_port_resume(&hcd->self, wIndex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) if (temp & PORT_OC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) status |= USB_PORT_STAT_OVERCURRENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) if (temp & PORT_RESET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) status |= USB_PORT_STAT_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) if (temp & PORT_POWER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) status |= USB_PORT_STAT_POWER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) if (test_bit(wIndex, &ehci->port_c_suspend))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) status |= USB_PORT_STAT_C_SUSPEND << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) if (status & ~0xffff) /* only if wPortChange is interesting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) dbg_port(ehci, "GetStatus", wIndex + 1, temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) put_unaligned_le32(status, buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) case SetHubFeature:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) switch (wValue) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) case C_HUB_LOCAL_POWER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) case C_HUB_OVER_CURRENT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) /* no hub-wide feature/status flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) case SetPortFeature:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) selector = wIndex >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) wIndex &= 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) if (unlikely(ehci->debug)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) /* If the debug port is active any port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) * feature requests should get denied */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) if (wIndex == HCS_DEBUG_PORT(ehci->hcs_params) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) (readl(&ehci->debug->control) & DBGP_ENABLED)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) retval = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) goto error_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) if (!wIndex || wIndex > ports)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) wIndex--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) temp = ehci_readl(ehci, status_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) if (temp & PORT_OWNER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) temp &= ~PORT_RWC_BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) switch (wValue) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) case USB_PORT_FEAT_SUSPEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) if (ehci->no_selective_suspend)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) if ((temp & PORT_PE) == 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) || (temp & PORT_RESET) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) /* After above check the port must be connected.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) * Set appropriate bit thus could put phy into low power
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) * mode if we have tdi_phy_lpm feature
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) temp &= ~PORT_WKCONN_E;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) temp |= PORT_WKDISC_E | PORT_WKOC_E;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) ehci_writel(ehci, temp | PORT_SUSPEND, status_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) if (ehci->has_tdi_phy_lpm) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) spin_unlock_irqrestore(&ehci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) msleep(5);/* 5ms for HCD enter low pwr mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) spin_lock_irqsave(&ehci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) temp1 = ehci_readl(ehci, hostpc_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) ehci_writel(ehci, temp1 | HOSTPC_PHCD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) hostpc_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) temp1 = ehci_readl(ehci, hostpc_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) ehci_dbg(ehci, "Port%d phy low pwr mode %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) wIndex, (temp1 & HOSTPC_PHCD) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) "succeeded" : "failed");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) if (ehci_has_fsl_susp_errata(ehci)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) /* 10ms for HCD enter suspend */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) spin_unlock_irqrestore(&ehci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) usleep_range(10000, 20000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) spin_lock_irqsave(&ehci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) set_bit(wIndex, &ehci->suspended_ports);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) case USB_PORT_FEAT_POWER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) if (HCS_PPC(ehci->hcs_params)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) spin_unlock_irqrestore(&ehci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) ehci_port_power(ehci, wIndex, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) spin_lock_irqsave(&ehci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) case USB_PORT_FEAT_RESET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) if (temp & (PORT_SUSPEND|PORT_RESUME))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) /* line status bits may report this as low speed,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) * which can be fine if this root hub has a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) * transaction translator built in.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) if ((temp & (PORT_PE|PORT_CONNECT)) == PORT_CONNECT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) && !ehci_is_TDI(ehci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) && PORT_USB11 (temp)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) ehci_dbg (ehci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) "port %d low speed --> companion\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) wIndex + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) temp |= PORT_OWNER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) temp |= PORT_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) temp &= ~PORT_PE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) * caller must wait, then call GetPortStatus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) * usb 2.0 spec says 50 ms resets on root
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) ehci->reset_done [wIndex] = jiffies
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) + msecs_to_jiffies (50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) * Force full-speed connect for FSL high-speed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) * erratum; disable HS Chirp by setting PFSC bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) if (ehci_has_fsl_hs_errata(ehci))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) temp |= (1 << PORTSC_FSL_PFSC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) ehci_writel(ehci, temp, status_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) /* For downstream facing ports (these): one hub port is put
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) * into test mode according to USB2 11.24.2.13, then the hub
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) * must be reset (which for root hub now means rmmod+modprobe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) * or else system reboot). See EHCI 2.3.9 and 4.14 for info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) * about the EHCI-specific stuff.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) case USB_PORT_FEAT_TEST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) #ifdef CONFIG_USB_HCD_TEST_MODE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) if (selector == EHSET_TEST_SINGLE_STEP_SET_FEATURE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) spin_unlock_irqrestore(&ehci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) retval = ehset_single_step_set_feature(hcd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) wIndex + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) spin_lock_irqsave(&ehci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) if (!selector || selector > 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) spin_unlock_irqrestore(&ehci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) ehci_quiesce(ehci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) spin_lock_irqsave(&ehci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) /* Put all enabled ports into suspend */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) while (ports--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) u32 __iomem *sreg =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) &ehci->regs->port_status[ports];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) temp = ehci_readl(ehci, sreg) & ~PORT_RWC_BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) if (temp & PORT_PE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) ehci_writel(ehci, temp | PORT_SUSPEND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) sreg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) spin_unlock_irqrestore(&ehci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) ehci_halt(ehci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) spin_lock_irqsave(&ehci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) temp = ehci_readl(ehci, status_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) temp |= selector << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) ehci_writel(ehci, temp, status_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) ehci_readl(ehci, &ehci->regs->command); /* unblock posted writes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) /* "stall" on error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) retval = -EPIPE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) error_exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) spin_unlock_irqrestore (&ehci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) EXPORT_SYMBOL_GPL(ehci_hub_control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) static void ehci_relinquish_port(struct usb_hcd *hcd, int portnum)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) struct ehci_hcd *ehci = hcd_to_ehci(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) if (ehci_is_TDI(ehci))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) set_owner(ehci, --portnum, PORT_OWNER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) static int ehci_port_handed_over(struct usb_hcd *hcd, int portnum)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) struct ehci_hcd *ehci = hcd_to_ehci(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) u32 __iomem *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) if (ehci_is_TDI(ehci))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) reg = &ehci->regs->port_status[portnum - 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) return ehci_readl(ehci, reg) & PORT_OWNER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) static int ehci_port_power(struct ehci_hcd *ehci, int portnum, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) struct usb_hcd *hcd = ehci_to_hcd(ehci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) u32 __iomem *status_reg = &ehci->regs->port_status[portnum];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) u32 temp = ehci_readl(ehci, status_reg) & ~PORT_RWC_BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) ehci_writel(ehci, temp | PORT_POWER, status_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) ehci_writel(ehci, temp & ~PORT_POWER, status_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) if (hcd->driver->port_power)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) hcd->driver->port_power(hcd, portnum, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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