^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Enhanced Host Controller Interface (EHCI) driver for USB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Maintainer: Alan Stern <stern@rowland.harvard.edu>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (c) 2000-2004 by David Brownell
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/dmapool.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/vmalloc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/hrtimer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/list.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/usb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/usb/hcd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/usb/otg.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/moduleparam.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/debugfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <asm/byteorder.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <asm/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <asm/unaligned.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #if defined(CONFIG_PPC_PS3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <asm/firmware.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /*-------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * EHCI hc_driver implementation ... experimental, incomplete.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * Based on the final 1.0 register interface specification.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * USB 2.0 shows up in upcoming www.pcmcia.org technology.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * First was PCMCIA, like ISA; then CardBus, which is PCI.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * Next comes "CardBay", using USB 2.0 signals.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * Contains additional contributions by Brad Hards, Rory Bolt, and others.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * Special thanks to Intel and VIA for providing host controllers to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * test this driver on, and Cypress (including In-System Design) for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * providing early devices for those host controllers to talk to!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define DRIVER_AUTHOR "David Brownell"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define DRIVER_DESC "USB 2.0 'Enhanced' Host Controller (EHCI) Driver"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) static const char hcd_name [] = "ehci_hcd";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #undef EHCI_URB_TRACE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /* magic numbers that can affect system performance */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define EHCI_TUNE_CERR 3 /* 0-3 qtd retries; 0 == don't stop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define EHCI_TUNE_RL_HS 4 /* nak throttle; see 4.9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define EHCI_TUNE_RL_TT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define EHCI_TUNE_MULT_HS 1 /* 1-3 transactions/uframe; 4.10.3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define EHCI_TUNE_MULT_TT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * Some drivers think it's safe to schedule isochronous transfers more than
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * 256 ms into the future (partly as a result of an old bug in the scheduling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * code). In an attempt to avoid trouble, we will use a minimum scheduling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * length of 512 frames instead of 256.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define EHCI_TUNE_FLS 1 /* (medium) 512-frame schedule */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /* Initial IRQ latency: faster than hw default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) static int log2_irq_thresh = 0; // 0 to 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) module_param (log2_irq_thresh, int, S_IRUGO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) MODULE_PARM_DESC (log2_irq_thresh, "log2 IRQ latency, 1-64 microframes");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /* initial park setting: slower than hw default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) static unsigned park = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) module_param (park, uint, S_IRUGO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) MODULE_PARM_DESC (park, "park setting; 1-3 back-to-back async packets");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /* for flakey hardware, ignore overcurrent indicators */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static bool ignore_oc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) module_param (ignore_oc, bool, S_IRUGO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) MODULE_PARM_DESC (ignore_oc, "ignore bogus hardware overcurrent indications");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define INTR_MASK (STS_IAA | STS_FATAL | STS_PCD | STS_ERR | STS_INT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /*-------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #include "ehci.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #include "pci-quirks.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static void compute_tt_budget(u8 budget_table[EHCI_BANDWIDTH_SIZE],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) struct ehci_tt *tt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * The MosChip MCS9990 controller updates its microframe counter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * a little before the frame counter, and occasionally we will read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * the invalid intermediate value. Avoid problems by checking the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * microframe number (the low-order 3 bits); if they are 0 then
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * re-read the register to get the correct value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static unsigned ehci_moschip_read_frame_index(struct ehci_hcd *ehci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) unsigned uf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) uf = ehci_readl(ehci, &ehci->regs->frame_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) if (unlikely((uf & 7) == 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) uf = ehci_readl(ehci, &ehci->regs->frame_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) return uf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static inline unsigned ehci_read_frame_index(struct ehci_hcd *ehci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) if (ehci->frame_index_bug)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) return ehci_moschip_read_frame_index(ehci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) return ehci_readl(ehci, &ehci->regs->frame_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #include "ehci-dbg.c"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /*-------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * ehci_handshake - spin reading hc until handshake completes or fails
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * @ptr: address of hc register to be read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * @mask: bits to look at in result of read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) * @done: value of those bits when handshake succeeds
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * @usec: timeout in microseconds
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) * Returns negative errno, or zero on success
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) * Success happens when the "mask" bits have the specified value (hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) * handshake done). There are two failure modes: "usec" have passed (major
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) * hardware flakeout), or the register reads as all-ones (hardware removed).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) * That last failure should_only happen in cases like physical cardbus eject
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) * before driver shutdown. But it also seems to be caused by bugs in cardbus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) * bridge shutdown: shutting down the bridge before the devices using it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) int ehci_handshake(struct ehci_hcd *ehci, void __iomem *ptr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) u32 mask, u32 done, int usec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) u32 result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) result = ehci_readl(ehci, ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) if (result == ~(u32)0) /* card removed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) result &= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) if (result == done)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) udelay (1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) usec--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) } while (usec > 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) EXPORT_SYMBOL_GPL(ehci_handshake);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /* check TDI/ARC silicon is in host mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static int tdi_in_host_mode (struct ehci_hcd *ehci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) tmp = ehci_readl(ehci, &ehci->regs->usbmode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) return (tmp & 3) == USBMODE_CM_HC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) * Force HC to halt state from unknown (EHCI spec section 2.3).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) * Must be called with interrupts enabled and the lock not held.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) static int ehci_halt (struct ehci_hcd *ehci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) u32 temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) spin_lock_irq(&ehci->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) /* disable any irqs left enabled by previous code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) ehci_writel(ehci, 0, &ehci->regs->intr_enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) if (ehci_is_TDI(ehci) && !tdi_in_host_mode(ehci)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) spin_unlock_irq(&ehci->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) * This routine gets called during probe before ehci->command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) * has been initialized, so we can't rely on its value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) ehci->command &= ~CMD_RUN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) temp = ehci_readl(ehci, &ehci->regs->command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) temp &= ~(CMD_RUN | CMD_IAAD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) ehci_writel(ehci, temp, &ehci->regs->command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) spin_unlock_irq(&ehci->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) synchronize_irq(ehci_to_hcd(ehci)->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) return ehci_handshake(ehci, &ehci->regs->status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) STS_HALT, STS_HALT, 16 * 125);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) /* put TDI/ARC silicon into EHCI mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) static void tdi_reset (struct ehci_hcd *ehci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) tmp = ehci_readl(ehci, &ehci->regs->usbmode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) tmp |= USBMODE_CM_HC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /* The default byte access to MMR space is LE after
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) * controller reset. Set the required endian mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) * for transfer buffers to match the host microprocessor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) if (ehci_big_endian_mmio(ehci))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) tmp |= USBMODE_BE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) ehci_writel(ehci, tmp, &ehci->regs->usbmode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) * Reset a non-running (STS_HALT == 1) controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) * Must be called with interrupts enabled and the lock not held.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) int ehci_reset(struct ehci_hcd *ehci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) int retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) u32 command = ehci_readl(ehci, &ehci->regs->command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) /* If the EHCI debug controller is active, special care must be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) * taken before and after a host controller reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) if (ehci->debug && !dbgp_reset_prep(ehci_to_hcd(ehci)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) ehci->debug = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) command |= CMD_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) dbg_cmd (ehci, "reset", command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) ehci_writel(ehci, command, &ehci->regs->command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) ehci->rh_state = EHCI_RH_HALTED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) ehci->next_statechange = jiffies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) retval = ehci_handshake(ehci, &ehci->regs->command,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) CMD_RESET, 0, 250 * 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) if (ehci->has_hostpc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) ehci_writel(ehci, USBMODE_EX_HC | USBMODE_EX_VBPS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) &ehci->regs->usbmode_ex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) ehci_writel(ehci, TXFIFO_DEFAULT, &ehci->regs->txfill_tuning);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) if (retval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) if (ehci_is_TDI(ehci))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) tdi_reset (ehci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) if (ehci->debug)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) dbgp_external_startup(ehci_to_hcd(ehci));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) ehci->port_c_suspend = ehci->suspended_ports =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) ehci->resuming_ports = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) EXPORT_SYMBOL_GPL(ehci_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) * Idle the controller (turn off the schedules).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) * Must be called with interrupts enabled and the lock not held.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) static void ehci_quiesce (struct ehci_hcd *ehci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) u32 temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) if (ehci->rh_state != EHCI_RH_RUNNING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) /* wait for any schedule enables/disables to take effect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) temp = (ehci->command << 10) & (STS_ASS | STS_PSS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) ehci_handshake(ehci, &ehci->regs->status, STS_ASS | STS_PSS, temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 16 * 125);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) /* then disable anything that's still active */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) spin_lock_irq(&ehci->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) ehci->command &= ~(CMD_ASE | CMD_PSE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) ehci_writel(ehci, ehci->command, &ehci->regs->command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) spin_unlock_irq(&ehci->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) /* hardware can take 16 microframes to turn off ... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) ehci_handshake(ehci, &ehci->regs->status, STS_ASS | STS_PSS, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 16 * 125);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) /*-------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) static void end_iaa_cycle(struct ehci_hcd *ehci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) static void end_unlink_async(struct ehci_hcd *ehci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) static void unlink_empty_async(struct ehci_hcd *ehci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) static void ehci_work(struct ehci_hcd *ehci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) static void start_unlink_intr(struct ehci_hcd *ehci, struct ehci_qh *qh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) static void end_unlink_intr(struct ehci_hcd *ehci, struct ehci_qh *qh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) static int ehci_port_power(struct ehci_hcd *ehci, int portnum, bool enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #include "ehci-timer.c"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #include "ehci-hub.c"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #include "ehci-mem.c"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #include "ehci-q.c"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #include "ehci-sched.c"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #include "ehci-sysfs.c"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) /*-------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) /* On some systems, leaving remote wakeup enabled prevents system shutdown.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) * The firmware seems to think that powering off is a wakeup event!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) * This routine turns off remote wakeup and everything else, on all ports.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) static void ehci_turn_off_all_ports(struct ehci_hcd *ehci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) int port = HCS_N_PORTS(ehci->hcs_params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) while (port--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) spin_unlock_irq(&ehci->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) ehci_port_power(ehci, port, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) spin_lock_irq(&ehci->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) ehci_writel(ehci, PORT_RWC_BITS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) &ehci->regs->port_status[port]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) * Halt HC, turn off all ports, and let the BIOS use the companion controllers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) * Must be called with interrupts enabled and the lock not held.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) static void ehci_silence_controller(struct ehci_hcd *ehci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) ehci_halt(ehci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) spin_lock_irq(&ehci->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) ehci->rh_state = EHCI_RH_HALTED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) ehci_turn_off_all_ports(ehci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) /* make BIOS/etc use companion controller during reboot */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) ehci_writel(ehci, 0, &ehci->regs->configured_flag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) /* unblock posted writes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) ehci_readl(ehci, &ehci->regs->configured_flag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) spin_unlock_irq(&ehci->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) /* ehci_shutdown kick in for silicon on any bus (not just pci, etc).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) * This forcibly disables dma and IRQs, helping kexec and other cases
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) * where the next system software may expect clean state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) static void ehci_shutdown(struct usb_hcd *hcd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) struct ehci_hcd *ehci = hcd_to_ehci(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) * Protect the system from crashing at system shutdown in cases where
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) * usb host is not added yet from OTG controller driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) * As ehci_setup() not done yet, so stop accessing registers or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) * variables initialized in ehci_setup()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) if (!ehci->sbrn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) spin_lock_irq(&ehci->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) ehci->shutdown = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) ehci->rh_state = EHCI_RH_STOPPING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) ehci->enabled_hrtimer_events = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) spin_unlock_irq(&ehci->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) ehci_silence_controller(ehci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) hrtimer_cancel(&ehci->hrtimer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) /*-------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) * ehci_work is called from some interrupts, timers, and so on.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) * it calls driver completion functions, after dropping ehci->lock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) static void ehci_work (struct ehci_hcd *ehci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) /* another CPU may drop ehci->lock during a schedule scan while
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) * it reports urb completions. this flag guards against bogus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) * attempts at re-entrant schedule scanning.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) if (ehci->scanning) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) ehci->need_rescan = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) ehci->scanning = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) rescan:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) ehci->need_rescan = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) if (ehci->async_count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) scan_async(ehci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) if (ehci->intr_count > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) scan_intr(ehci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) if (ehci->isoc_count > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) scan_isoc(ehci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) if (ehci->need_rescan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) goto rescan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) ehci->scanning = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) /* the IO watchdog guards against hardware or driver bugs that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) * misplace IRQs, and should let us run completely without IRQs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) * such lossage has been observed on both VT6202 and VT8235.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) turn_on_io_watchdog(ehci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) * Called when the ehci_hcd module is removed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) static void ehci_stop (struct usb_hcd *hcd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) struct ehci_hcd *ehci = hcd_to_ehci (hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) ehci_dbg (ehci, "stop\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) /* no more interrupts ... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) spin_lock_irq(&ehci->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) ehci->enabled_hrtimer_events = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) spin_unlock_irq(&ehci->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) ehci_quiesce(ehci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) ehci_silence_controller(ehci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) ehci_reset (ehci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) hrtimer_cancel(&ehci->hrtimer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) remove_sysfs_files(ehci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) remove_debug_files (ehci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) /* root hub is shut down separately (first, when possible) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) spin_lock_irq (&ehci->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) end_free_itds(ehci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) spin_unlock_irq (&ehci->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) ehci_mem_cleanup (ehci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) if (ehci->amd_pll_fix == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) usb_amd_dev_put();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) dbg_status (ehci, "ehci_stop completed",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) ehci_readl(ehci, &ehci->regs->status));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) /* one-time init, only for memory state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) static int ehci_init(struct usb_hcd *hcd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) struct ehci_hcd *ehci = hcd_to_ehci(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) u32 temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) int retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) u32 hcc_params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) struct ehci_qh_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) spin_lock_init(&ehci->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) * keep io watchdog by default, those good HCDs could turn off it later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) ehci->need_io_watchdog = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) hrtimer_init(&ehci->hrtimer, CLOCK_MONOTONIC, HRTIMER_MODE_ABS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) ehci->hrtimer.function = ehci_hrtimer_func;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) ehci->next_hrtimer_event = EHCI_HRTIMER_NO_EVENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) hcc_params = ehci_readl(ehci, &ehci->caps->hcc_params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) * by default set standard 80% (== 100 usec/uframe) max periodic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) * bandwidth as required by USB 2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) ehci->uframe_periodic_max = 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) * hw default: 1K periodic list heads, one per frame.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) * periodic_size can shrink by USBCMD update if hcc_params allows.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) ehci->periodic_size = DEFAULT_I_TDPS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) INIT_LIST_HEAD(&ehci->async_unlink);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) INIT_LIST_HEAD(&ehci->async_idle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) INIT_LIST_HEAD(&ehci->intr_unlink_wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) INIT_LIST_HEAD(&ehci->intr_unlink);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) INIT_LIST_HEAD(&ehci->intr_qh_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) INIT_LIST_HEAD(&ehci->cached_itd_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) INIT_LIST_HEAD(&ehci->cached_sitd_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) INIT_LIST_HEAD(&ehci->tt_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) if (HCC_PGM_FRAMELISTLEN(hcc_params)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) /* periodic schedule size can be smaller than default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) switch (EHCI_TUNE_FLS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) case 0: ehci->periodic_size = 1024; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) case 1: ehci->periodic_size = 512; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) case 2: ehci->periodic_size = 256; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) default: BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) if ((retval = ehci_mem_init(ehci, GFP_KERNEL)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) /* controllers may cache some of the periodic schedule ... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) if (HCC_ISOC_CACHE(hcc_params)) // full frame cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) ehci->i_thresh = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) else // N microframes cached
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) ehci->i_thresh = 2 + HCC_ISOC_THRES(hcc_params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) * dedicate a qh for the async ring head, since we couldn't unlink
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) * a 'real' qh without stopping the async schedule [4.8]. use it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) * as the 'reclamation list head' too.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) * its dummy is used in hw_alt_next of many tds, to prevent the qh
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) * from automatically advancing to the next td after short reads.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) ehci->async->qh_next.qh = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) hw = ehci->async->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) hw->hw_next = QH_NEXT(ehci, ehci->async->qh_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) hw->hw_info1 = cpu_to_hc32(ehci, QH_HEAD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) #if defined(CONFIG_PPC_PS3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) hw->hw_info1 |= cpu_to_hc32(ehci, QH_INACTIVATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) hw->hw_token = cpu_to_hc32(ehci, QTD_STS_HALT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) hw->hw_qtd_next = EHCI_LIST_END(ehci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) ehci->async->qh_state = QH_STATE_LINKED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) hw->hw_alt_next = QTD_NEXT(ehci, ehci->async->dummy->qtd_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) /* clear interrupt enables, set irq latency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) if (log2_irq_thresh < 0 || log2_irq_thresh > 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) log2_irq_thresh = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) temp = 1 << (16 + log2_irq_thresh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) if (HCC_PER_PORT_CHANGE_EVENT(hcc_params)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) ehci->has_ppcd = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) ehci_dbg(ehci, "enable per-port change event\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) temp |= CMD_PPCEE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) if (HCC_CANPARK(hcc_params)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) /* HW default park == 3, on hardware that supports it (like
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) * NVidia and ALI silicon), maximizes throughput on the async
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) * schedule by avoiding QH fetches between transfers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) * With fast usb storage devices and NForce2, "park" seems to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) * make problems: throughput reduction (!), data errors...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) if (park) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) park = min(park, (unsigned) 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) temp |= CMD_PARK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) temp |= park << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) ehci_dbg(ehci, "park %d\n", park);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) if (HCC_PGM_FRAMELISTLEN(hcc_params)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) /* periodic schedule size can be smaller than default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) temp &= ~(3 << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) temp |= (EHCI_TUNE_FLS << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) ehci->command = temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) /* Accept arbitrarily long scatter-gather lists */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) if (!hcd->localmem_pool)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) hcd->self.sg_tablesize = ~0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) /* Prepare for unlinking active QHs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) ehci->old_current = ~0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) /* start HC running; it's halted, ehci_init() has been run (once) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) static int ehci_run (struct usb_hcd *hcd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) struct ehci_hcd *ehci = hcd_to_ehci (hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) u32 temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) u32 hcc_params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) hcd->uses_new_polling = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) /* EHCI spec section 4.1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) ehci_writel(ehci, ehci->periodic_dma, &ehci->regs->frame_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) ehci_writel(ehci, (u32)ehci->async->qh_dma, &ehci->regs->async_next);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) * hcc_params controls whether ehci->regs->segment must (!!!)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) * be used; it constrains QH/ITD/SITD and QTD locations.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) * dma_pool consistent memory always uses segment zero.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) * streaming mappings for I/O buffers, like pci_map_single(),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) * can return segments above 4GB, if the device allows.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) * NOTE: the dma mask is visible through dev->dma_mask, so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) * drivers can pass this info along ... like NETIF_F_HIGHDMA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) * Scsi_Host.highmem_io, and so forth. It's readonly to all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) * host side drivers though.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) hcc_params = ehci_readl(ehci, &ehci->caps->hcc_params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) if (HCC_64BIT_ADDR(hcc_params)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) ehci_writel(ehci, 0, &ehci->regs->segment);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) // this is deeply broken on almost all architectures
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) if (!dma_set_mask(hcd->self.controller, DMA_BIT_MASK(64)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) ehci_info(ehci, "enabled 64bit DMA\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) // Philips, Intel, and maybe others need CMD_RUN before the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) // root hub will detect new devices (why?); NEC doesn't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) ehci->command &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) ehci->command |= CMD_RUN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) ehci_writel(ehci, ehci->command, &ehci->regs->command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) dbg_cmd (ehci, "init", ehci->command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) * Start, enabling full USB 2.0 functionality ... usb 1.1 devices
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) * are explicitly handed to companion controller(s), so no TT is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) * involved with the root hub. (Except where one is integrated,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) * and there's no companion controller unless maybe for USB OTG.)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) * Turning on the CF flag will transfer ownership of all ports
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) * from the companions to the EHCI controller. If any of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) * companions are in the middle of a port reset at the time, it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) * could cause trouble. Write-locking ehci_cf_port_reset_rwsem
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) * guarantees that no resets are in progress. After we set CF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) * a short delay lets the hardware catch up; new resets shouldn't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) * be started before the port switching actions could complete.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) down_write(&ehci_cf_port_reset_rwsem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) ehci->rh_state = EHCI_RH_RUNNING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) ehci_writel(ehci, FLAG_CF, &ehci->regs->configured_flag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) /* Wait until HC become operational */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) ehci_readl(ehci, &ehci->regs->command); /* unblock posted writes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) msleep(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) /* For Aspeed, STS_HALT also depends on ASS/PSS status.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) * Check CMD_RUN instead.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) if (ehci->is_aspeed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) rc = ehci_handshake(ehci, &ehci->regs->command, CMD_RUN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) 1, 100 * 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) rc = ehci_handshake(ehci, &ehci->regs->status, STS_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) 0, 100 * 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) up_write(&ehci_cf_port_reset_rwsem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) ehci_err(ehci, "USB %x.%x, controller refused to start: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) ((ehci->sbrn & 0xf0)>>4), (ehci->sbrn & 0x0f), rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) ehci->last_periodic_enable = ktime_get_real();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) temp = HC_VERSION(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) ehci_info (ehci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) "USB %x.%x started, EHCI %x.%02x%s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) ((ehci->sbrn & 0xf0)>>4), (ehci->sbrn & 0x0f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) temp >> 8, temp & 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) ignore_oc ? ", overcurrent ignored" : "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) ehci_writel(ehci, INTR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) &ehci->regs->intr_enable); /* Turn On Interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) /* GRR this is run-once init(), being done every time the HC starts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) * So long as they're part of class devices, we can't do it init()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) * since the class device isn't created that early.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) create_debug_files(ehci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) create_sysfs_files(ehci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) int ehci_setup(struct usb_hcd *hcd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) struct ehci_hcd *ehci = hcd_to_ehci(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) int retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) ehci->regs = (void __iomem *)ehci->caps +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) HC_LENGTH(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) dbg_hcs_params(ehci, "reset");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) dbg_hcc_params(ehci, "reset");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) /* cache this readonly data; minimize chip reads */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) ehci->sbrn = HCD_USB2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) /* data structure init */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) retval = ehci_init(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) if (retval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) retval = ehci_halt(ehci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) if (retval) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) ehci_mem_cleanup(ehci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) ehci_reset(ehci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) EXPORT_SYMBOL_GPL(ehci_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) /*-------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) static irqreturn_t ehci_irq (struct usb_hcd *hcd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) struct ehci_hcd *ehci = hcd_to_ehci (hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) u32 status, current_status, masked_status, pcd_status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) u32 cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) int bh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) * For threadirqs option we use spin_lock_irqsave() variant to prevent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) * deadlock with ehci hrtimer callback, because hrtimer callbacks run
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) * in interrupt context even when threadirqs is specified. We can go
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) * back to spin_lock() variant when hrtimer callbacks become threaded.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) spin_lock_irqsave(&ehci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) current_status = ehci_readl(ehci, &ehci->regs->status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) restart:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) /* e.g. cardbus physical eject */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) if (current_status == ~(u32) 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) ehci_dbg (ehci, "device removed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) goto dead;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) status |= current_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) * We don't use STS_FLR, but some controllers don't like it to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) * remain on, so mask it out along with the other status bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) masked_status = current_status & (INTR_MASK | STS_FLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) /* Shared IRQ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) if (!masked_status || unlikely(ehci->rh_state == EHCI_RH_HALTED)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) spin_unlock_irqrestore(&ehci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) /* clear (just) interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) ehci_writel(ehci, masked_status, &ehci->regs->status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) /* For edge interrupts, don't race with an interrupt bit being raised */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) current_status = ehci_readl(ehci, &ehci->regs->status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) if (current_status & INTR_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) goto restart;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) cmd = ehci_readl(ehci, &ehci->regs->command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) bh = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) /* normal [4.15.1.2] or error [4.15.1.1] completion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) if (likely ((status & (STS_INT|STS_ERR)) != 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) if (likely ((status & STS_ERR) == 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) INCR(ehci->stats.normal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) INCR(ehci->stats.error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) bh = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) /* complete the unlinking of some qh [4.15.2.3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) if (status & STS_IAA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) /* Turn off the IAA watchdog */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) ehci->enabled_hrtimer_events &= ~BIT(EHCI_HRTIMER_IAA_WATCHDOG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) * Mild optimization: Allow another IAAD to reset the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) * hrtimer, if one occurs before the next expiration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) * In theory we could always cancel the hrtimer, but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) * tests show that about half the time it will be reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) * for some other event anyway.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) if (ehci->next_hrtimer_event == EHCI_HRTIMER_IAA_WATCHDOG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) ++ehci->next_hrtimer_event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) /* guard against (alleged) silicon errata */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) if (cmd & CMD_IAAD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) ehci_dbg(ehci, "IAA with IAAD still set?\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) if (ehci->iaa_in_progress)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) INCR(ehci->stats.iaa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) end_iaa_cycle(ehci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) /* remote wakeup [4.3.1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) if (status & STS_PCD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) unsigned i = HCS_N_PORTS (ehci->hcs_params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) u32 ppcd = ~0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) /* kick root hub later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) pcd_status = status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) /* resume root hub? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) if (ehci->rh_state == EHCI_RH_SUSPENDED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) usb_hcd_resume_root_hub(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) /* get per-port change detect bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) if (ehci->has_ppcd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) ppcd = status >> 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) while (i--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) int pstatus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) /* leverage per-port change bits feature */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) if (!(ppcd & (1 << i)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) pstatus = ehci_readl(ehci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) &ehci->regs->port_status[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) if (pstatus & PORT_OWNER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) if (!(test_bit(i, &ehci->suspended_ports) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) ((pstatus & PORT_RESUME) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) !(pstatus & PORT_SUSPEND)) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) (pstatus & PORT_PE) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) ehci->reset_done[i] == 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) /* start USB_RESUME_TIMEOUT msec resume signaling from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) * this port, and make hub_wq collect
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) * PORT_STAT_C_SUSPEND to stop that signaling.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) ehci->reset_done[i] = jiffies +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) msecs_to_jiffies(USB_RESUME_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) set_bit(i, &ehci->resuming_ports);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) ehci_dbg (ehci, "port %d remote wakeup\n", i + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) usb_hcd_start_port_resume(&hcd->self, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) mod_timer(&hcd->rh_timer, ehci->reset_done[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) /* PCI errors [4.15.2.4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) if (unlikely ((status & STS_FATAL) != 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) ehci_err(ehci, "fatal error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) dbg_cmd(ehci, "fatal", cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) dbg_status(ehci, "fatal", status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) dead:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) usb_hc_died(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) /* Don't let the controller do anything more */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) ehci->shutdown = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) ehci->rh_state = EHCI_RH_STOPPING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) ehci->command &= ~(CMD_RUN | CMD_ASE | CMD_PSE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) ehci_writel(ehci, ehci->command, &ehci->regs->command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) ehci_writel(ehci, 0, &ehci->regs->intr_enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) ehci_handle_controller_death(ehci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) /* Handle completions when the controller stops */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) bh = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) if (bh)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) ehci_work (ehci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) spin_unlock_irqrestore(&ehci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) if (pcd_status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) usb_hcd_poll_rh_status(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) /*-------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) * non-error returns are a promise to giveback() the urb later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) * we drop ownership so next owner (or urb unlink) can get it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) * urb + dev is in hcd.self.controller.urb_list
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) * we're queueing TDs onto software and hardware lists
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) * hcd-specific init for hcpriv hasn't been done yet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) * NOTE: control, bulk, and interrupt share the same code to append TDs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) * to a (possibly active) QH, and the same QH scanning code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) static int ehci_urb_enqueue (
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) struct usb_hcd *hcd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) struct urb *urb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) gfp_t mem_flags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) struct ehci_hcd *ehci = hcd_to_ehci (hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) struct list_head qtd_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) INIT_LIST_HEAD (&qtd_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) switch (usb_pipetype (urb->pipe)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) case PIPE_CONTROL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) /* qh_completions() code doesn't handle all the fault cases
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) * in multi-TD control transfers. Even 1KB is rare anyway.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) if (urb->transfer_buffer_length > (16 * 1024))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) return -EMSGSIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) /* FALLTHROUGH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) /* case PIPE_BULK: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) if (!qh_urb_transaction (ehci, urb, &qtd_list, mem_flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) return submit_async(ehci, urb, &qtd_list, mem_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) case PIPE_INTERRUPT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) if (!qh_urb_transaction (ehci, urb, &qtd_list, mem_flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) return intr_submit(ehci, urb, &qtd_list, mem_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) case PIPE_ISOCHRONOUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) if (urb->dev->speed == USB_SPEED_HIGH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) return itd_submit (ehci, urb, mem_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) return sitd_submit (ehci, urb, mem_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) /* remove from hardware lists
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) * completions normally happen asynchronously
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) static int ehci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) struct ehci_hcd *ehci = hcd_to_ehci (hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) struct ehci_qh *qh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) spin_lock_irqsave (&ehci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) rc = usb_hcd_check_unlink_urb(hcd, urb, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) * We don't expedite dequeue for isochronous URBs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) * Just wait until they complete normally or their
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) * time slot expires.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) qh = (struct ehci_qh *) urb->hcpriv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) qh->unlink_reason |= QH_UNLINK_REQUESTED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) switch (qh->qh_state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) case QH_STATE_LINKED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) if (usb_pipetype(urb->pipe) == PIPE_INTERRUPT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) start_unlink_intr(ehci, qh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) start_unlink_async(ehci, qh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) case QH_STATE_COMPLETING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) qh->dequeue_during_giveback = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) case QH_STATE_UNLINK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) case QH_STATE_UNLINK_WAIT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) /* already started */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) case QH_STATE_IDLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) /* QH might be waiting for a Clear-TT-Buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) qh_completions(ehci, qh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) spin_unlock_irqrestore (&ehci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) /*-------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) // bulk qh holds the data toggle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) ehci_endpoint_disable (struct usb_hcd *hcd, struct usb_host_endpoint *ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) struct ehci_hcd *ehci = hcd_to_ehci (hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) struct ehci_qh *qh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) /* ASSERT: any requests/urbs are being unlinked */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) /* ASSERT: nobody can be submitting urbs for this any more */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) rescan:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) spin_lock_irqsave (&ehci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) qh = ep->hcpriv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) if (!qh)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) /* endpoints can be iso streams. for now, we don't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) * accelerate iso completions ... so spin a while.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) if (qh->hw == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) struct ehci_iso_stream *stream = ep->hcpriv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) if (!list_empty(&stream->td_list))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) goto idle_timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) /* BUG_ON(!list_empty(&stream->free_list)); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) reserve_release_iso_bandwidth(ehci, stream, -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) kfree(stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) qh->unlink_reason |= QH_UNLINK_REQUESTED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) switch (qh->qh_state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) case QH_STATE_LINKED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) if (list_empty(&qh->qtd_list))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) qh->unlink_reason |= QH_UNLINK_QUEUE_EMPTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) WARN_ON(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) if (usb_endpoint_type(&ep->desc) != USB_ENDPOINT_XFER_INT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) start_unlink_async(ehci, qh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) start_unlink_intr(ehci, qh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) case QH_STATE_COMPLETING: /* already in unlinking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) case QH_STATE_UNLINK: /* wait for hw to finish? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) case QH_STATE_UNLINK_WAIT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) idle_timeout:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) spin_unlock_irqrestore (&ehci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) schedule_timeout_uninterruptible(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) goto rescan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) case QH_STATE_IDLE: /* fully unlinked */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) if (qh->clearing_tt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) goto idle_timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) if (list_empty (&qh->qtd_list)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) if (qh->ps.bw_uperiod)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) reserve_release_intr_bandwidth(ehci, qh, -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) qh_destroy(ehci, qh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) /* caller was supposed to have unlinked any requests;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) * that's not our job. just leak this memory.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) ehci_err (ehci, "qh %p (#%02x) state %d%s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) qh, ep->desc.bEndpointAddress, qh->qh_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) list_empty (&qh->qtd_list) ? "" : "(has tds)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) ep->hcpriv = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) spin_unlock_irqrestore (&ehci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) ehci_endpoint_reset(struct usb_hcd *hcd, struct usb_host_endpoint *ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) struct ehci_hcd *ehci = hcd_to_ehci(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) struct ehci_qh *qh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) int eptype = usb_endpoint_type(&ep->desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) int epnum = usb_endpoint_num(&ep->desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) int is_out = usb_endpoint_dir_out(&ep->desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) if (eptype != USB_ENDPOINT_XFER_BULK && eptype != USB_ENDPOINT_XFER_INT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) spin_lock_irqsave(&ehci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) qh = ep->hcpriv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) /* For Bulk and Interrupt endpoints we maintain the toggle state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) * in the hardware; the toggle bits in udev aren't used at all.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) * When an endpoint is reset by usb_clear_halt() we must reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) * the toggle bit in the QH.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) if (qh) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) if (!list_empty(&qh->qtd_list)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) WARN_ONCE(1, "clear_halt for a busy endpoint\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) /* The toggle value in the QH can't be updated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) * while the QH is active. Unlink it now;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) * re-linking will call qh_refresh().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) usb_settoggle(qh->ps.udev, epnum, is_out, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) qh->unlink_reason |= QH_UNLINK_REQUESTED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) if (eptype == USB_ENDPOINT_XFER_BULK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) start_unlink_async(ehci, qh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) start_unlink_intr(ehci, qh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) spin_unlock_irqrestore(&ehci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) static int ehci_get_frame (struct usb_hcd *hcd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) struct ehci_hcd *ehci = hcd_to_ehci (hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) return (ehci_read_frame_index(ehci) >> 3) % ehci->periodic_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) /*-------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) /* Device addition and removal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) static void ehci_remove_device(struct usb_hcd *hcd, struct usb_device *udev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) struct ehci_hcd *ehci = hcd_to_ehci(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) spin_lock_irq(&ehci->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) drop_tt(udev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) spin_unlock_irq(&ehci->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) /*-------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) /* suspend/resume, section 4.3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) /* These routines handle the generic parts of controller suspend/resume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) int ehci_suspend(struct usb_hcd *hcd, bool do_wakeup)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) struct ehci_hcd *ehci = hcd_to_ehci(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) if (time_before(jiffies, ehci->next_statechange))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) msleep(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) * Root hub was already suspended. Disable IRQ emission and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) * mark HW unaccessible. The PM and USB cores make sure that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) * the root hub is either suspended or stopped.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) ehci_prepare_ports_for_controller_suspend(ehci, do_wakeup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) spin_lock_irq(&ehci->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) ehci_writel(ehci, 0, &ehci->regs->intr_enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) (void) ehci_readl(ehci, &ehci->regs->intr_enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) spin_unlock_irq(&ehci->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) synchronize_irq(hcd->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) /* Check for race with a wakeup request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) if (do_wakeup && HCD_WAKEUP_PENDING(hcd)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) ehci_resume(hcd, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) EXPORT_SYMBOL_GPL(ehci_suspend);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) /* Returns 0 if power was preserved, 1 if power was lost */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) int ehci_resume(struct usb_hcd *hcd, bool force_reset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) struct ehci_hcd *ehci = hcd_to_ehci(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) if (time_before(jiffies, ehci->next_statechange))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) msleep(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) /* Mark hardware accessible again as we are back to full power by now */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) if (ehci->shutdown)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) return 0; /* Controller is dead */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) * If CF is still set and reset isn't forced
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) * then we maintained suspend power.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) * Just undo the effect of ehci_suspend().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) if (ehci_readl(ehci, &ehci->regs->configured_flag) == FLAG_CF &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) !force_reset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) int mask = INTR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) ehci_prepare_ports_for_controller_resume(ehci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) spin_lock_irq(&ehci->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) if (ehci->shutdown)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) goto skip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) if (!hcd->self.root_hub->do_remote_wakeup)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) mask &= ~STS_PCD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) ehci_writel(ehci, mask, &ehci->regs->intr_enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) ehci_readl(ehci, &ehci->regs->intr_enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) skip:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) spin_unlock_irq(&ehci->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) * Else reset, to cope with power loss or resume from hibernation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) * having let the firmware kick in during reboot.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) usb_root_hub_lost_power(hcd->self.root_hub);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) (void) ehci_halt(ehci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) (void) ehci_reset(ehci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) spin_lock_irq(&ehci->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) if (ehci->shutdown)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) goto skip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) ehci_writel(ehci, ehci->command, &ehci->regs->command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) ehci_writel(ehci, FLAG_CF, &ehci->regs->configured_flag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) ehci_readl(ehci, &ehci->regs->command); /* unblock posted writes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) ehci->rh_state = EHCI_RH_SUSPENDED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) spin_unlock_irq(&ehci->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) EXPORT_SYMBOL_GPL(ehci_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) /*-------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) * Generic structure: This gets copied for platform drivers so that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) * individual entries can be overridden as needed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) static const struct hc_driver ehci_hc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) .description = hcd_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) .product_desc = "EHCI Host Controller",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) .hcd_priv_size = sizeof(struct ehci_hcd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) * generic hardware linkage
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) .irq = ehci_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) .flags = HCD_MEMORY | HCD_DMA | HCD_USB2 | HCD_BH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) * basic lifecycle operations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) .reset = ehci_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) .start = ehci_run,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) .stop = ehci_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) .shutdown = ehci_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) * managing i/o requests and associated device resources
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) .urb_enqueue = ehci_urb_enqueue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) .urb_dequeue = ehci_urb_dequeue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) .endpoint_disable = ehci_endpoint_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) .endpoint_reset = ehci_endpoint_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) .clear_tt_buffer_complete = ehci_clear_tt_buffer_complete,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) * scheduling support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) .get_frame_number = ehci_get_frame,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) * root hub support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) .hub_status_data = ehci_hub_status_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) .hub_control = ehci_hub_control,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) .bus_suspend = ehci_bus_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) .bus_resume = ehci_bus_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) .relinquish_port = ehci_relinquish_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) .port_handed_over = ehci_port_handed_over,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) .get_resuming_ports = ehci_get_resuming_ports,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) * device support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) .free_dev = ehci_remove_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) void ehci_init_driver(struct hc_driver *drv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) const struct ehci_driver_overrides *over)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) /* Copy the generic table to drv and then apply the overrides */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) *drv = ehci_hc_driver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) if (over) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) drv->hcd_priv_size += over->extra_priv_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) if (over->reset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) drv->reset = over->reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) if (over->port_power)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) drv->port_power = over->port_power;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) EXPORT_SYMBOL_GPL(ehci_init_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) /*-------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) MODULE_DESCRIPTION(DRIVER_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) MODULE_AUTHOR (DRIVER_AUTHOR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) MODULE_LICENSE ("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) #ifdef CONFIG_USB_EHCI_SH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) #include "ehci-sh.c"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) #define PLATFORM_DRIVER ehci_hcd_sh_driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) #ifdef CONFIG_PPC_PS3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) #include "ehci-ps3.c"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) #define PS3_SYSTEM_BUS_DRIVER ps3_ehci_driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) #ifdef CONFIG_USB_EHCI_HCD_PPC_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) #include "ehci-ppc-of.c"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) #define OF_PLATFORM_DRIVER ehci_hcd_ppc_of_driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) #ifdef CONFIG_XPS_USB_HCD_XILINX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) #include "ehci-xilinx-of.c"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) #define XILINX_OF_PLATFORM_DRIVER ehci_hcd_xilinx_of_driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) #ifdef CONFIG_USB_EHCI_HCD_PMC_MSP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) #include "ehci-pmcmsp.c"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) #define PLATFORM_DRIVER ehci_hcd_msp_driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) #ifdef CONFIG_SPARC_LEON
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) #include "ehci-grlib.c"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) #define PLATFORM_DRIVER ehci_grlib_driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) static int __init ehci_hcd_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) int retval = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) if (usb_disabled())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) printk(KERN_INFO "%s: " DRIVER_DESC "\n", hcd_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) set_bit(USB_EHCI_LOADED, &usb_hcds_loaded);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) if (test_bit(USB_UHCI_LOADED, &usb_hcds_loaded) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) test_bit(USB_OHCI_LOADED, &usb_hcds_loaded))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) printk(KERN_WARNING "Warning! ehci_hcd should always be loaded"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) " before uhci_hcd and ohci_hcd, not after\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) pr_debug("%s: block sizes: qh %zd qtd %zd itd %zd sitd %zd\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) hcd_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) sizeof(struct ehci_qh), sizeof(struct ehci_qtd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) sizeof(struct ehci_itd), sizeof(struct ehci_sitd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) #ifdef CONFIG_DYNAMIC_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) ehci_debug_root = debugfs_create_dir("ehci", usb_debug_root);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) #ifdef PLATFORM_DRIVER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) retval = platform_driver_register(&PLATFORM_DRIVER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) if (retval < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) goto clean0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) #ifdef PS3_SYSTEM_BUS_DRIVER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) retval = ps3_ehci_driver_register(&PS3_SYSTEM_BUS_DRIVER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) if (retval < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) goto clean2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) #ifdef OF_PLATFORM_DRIVER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) retval = platform_driver_register(&OF_PLATFORM_DRIVER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) if (retval < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) goto clean3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) #ifdef XILINX_OF_PLATFORM_DRIVER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) retval = platform_driver_register(&XILINX_OF_PLATFORM_DRIVER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) if (retval < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) goto clean4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) #ifdef XILINX_OF_PLATFORM_DRIVER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) /* platform_driver_unregister(&XILINX_OF_PLATFORM_DRIVER); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) clean4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) #ifdef OF_PLATFORM_DRIVER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) platform_driver_unregister(&OF_PLATFORM_DRIVER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) clean3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) #ifdef PS3_SYSTEM_BUS_DRIVER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) ps3_ehci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) clean2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) #ifdef PLATFORM_DRIVER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) platform_driver_unregister(&PLATFORM_DRIVER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) clean0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) #ifdef CONFIG_DYNAMIC_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) debugfs_remove(ehci_debug_root);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) ehci_debug_root = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) clear_bit(USB_EHCI_LOADED, &usb_hcds_loaded);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) module_init(ehci_hcd_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) static void __exit ehci_hcd_cleanup(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) #ifdef XILINX_OF_PLATFORM_DRIVER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) platform_driver_unregister(&XILINX_OF_PLATFORM_DRIVER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) #ifdef OF_PLATFORM_DRIVER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) platform_driver_unregister(&OF_PLATFORM_DRIVER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) #ifdef PLATFORM_DRIVER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) platform_driver_unregister(&PLATFORM_DRIVER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) #ifdef PS3_SYSTEM_BUS_DRIVER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) ps3_ehci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) #ifdef CONFIG_DYNAMIC_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) debugfs_remove(ehci_debug_root);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) clear_bit(USB_EHCI_LOADED, &usb_hcds_loaded);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) module_exit(ehci_hcd_cleanup);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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