Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0+ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /* Copyright (C) 2005-2010,2012 Freescale Semiconductor, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright (c) 2005 MontaVista Software
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) #ifndef _EHCI_FSL_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #define _EHCI_FSL_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) /* offsets for the non-ehci registers in the FSL SOC USB controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #define FSL_SOC_USB_SBUSCFG	0x90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define SBUSCFG_INCR8		0x02	/* INCR8, specified */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define FSL_SOC_USB_ULPIVP	0x170
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define FSL_SOC_USB_PORTSC1	0x184
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define PORT_PTS_MSK		(3<<30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define PORT_PTS_UTMI		(0<<30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define PORT_PTS_ULPI		(2<<30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define	PORT_PTS_SERIAL		(3<<30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define PORT_PTS_PTW		(1<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define FSL_SOC_USB_PORTSC2	0x188
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define FSL_SOC_USB_USBMODE	0x1a8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define USBMODE_CM_MASK		(3 << 0)	/* controller mode mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define USBMODE_CM_HOST		(3 << 0)	/* controller mode: host */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define USBMODE_ES		(1 << 2)	/* (Big) Endian Select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define FSL_SOC_USB_USBGENCTRL	0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define USBGENCTRL_PPP		(1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define USBGENCTRL_PFP		(1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define FSL_SOC_USB_ISIPHYCTRL	0x204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define ISIPHYCTRL_PXE		(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define ISIPHYCTRL_PHYE		(1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define FSL_SOC_USB_SNOOP1	0x400	/* NOTE: big-endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define FSL_SOC_USB_SNOOP2	0x404	/* NOTE: big-endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define FSL_SOC_USB_AGECNTTHRSH	0x408	/* NOTE: big-endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define FSL_SOC_USB_PRICTRL	0x40c	/* NOTE: big-endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define FSL_SOC_USB_SICTRL	0x410	/* NOTE: big-endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define FSL_SOC_USB_CTRL	0x500	/* NOTE: big-endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define CTRL_UTMI_PHY_EN	(1<<9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define CTRL_PHY_CLK_VALID	(1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define SNOOP_SIZE_2GB		0x1e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /* control Register Bit Masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define CONTROL_REGISTER_W1C_MASK       0x00020000  /* W1C: PHY_CLK_VALID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define ULPI_INT_EN             (1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define WU_INT_EN               (1<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define USB_CTRL_USB_EN         (1<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define LINE_STATE_FILTER__EN   (1<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define KEEP_OTG_ON             (1<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define OTG_PORT                (1<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define PLL_RESET               (1<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define UTMI_PHY_EN             (1<<9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define ULPI_PHY_CLK_SEL        (1<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define PHY_CLK_VALID		(1<<17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* Retry count for checking UTMI PHY CLK validity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define UTMI_PHY_CLK_VALID_CHK_RETRY 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #endif				/* _EHCI_FSL_H */