^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright 2005-2009 MontaVista Software, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright 2008,2012,2015 Freescale Semiconductor, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Ported to 834x by Randy Vinson <rvinson@mvista.com> using code provided
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * by Hunter Wu.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Power Management support by Dave Liu <daveliu@freescale.com>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Jerry Huang <Chang-Ming.Huang@freescale.com> and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Anton Vorontsov <avorontsov@ru.mvista.com>.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/pm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/usb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/usb/ehci_def.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/usb/hcd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/usb/otg.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/fsl_devices.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include "ehci.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include "ehci-fsl.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define DRIVER_DESC "Freescale EHCI Host controller driver"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define DRV_NAME "ehci-fsl"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) static struct hc_driver __read_mostly fsl_ehci_hc_driver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /* configure so an HC device and id are always provided */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /* always called with process context; sleeping is OK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * fsl_ehci_drv_probe - initialize FSL-based HCDs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * @pdev: USB Host Controller being probed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * Context: !in_interrupt()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * Allocates basic resources for this USB host controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) static int fsl_ehci_drv_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) struct fsl_usb2_platform_data *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) struct usb_hcd *hcd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) int retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) pr_debug("initializing FSL-SOC USB Controller\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /* Need platform data for setup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) pdata = dev_get_platdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) if (!pdata) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) "No platform data for %s.\n", dev_name(&pdev->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * This is a host mode driver, verify that we're supposed to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * in host mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) if (!((pdata->operating_mode == FSL_USB2_DR_HOST) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) (pdata->operating_mode == FSL_USB2_MPH_HOST) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) (pdata->operating_mode == FSL_USB2_DR_OTG))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) "Non Host Mode configured for %s. Wrong driver linked.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) dev_name(&pdev->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) if (!res) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) "Found HC with no IRQ. Check %s setup!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) dev_name(&pdev->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) irq = res->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) hcd = __usb_create_hcd(&fsl_ehci_hc_driver, pdev->dev.parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) &pdev->dev, dev_name(&pdev->dev), NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) if (!hcd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) retval = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) goto err1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) hcd->regs = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) if (IS_ERR(hcd->regs)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) retval = PTR_ERR(hcd->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) goto err2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) hcd->rsrc_start = res->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) hcd->rsrc_len = resource_size(res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) pdata->regs = hcd->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) if (pdata->power_budget)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) hcd->power_budget = pdata->power_budget;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * do platform specific init: check the clock, grab/config pins, etc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) if (pdata->init && pdata->init(pdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) retval = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) goto err2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /* Enable USB controller, 83xx or 8536 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) if (pdata->have_sysif_regs && pdata->controller_ver < FSL_USB_VER_1_6) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) tmp = ioread32be(hcd->regs + FSL_SOC_USB_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) tmp &= ~CONTROL_REGISTER_W1C_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) tmp |= 0x4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) iowrite32be(tmp, hcd->regs + FSL_SOC_USB_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /* Set USB_EN bit to select ULPI phy for USB controller version 2.5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) if (pdata->controller_ver == FSL_USB_VER_2_5 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) pdata->phy_mode == FSL_USB2_PHY_ULPI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) iowrite32be(USB_CTRL_USB_EN, hcd->regs + FSL_SOC_USB_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * Enable UTMI phy and program PTS field in UTMI mode before asserting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * controller reset for USB Controller version 2.5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) if (pdata->has_fsl_erratum_a007792) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) tmp = ioread32be(hcd->regs + FSL_SOC_USB_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) tmp &= ~CONTROL_REGISTER_W1C_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) tmp |= CTRL_UTMI_PHY_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) iowrite32be(tmp, hcd->regs + FSL_SOC_USB_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) writel(PORT_PTS_UTMI, hcd->regs + FSL_SOC_USB_PORTSC1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /* Don't need to set host mode here. It will be done by tdi_reset() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) retval = usb_add_hcd(hcd, irq, IRQF_SHARED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) if (retval != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) goto err2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) device_wakeup_enable(hcd->self.controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #ifdef CONFIG_USB_OTG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) if (pdata->operating_mode == FSL_USB2_DR_OTG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) struct ehci_hcd *ehci = hcd_to_ehci(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) hcd->usb_phy = usb_get_phy(USB_PHY_TYPE_USB2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) dev_dbg(&pdev->dev, "hcd=0x%p ehci=0x%p, phy=0x%p\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) hcd, ehci, hcd->usb_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) if (!IS_ERR_OR_NULL(hcd->usb_phy)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) retval = otg_set_host(hcd->usb_phy->otg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) &ehci_to_hcd(ehci)->self);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) if (retval) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) usb_put_phy(hcd->usb_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) goto err2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) dev_err(&pdev->dev, "can't find phy\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) retval = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) goto err2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) hcd->skip_phy_initialization = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) err2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) usb_put_hcd(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) err1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) dev_err(&pdev->dev, "init %s fail, %d\n", dev_name(&pdev->dev), retval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) if (pdata->exit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) pdata->exit(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static bool usb_phy_clk_valid(struct usb_hcd *hcd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) void __iomem *non_ehci = hcd->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) bool ret = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) if (!(ioread32be(non_ehci + FSL_SOC_USB_CTRL) & PHY_CLK_VALID))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) ret = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static int ehci_fsl_setup_phy(struct usb_hcd *hcd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) enum fsl_usb2_phy_modes phy_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) unsigned int port_offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) u32 portsc, tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) struct ehci_hcd *ehci = hcd_to_ehci(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) void __iomem *non_ehci = hcd->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) struct device *dev = hcd->self.controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) struct fsl_usb2_platform_data *pdata = dev_get_platdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) if (pdata->controller_ver < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) dev_warn(hcd->self.controller, "Could not get controller version\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) portsc = ehci_readl(ehci, &ehci->regs->port_status[port_offset]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) portsc &= ~(PORT_PTS_MSK | PORT_PTS_PTW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) switch (phy_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) case FSL_USB2_PHY_ULPI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) if (pdata->have_sysif_regs && pdata->controller_ver) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) /* controller version 1.6 or above */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) /* turn off UTMI PHY first */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) tmp = ioread32be(non_ehci + FSL_SOC_USB_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) tmp &= ~(CONTROL_REGISTER_W1C_MASK | UTMI_PHY_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) iowrite32be(tmp, non_ehci + FSL_SOC_USB_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) /* then turn on ULPI and enable USB controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) tmp = ioread32be(non_ehci + FSL_SOC_USB_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) tmp &= ~CONTROL_REGISTER_W1C_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) tmp |= ULPI_PHY_CLK_SEL | USB_CTRL_USB_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) iowrite32be(tmp, non_ehci + FSL_SOC_USB_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) portsc |= PORT_PTS_ULPI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) case FSL_USB2_PHY_SERIAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) portsc |= PORT_PTS_SERIAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) case FSL_USB2_PHY_UTMI_WIDE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) portsc |= PORT_PTS_PTW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) case FSL_USB2_PHY_UTMI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) /* Presence of this node "has_fsl_erratum_a006918"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) * in device-tree is used to stop USB controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) * initialization in Linux
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) if (pdata->has_fsl_erratum_a006918) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) dev_warn(dev, "USB PHY clock invalid\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) case FSL_USB2_PHY_UTMI_DUAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) /* PHY_CLK_VALID bit is de-featured from all controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) * versions below 2.4 and is to be checked only for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) * internal UTMI phy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) if (pdata->controller_ver > FSL_USB_VER_2_4 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) pdata->have_sysif_regs && !usb_phy_clk_valid(hcd)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) dev_err(dev, "USB PHY clock invalid\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) if (pdata->have_sysif_regs && pdata->controller_ver) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) /* controller version 1.6 or above */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) tmp = ioread32be(non_ehci + FSL_SOC_USB_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) tmp &= ~CONTROL_REGISTER_W1C_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) tmp |= UTMI_PHY_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) iowrite32be(tmp, non_ehci + FSL_SOC_USB_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) mdelay(FSL_UTMI_PHY_DLY); /* Delay for UTMI PHY CLK to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) become stable - 10ms*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) /* enable UTMI PHY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) if (pdata->have_sysif_regs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) tmp = ioread32be(non_ehci + FSL_SOC_USB_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) tmp &= ~CONTROL_REGISTER_W1C_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) tmp |= CTRL_UTMI_PHY_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) iowrite32be(tmp, non_ehci + FSL_SOC_USB_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) portsc |= PORT_PTS_UTMI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) case FSL_USB2_PHY_NONE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) if (pdata->have_sysif_regs &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) pdata->controller_ver > FSL_USB_VER_1_6 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) !usb_phy_clk_valid(hcd)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) dev_warn(hcd->self.controller, "USB PHY clock invalid\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) ehci_writel(ehci, portsc, &ehci->regs->port_status[port_offset]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) if (phy_mode != FSL_USB2_PHY_ULPI && pdata->have_sysif_regs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) tmp = ioread32be(non_ehci + FSL_SOC_USB_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) tmp &= ~CONTROL_REGISTER_W1C_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) tmp |= USB_CTRL_USB_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) iowrite32be(tmp, non_ehci + FSL_SOC_USB_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) static int ehci_fsl_usb_setup(struct ehci_hcd *ehci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) struct usb_hcd *hcd = ehci_to_hcd(ehci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) struct fsl_usb2_platform_data *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) void __iomem *non_ehci = hcd->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) pdata = dev_get_platdata(hcd->self.controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) if (pdata->have_sysif_regs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) * Turn on cache snooping hardware, since some PowerPC platforms
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) * wholly rely on hardware to deal with cache coherent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) /* Setup Snooping for all the 4GB space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) /* SNOOP1 starts from 0x0, size 2G */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) iowrite32be(0x0 | SNOOP_SIZE_2GB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) non_ehci + FSL_SOC_USB_SNOOP1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) /* SNOOP2 starts from 0x80000000, size 2G */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) iowrite32be(0x80000000 | SNOOP_SIZE_2GB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) non_ehci + FSL_SOC_USB_SNOOP2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) /* Deal with USB erratum A-005275 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) if (pdata->has_fsl_erratum_a005275 == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) ehci->has_fsl_hs_errata = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) if (pdata->has_fsl_erratum_a005697 == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) ehci->has_fsl_susp_errata = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) if ((pdata->operating_mode == FSL_USB2_DR_HOST) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) (pdata->operating_mode == FSL_USB2_DR_OTG))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) if (ehci_fsl_setup_phy(hcd, pdata->phy_mode, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) if (pdata->operating_mode == FSL_USB2_MPH_HOST) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) /* Deal with USB Erratum #14 on MPC834x Rev 1.0 & 1.1 chips */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) if (pdata->has_fsl_erratum_14 == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) ehci->has_fsl_port_bug = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) if (pdata->port_enables & FSL_USB2_PORT0_ENABLED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) if (ehci_fsl_setup_phy(hcd, pdata->phy_mode, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) if (pdata->port_enables & FSL_USB2_PORT1_ENABLED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) if (ehci_fsl_setup_phy(hcd, pdata->phy_mode, 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) if (pdata->have_sysif_regs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #ifdef CONFIG_FSL_SOC_BOOKE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) iowrite32be(0x00000008, non_ehci + FSL_SOC_USB_PRICTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) iowrite32be(0x00000080, non_ehci + FSL_SOC_USB_AGECNTTHRSH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) iowrite32be(0x0000000c, non_ehci + FSL_SOC_USB_PRICTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) iowrite32be(0x00000040, non_ehci + FSL_SOC_USB_AGECNTTHRSH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) iowrite32be(0x00000001, non_ehci + FSL_SOC_USB_SICTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) /* called after powerup, by probe or system-pm "wakeup" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) static int ehci_fsl_reinit(struct ehci_hcd *ehci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) if (ehci_fsl_usb_setup(ehci))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) /* called during probe() after chip reset completes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) static int ehci_fsl_setup(struct usb_hcd *hcd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) struct ehci_hcd *ehci = hcd_to_ehci(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) int retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) struct fsl_usb2_platform_data *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) dev = hcd->self.controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) pdata = dev_get_platdata(hcd->self.controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) ehci->big_endian_desc = pdata->big_endian_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) ehci->big_endian_mmio = pdata->big_endian_mmio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) /* EHCI registers start at offset 0x100 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) ehci->caps = hcd->regs + 0x100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #ifdef CONFIG_PPC_83xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) * Deal with MPC834X that need port power to be cycled after the power
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) * fault condition is removed. Otherwise the state machine does not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) * reflect PORTSC[CSC] correctly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) ehci->need_oc_pp_cycle = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) hcd->has_tt = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) retval = ehci_setup(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) if (retval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) if (of_device_is_compatible(dev->parent->of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) "fsl,mpc5121-usb2-dr")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) * set SBUSCFG:AHBBRST so that control msgs don't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) * fail when doing heavy PATA writes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) ehci_writel(ehci, SBUSCFG_INCR8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) hcd->regs + FSL_SOC_USB_SBUSCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) retval = ehci_fsl_reinit(ehci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) struct ehci_fsl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) struct ehci_hcd ehci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) /* Saved USB PHY settings, need to restore after deep sleep. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) u32 usb_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) #ifdef CONFIG_PPC_MPC512x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) static int ehci_fsl_mpc512x_drv_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) struct usb_hcd *hcd = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) struct ehci_hcd *ehci = hcd_to_ehci(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) struct fsl_usb2_platform_data *pdata = dev_get_platdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) #ifdef CONFIG_DYNAMIC_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) u32 mode = ehci_readl(ehci, hcd->regs + FSL_SOC_USB_USBMODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) mode &= USBMODE_CM_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) tmp = ehci_readl(ehci, hcd->regs + 0x140); /* usbcmd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) dev_dbg(dev, "suspend=%d already_suspended=%d "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) "mode=%d usbcmd %08x\n", pdata->suspended,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) pdata->already_suspended, mode, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) * If the controller is already suspended, then this must be a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) * PM suspend. Remember this fact, so that we will leave the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) * controller suspended at PM resume time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) if (pdata->suspended) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) dev_dbg(dev, "already suspended, leaving early\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) pdata->already_suspended = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) dev_dbg(dev, "suspending...\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) ehci->rh_state = EHCI_RH_SUSPENDED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) dev->power.power_state = PMSG_SUSPEND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) /* ignore non-host interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) /* stop the controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) tmp = ehci_readl(ehci, &ehci->regs->command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) tmp &= ~CMD_RUN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) ehci_writel(ehci, tmp, &ehci->regs->command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) /* save EHCI registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) pdata->pm_command = ehci_readl(ehci, &ehci->regs->command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) pdata->pm_command &= ~CMD_RUN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) pdata->pm_status = ehci_readl(ehci, &ehci->regs->status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) pdata->pm_intr_enable = ehci_readl(ehci, &ehci->regs->intr_enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) pdata->pm_frame_index = ehci_readl(ehci, &ehci->regs->frame_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) pdata->pm_segment = ehci_readl(ehci, &ehci->regs->segment);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) pdata->pm_frame_list = ehci_readl(ehci, &ehci->regs->frame_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) pdata->pm_async_next = ehci_readl(ehci, &ehci->regs->async_next);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) pdata->pm_configured_flag =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) ehci_readl(ehci, &ehci->regs->configured_flag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) pdata->pm_portsc = ehci_readl(ehci, &ehci->regs->port_status[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) pdata->pm_usbgenctrl = ehci_readl(ehci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) hcd->regs + FSL_SOC_USB_USBGENCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) /* clear the W1C bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) pdata->pm_portsc &= cpu_to_hc32(ehci, ~PORT_RWC_BITS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) pdata->suspended = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) /* clear PP to cut power to the port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) tmp = ehci_readl(ehci, &ehci->regs->port_status[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) tmp &= ~PORT_POWER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) ehci_writel(ehci, tmp, &ehci->regs->port_status[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) static int ehci_fsl_mpc512x_drv_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) struct usb_hcd *hcd = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) struct ehci_hcd *ehci = hcd_to_ehci(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) struct fsl_usb2_platform_data *pdata = dev_get_platdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) dev_dbg(dev, "suspend=%d already_suspended=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) pdata->suspended, pdata->already_suspended);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) * If the controller was already suspended at suspend time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) * then don't resume it now.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) if (pdata->already_suspended) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) dev_dbg(dev, "already suspended, leaving early\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) pdata->already_suspended = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) if (!pdata->suspended) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) dev_dbg(dev, "not suspended, leaving early\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) pdata->suspended = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) dev_dbg(dev, "resuming...\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) /* set host mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) tmp = USBMODE_CM_HOST | (pdata->es ? USBMODE_ES : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) ehci_writel(ehci, tmp, hcd->regs + FSL_SOC_USB_USBMODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) ehci_writel(ehci, pdata->pm_usbgenctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) hcd->regs + FSL_SOC_USB_USBGENCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) ehci_writel(ehci, ISIPHYCTRL_PXE | ISIPHYCTRL_PHYE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) hcd->regs + FSL_SOC_USB_ISIPHYCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) ehci_writel(ehci, SBUSCFG_INCR8, hcd->regs + FSL_SOC_USB_SBUSCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) /* restore EHCI registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) ehci_writel(ehci, pdata->pm_command, &ehci->regs->command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) ehci_writel(ehci, pdata->pm_intr_enable, &ehci->regs->intr_enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) ehci_writel(ehci, pdata->pm_frame_index, &ehci->regs->frame_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) ehci_writel(ehci, pdata->pm_segment, &ehci->regs->segment);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) ehci_writel(ehci, pdata->pm_frame_list, &ehci->regs->frame_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) ehci_writel(ehci, pdata->pm_async_next, &ehci->regs->async_next);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) ehci_writel(ehci, pdata->pm_configured_flag,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) &ehci->regs->configured_flag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) ehci_writel(ehci, pdata->pm_portsc, &ehci->regs->port_status[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) ehci->rh_state = EHCI_RH_RUNNING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) dev->power.power_state = PMSG_ON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) tmp = ehci_readl(ehci, &ehci->regs->command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) tmp |= CMD_RUN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) ehci_writel(ehci, tmp, &ehci->regs->command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) usb_hcd_resume_root_hub(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) static inline int ehci_fsl_mpc512x_drv_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) static inline int ehci_fsl_mpc512x_drv_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) #endif /* CONFIG_PPC_MPC512x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) static struct ehci_fsl *hcd_to_ehci_fsl(struct usb_hcd *hcd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) struct ehci_hcd *ehci = hcd_to_ehci(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) return container_of(ehci, struct ehci_fsl, ehci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) static int ehci_fsl_drv_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) struct usb_hcd *hcd = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) struct ehci_fsl *ehci_fsl = hcd_to_ehci_fsl(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) void __iomem *non_ehci = hcd->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) if (of_device_is_compatible(dev->parent->of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) "fsl,mpc5121-usb2-dr")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) return ehci_fsl_mpc512x_drv_suspend(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) ehci_prepare_ports_for_controller_suspend(hcd_to_ehci(hcd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) device_may_wakeup(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) if (!fsl_deep_sleep())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) ehci_fsl->usb_ctrl = ioread32be(non_ehci + FSL_SOC_USB_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) static int ehci_fsl_drv_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) struct usb_hcd *hcd = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) struct ehci_fsl *ehci_fsl = hcd_to_ehci_fsl(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) struct ehci_hcd *ehci = hcd_to_ehci(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) void __iomem *non_ehci = hcd->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) if (of_device_is_compatible(dev->parent->of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) "fsl,mpc5121-usb2-dr")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) return ehci_fsl_mpc512x_drv_resume(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) ehci_prepare_ports_for_controller_resume(ehci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) if (!fsl_deep_sleep())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) usb_root_hub_lost_power(hcd->self.root_hub);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) /* Restore USB PHY settings and enable the controller. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) iowrite32be(ehci_fsl->usb_ctrl, non_ehci + FSL_SOC_USB_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) ehci_reset(ehci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) ehci_fsl_reinit(ehci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) static int ehci_fsl_drv_restore(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) struct usb_hcd *hcd = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) usb_root_hub_lost_power(hcd->self.root_hub);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) static const struct dev_pm_ops ehci_fsl_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) .suspend = ehci_fsl_drv_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) .resume = ehci_fsl_drv_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) .restore = ehci_fsl_drv_restore,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) #define EHCI_FSL_PM_OPS (&ehci_fsl_pm_ops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) #define EHCI_FSL_PM_OPS NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) #endif /* CONFIG_PM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) #ifdef CONFIG_USB_OTG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) static int ehci_start_port_reset(struct usb_hcd *hcd, unsigned port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) struct ehci_hcd *ehci = hcd_to_ehci(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) if (!port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) port--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) /* start port reset before HNP protocol time out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) status = readl(&ehci->regs->port_status[port]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) if (!(status & PORT_CONNECT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) /* hub_wq will finish the reset later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) if (ehci_is_TDI(ehci)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) writel(PORT_RESET |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) (status & ~(PORT_CSC | PORT_PEC | PORT_OCC)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) &ehci->regs->port_status[port]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) writel(PORT_RESET, &ehci->regs->port_status[port]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) #define ehci_start_port_reset NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) #endif /* CONFIG_USB_OTG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) static const struct ehci_driver_overrides ehci_fsl_overrides __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) .extra_priv_size = sizeof(struct ehci_fsl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) .reset = ehci_fsl_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) * fsl_ehci_drv_remove - shutdown processing for FSL-based HCDs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) * @pdev: USB Host Controller being removed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) * Context: !in_interrupt()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) * Reverses the effect of usb_hcd_fsl_probe().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) static int fsl_ehci_drv_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) struct fsl_usb2_platform_data *pdata = dev_get_platdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) struct usb_hcd *hcd = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) if (!IS_ERR_OR_NULL(hcd->usb_phy)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) otg_set_host(hcd->usb_phy->otg, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) usb_put_phy(hcd->usb_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) usb_remove_hcd(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) * do platform specific un-initialization:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) * release iomux pins, disable clock, etc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) if (pdata->exit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) pdata->exit(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) usb_put_hcd(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) static struct platform_driver ehci_fsl_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) .probe = fsl_ehci_drv_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) .remove = fsl_ehci_drv_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) .shutdown = usb_hcd_platform_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) .name = "fsl-ehci",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) .pm = EHCI_FSL_PM_OPS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) static int __init ehci_fsl_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) if (usb_disabled())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) pr_info(DRV_NAME ": " DRIVER_DESC "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) ehci_init_driver(&fsl_ehci_hc_driver, &ehci_fsl_overrides);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) fsl_ehci_hc_driver.product_desc =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) "Freescale On-Chip EHCI Host Controller";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) fsl_ehci_hc_driver.start_port_reset = ehci_start_port_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) return platform_driver_register(&ehci_fsl_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) module_init(ehci_fsl_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) static void __exit ehci_fsl_cleanup(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) platform_driver_unregister(&ehci_fsl_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) module_exit(ehci_fsl_cleanup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) MODULE_DESCRIPTION(DRIVER_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) MODULE_ALIAS("platform:" DRV_NAME);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags