^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Xilinx USB peripheral controller driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2004 by Thomas Rathbone
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2005 by HP Labs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2005 by David Brownell
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (C) 2010 - 2014 Xilinx, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Some parts of this driver code is based on the driver for at91-series
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * USB peripheral controller (at91_udc.c).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/prefetch.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/usb/ch9.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/usb/gadget.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /* Register offsets for the USB device.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define XUSB_EP0_CONFIG_OFFSET 0x0000 /* EP0 Config Reg Offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define XUSB_SETUP_PKT_ADDR_OFFSET 0x0080 /* Setup Packet Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define XUSB_ADDRESS_OFFSET 0x0100 /* Address Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define XUSB_CONTROL_OFFSET 0x0104 /* Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define XUSB_STATUS_OFFSET 0x0108 /* Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define XUSB_FRAMENUM_OFFSET 0x010C /* Frame Number Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define XUSB_IER_OFFSET 0x0110 /* Interrupt Enable Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define XUSB_BUFFREADY_OFFSET 0x0114 /* Buffer Ready Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define XUSB_TESTMODE_OFFSET 0x0118 /* Test Mode Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define XUSB_DMA_RESET_OFFSET 0x0200 /* DMA Soft Reset Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define XUSB_DMA_CONTROL_OFFSET 0x0204 /* DMA Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define XUSB_DMA_DSAR_ADDR_OFFSET 0x0208 /* DMA source Address Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define XUSB_DMA_DDAR_ADDR_OFFSET 0x020C /* DMA destination Addr Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define XUSB_DMA_LENGTH_OFFSET 0x0210 /* DMA Length Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define XUSB_DMA_STATUS_OFFSET 0x0214 /* DMA Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /* Endpoint Configuration Space offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define XUSB_EP_CFGSTATUS_OFFSET 0x00 /* Endpoint Config Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define XUSB_EP_BUF0COUNT_OFFSET 0x08 /* Buffer 0 Count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define XUSB_EP_BUF1COUNT_OFFSET 0x0C /* Buffer 1 Count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define XUSB_CONTROL_USB_READY_MASK 0x80000000 /* USB ready Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define XUSB_CONTROL_USB_RMTWAKE_MASK 0x40000000 /* Remote wake up mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /* Interrupt register related masks.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define XUSB_STATUS_GLOBAL_INTR_MASK 0x80000000 /* Global Intr Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define XUSB_STATUS_DMADONE_MASK 0x04000000 /* DMA done Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define XUSB_STATUS_DMAERR_MASK 0x02000000 /* DMA Error Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define XUSB_STATUS_DMABUSY_MASK 0x80000000 /* DMA Error Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define XUSB_STATUS_RESUME_MASK 0x01000000 /* USB Resume Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define XUSB_STATUS_RESET_MASK 0x00800000 /* USB Reset Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define XUSB_STATUS_SUSPEND_MASK 0x00400000 /* USB Suspend Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define XUSB_STATUS_DISCONNECT_MASK 0x00200000 /* USB Disconnect Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define XUSB_STATUS_FIFO_BUFF_RDY_MASK 0x00100000 /* FIFO Buff Ready Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define XUSB_STATUS_FIFO_BUFF_FREE_MASK 0x00080000 /* FIFO Buff Free Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define XUSB_STATUS_SETUP_PACKET_MASK 0x00040000 /* Setup packet received */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define XUSB_STATUS_EP1_BUFF2_COMP_MASK 0x00000200 /* EP 1 Buff 2 Processed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define XUSB_STATUS_EP1_BUFF1_COMP_MASK 0x00000002 /* EP 1 Buff 1 Processed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define XUSB_STATUS_EP0_BUFF2_COMP_MASK 0x00000100 /* EP 0 Buff 2 Processed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define XUSB_STATUS_EP0_BUFF1_COMP_MASK 0x00000001 /* EP 0 Buff 1 Processed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define XUSB_STATUS_HIGH_SPEED_MASK 0x00010000 /* USB Speed Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /* Suspend,Reset,Suspend and Disconnect Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define XUSB_STATUS_INTR_EVENT_MASK 0x01E00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* Buffers completion Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define XUSB_STATUS_INTR_BUFF_COMP_ALL_MASK 0x0000FEFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* Mask for buffer 0 and buffer 1 completion for all Endpoints */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define XUSB_STATUS_INTR_BUFF_COMP_SHIFT_MASK 0x00000101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define XUSB_STATUS_EP_BUFF2_SHIFT 8 /* EP buffer offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /* Endpoint Configuration Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define XUSB_EP_CFG_VALID_MASK 0x80000000 /* Endpoint Valid bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define XUSB_EP_CFG_STALL_MASK 0x40000000 /* Endpoint Stall bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define XUSB_EP_CFG_DATA_TOGGLE_MASK 0x08000000 /* Endpoint Data toggle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /* USB device specific global configuration constants.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define XUSB_MAX_ENDPOINTS 8 /* Maximum End Points */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define XUSB_EP_NUMBER_ZERO 0 /* End point Zero */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /* DPRAM is the source address for DMA transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define XUSB_DMA_READ_FROM_DPRAM 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define XUSB_DMA_DMASR_BUSY 0x80000000 /* DMA busy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define XUSB_DMA_DMASR_ERROR 0x40000000 /* DMA Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * When this bit is set, the DMA buffer ready bit is set by hardware upon
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * DMA transfer completion.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define XUSB_DMA_BRR_CTRL 0x40000000 /* DMA bufready ctrl bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /* Phase States */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define SETUP_PHASE 0x0000 /* Setup Phase */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define DATA_PHASE 0x0001 /* Data Phase */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define STATUS_PHASE 0x0002 /* Status Phase */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define EP0_MAX_PACKET 64 /* Endpoint 0 maximum packet length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define STATUSBUFF_SIZE 2 /* Buffer size for GET_STATUS command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define EPNAME_SIZE 4 /* Buffer size for endpoint name */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /* container_of helper macros */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define to_udc(g) container_of((g), struct xusb_udc, gadget)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define to_xusb_ep(ep) container_of((ep), struct xusb_ep, ep_usb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define to_xusb_req(req) container_of((req), struct xusb_req, usb_req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * struct xusb_req - Xilinx USB device request structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * @usb_req: Linux usb request structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * @queue: usb device request queue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * @ep: pointer to xusb_endpoint structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) struct xusb_req {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) struct usb_request usb_req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) struct list_head queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) struct xusb_ep *ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) * struct xusb_ep - USB end point structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) * @ep_usb: usb endpoint instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * @queue: endpoint message queue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) * @udc: xilinx usb peripheral driver instance pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * @desc: pointer to the usb endpoint descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * @rambase: the endpoint buffer address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * @offset: the endpoint register offset value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * @name: name of the endpoint
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * @epnumber: endpoint number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * @maxpacket: maximum packet size the endpoint can store
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * @buffer0count: the size of the packet recieved in the first buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * @buffer1count: the size of the packet received in the second buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * @curbufnum: current buffer of endpoint that will be processed next
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) * @buffer0ready: the busy state of first buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * @buffer1ready: the busy state of second buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) * @is_in: endpoint direction (IN or OUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) * @is_iso: endpoint type(isochronous or non isochronous)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) struct xusb_ep {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) struct usb_ep ep_usb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) struct list_head queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) struct xusb_udc *udc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) const struct usb_endpoint_descriptor *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) u32 rambase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) u32 offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) char name[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) u16 epnumber;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) u16 maxpacket;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) u16 buffer0count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) u16 buffer1count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) u8 curbufnum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) bool buffer0ready;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) bool buffer1ready;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) bool is_in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) bool is_iso;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) * struct xusb_udc - USB peripheral driver structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) * @gadget: USB gadget driver instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) * @ep: an array of endpoint structures
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * @driver: pointer to the usb gadget driver instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) * @setup: usb_ctrlrequest structure for control requests
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) * @req: pointer to dummy request for get status command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * @dev: pointer to device structure in gadget
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) * @usb_state: device in suspended state or not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) * @remote_wkp: remote wakeup enabled by host
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) * @setupseqtx: tx status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) * @setupseqrx: rx status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) * @addr: the usb device base address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) * @lock: instance of spinlock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) * @dma_enabled: flag indicating whether the dma is included in the system
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) * @read_fn: function pointer to read device registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) * @write_fn: function pointer to write to device registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) struct xusb_udc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) struct usb_gadget gadget;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) struct xusb_ep ep[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) struct usb_gadget_driver *driver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) struct usb_ctrlrequest setup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) struct xusb_req *req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) u32 usb_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) u32 remote_wkp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) u32 setupseqtx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) u32 setupseqrx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) void __iomem *addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) bool dma_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) unsigned int (*read_fn)(void __iomem *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) void (*write_fn)(void __iomem *, u32, u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) /* Endpoint buffer start addresses in the core */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static u32 rambase[8] = { 0x22, 0x1000, 0x1100, 0x1200, 0x1300, 0x1400, 0x1500,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 0x1600 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static const char driver_name[] = "xilinx-udc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) static const char ep0name[] = "ep0";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) /* Control endpoint configuration.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) static const struct usb_endpoint_descriptor config_bulk_out_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) .bLength = USB_DT_ENDPOINT_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) .bDescriptorType = USB_DT_ENDPOINT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) .bEndpointAddress = USB_DIR_OUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) .bmAttributes = USB_ENDPOINT_XFER_BULK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) .wMaxPacketSize = cpu_to_le16(EP0_MAX_PACKET),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) * xudc_write32 - little endian write to device registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) * @addr: base addr of device registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) * @offset: register offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) * @val: data to be written
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) static void xudc_write32(void __iomem *addr, u32 offset, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) iowrite32(val, addr + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) * xudc_read32 - little endian read from device registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) * @addr: addr of device register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) * Return: value at addr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static unsigned int xudc_read32(void __iomem *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) return ioread32(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) * xudc_write32_be - big endian write to device registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) * @addr: base addr of device registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) * @offset: register offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) * @val: data to be written
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static void xudc_write32_be(void __iomem *addr, u32 offset, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) iowrite32be(val, addr + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) * xudc_read32_be - big endian read from device registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) * @addr: addr of device register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) * Return: value at addr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) static unsigned int xudc_read32_be(void __iomem *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) return ioread32be(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) * xudc_wrstatus - Sets up the usb device status stages.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) * @udc: pointer to the usb device controller structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) static void xudc_wrstatus(struct xusb_udc *udc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) struct xusb_ep *ep0 = &udc->ep[XUSB_EP_NUMBER_ZERO];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) u32 epcfgreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) epcfgreg = udc->read_fn(udc->addr + ep0->offset)|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) XUSB_EP_CFG_DATA_TOGGLE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) udc->write_fn(udc->addr, ep0->offset, epcfgreg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) udc->write_fn(udc->addr, ep0->offset + XUSB_EP_BUF0COUNT_OFFSET, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) udc->write_fn(udc->addr, XUSB_BUFFREADY_OFFSET, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) * xudc_epconfig - Configures the given endpoint.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) * @ep: pointer to the usb device endpoint structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) * @udc: pointer to the usb peripheral controller structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) * This function configures a specific endpoint with the given configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) * data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) static void xudc_epconfig(struct xusb_ep *ep, struct xusb_udc *udc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) u32 epcfgreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) * Configure the end point direction, type, Max Packet Size and the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) * EP buffer location.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) epcfgreg = ((ep->is_in << 29) | (ep->is_iso << 28) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) (ep->ep_usb.maxpacket << 15) | (ep->rambase));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) udc->write_fn(udc->addr, ep->offset, epcfgreg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) /* Set the Buffer count and the Buffer ready bits.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) udc->write_fn(udc->addr, ep->offset + XUSB_EP_BUF0COUNT_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) ep->buffer0count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) udc->write_fn(udc->addr, ep->offset + XUSB_EP_BUF1COUNT_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) ep->buffer1count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) if (ep->buffer0ready)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) udc->write_fn(udc->addr, XUSB_BUFFREADY_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 1 << ep->epnumber);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) if (ep->buffer1ready)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) udc->write_fn(udc->addr, XUSB_BUFFREADY_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 1 << (ep->epnumber + XUSB_STATUS_EP_BUFF2_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) * xudc_start_dma - Starts DMA transfer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) * @ep: pointer to the usb device endpoint structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) * @src: DMA source address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) * @dst: DMA destination address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) * @length: number of bytes to transfer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) * Return: 0 on success, error code on failure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) * This function starts DMA transfer by writing to DMA source,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) * destination and lenth registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) static int xudc_start_dma(struct xusb_ep *ep, dma_addr_t src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) dma_addr_t dst, u32 length)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) struct xusb_udc *udc = ep->udc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) int rc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) u32 timeout = 500;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) * Set the addresses in the DMA source and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) * destination registers and then set the length
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) * into the DMA length register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) udc->write_fn(udc->addr, XUSB_DMA_DSAR_ADDR_OFFSET, src);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) udc->write_fn(udc->addr, XUSB_DMA_DDAR_ADDR_OFFSET, dst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) udc->write_fn(udc->addr, XUSB_DMA_LENGTH_OFFSET, length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) * Wait till DMA transaction is complete and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) * check whether the DMA transaction was
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) * successful.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) reg = udc->read_fn(udc->addr + XUSB_DMA_STATUS_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) if (!(reg & XUSB_DMA_DMASR_BUSY))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) * We can't sleep here, because it's also called from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) * interrupt context.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) timeout--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) if (!timeout) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) dev_err(udc->dev, "DMA timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) } while (1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) if ((udc->read_fn(udc->addr + XUSB_DMA_STATUS_OFFSET) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) XUSB_DMA_DMASR_ERROR) == XUSB_DMA_DMASR_ERROR){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) dev_err(udc->dev, "DMA Error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) rc = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) * xudc_dma_send - Sends IN data using DMA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) * @ep: pointer to the usb device endpoint structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) * @req: pointer to the usb request structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) * @buffer: pointer to data to be sent.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) * @length: number of bytes to send.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) * Return: 0 on success, -EAGAIN if no buffer is free and error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) * code on failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) * This function sends data using DMA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) static int xudc_dma_send(struct xusb_ep *ep, struct xusb_req *req,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) u8 *buffer, u32 length)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) u32 *eprambase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) dma_addr_t src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) dma_addr_t dst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) struct xusb_udc *udc = ep->udc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) src = req->usb_req.dma + req->usb_req.actual;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) if (req->usb_req.length)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) dma_sync_single_for_device(udc->dev, src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) length, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) if (!ep->curbufnum && !ep->buffer0ready) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) /* Get the Buffer address and copy the transmit data.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) eprambase = (u32 __force *)(udc->addr + ep->rambase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) dst = virt_to_phys(eprambase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) udc->write_fn(udc->addr, ep->offset +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) XUSB_EP_BUF0COUNT_OFFSET, length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) udc->write_fn(udc->addr, XUSB_DMA_CONTROL_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) XUSB_DMA_BRR_CTRL | (1 << ep->epnumber));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) ep->buffer0ready = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) ep->curbufnum = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) } else if (ep->curbufnum && !ep->buffer1ready) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) /* Get the Buffer address and copy the transmit data.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) eprambase = (u32 __force *)(udc->addr + ep->rambase +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) ep->ep_usb.maxpacket);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) dst = virt_to_phys(eprambase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) udc->write_fn(udc->addr, ep->offset +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) XUSB_EP_BUF1COUNT_OFFSET, length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) udc->write_fn(udc->addr, XUSB_DMA_CONTROL_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) XUSB_DMA_BRR_CTRL | (1 << (ep->epnumber +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) XUSB_STATUS_EP_BUFF2_SHIFT)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) ep->buffer1ready = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) ep->curbufnum = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) /* None of ping pong buffers are ready currently .*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) return xudc_start_dma(ep, src, dst, length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) * xudc_dma_receive - Receives OUT data using DMA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) * @ep: pointer to the usb device endpoint structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) * @req: pointer to the usb request structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) * @buffer: pointer to storage buffer of received data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) * @length: number of bytes to receive.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) * Return: 0 on success, -EAGAIN if no buffer is free and error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) * code on failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) * This function receives data using DMA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) static int xudc_dma_receive(struct xusb_ep *ep, struct xusb_req *req,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) u8 *buffer, u32 length)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) u32 *eprambase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) dma_addr_t src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) dma_addr_t dst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) struct xusb_udc *udc = ep->udc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) dst = req->usb_req.dma + req->usb_req.actual;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) if (!ep->curbufnum && !ep->buffer0ready) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) /* Get the Buffer address and copy the transmit data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) eprambase = (u32 __force *)(udc->addr + ep->rambase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) src = virt_to_phys(eprambase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) udc->write_fn(udc->addr, XUSB_DMA_CONTROL_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) XUSB_DMA_BRR_CTRL | XUSB_DMA_READ_FROM_DPRAM |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) (1 << ep->epnumber));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) ep->buffer0ready = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) ep->curbufnum = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) } else if (ep->curbufnum && !ep->buffer1ready) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) /* Get the Buffer address and copy the transmit data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) eprambase = (u32 __force *)(udc->addr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) ep->rambase + ep->ep_usb.maxpacket);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) src = virt_to_phys(eprambase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) udc->write_fn(udc->addr, XUSB_DMA_CONTROL_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) XUSB_DMA_BRR_CTRL | XUSB_DMA_READ_FROM_DPRAM |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) (1 << (ep->epnumber +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) XUSB_STATUS_EP_BUFF2_SHIFT)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) ep->buffer1ready = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) ep->curbufnum = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) /* None of the ping-pong buffers are ready currently */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) return xudc_start_dma(ep, src, dst, length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) * xudc_eptxrx - Transmits or receives data to or from an endpoint.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) * @ep: pointer to the usb endpoint configuration structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) * @req: pointer to the usb request structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) * @bufferptr: pointer to buffer containing the data to be sent.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) * @bufferlen: The number of data bytes to be sent.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) * Return: 0 on success, -EAGAIN if no buffer is free.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) * This function copies the transmit/receive data to/from the end point buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) * and enables the buffer for transmission/reception.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) static int xudc_eptxrx(struct xusb_ep *ep, struct xusb_req *req,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) u8 *bufferptr, u32 bufferlen)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) u32 *eprambase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) u32 bytestosend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) int rc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) struct xusb_udc *udc = ep->udc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) bytestosend = bufferlen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) if (udc->dma_enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) if (ep->is_in)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) rc = xudc_dma_send(ep, req, bufferptr, bufferlen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) rc = xudc_dma_receive(ep, req, bufferptr, bufferlen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) /* Put the transmit buffer into the correct ping-pong buffer.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) if (!ep->curbufnum && !ep->buffer0ready) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) /* Get the Buffer address and copy the transmit data.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) eprambase = (u32 __force *)(udc->addr + ep->rambase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) if (ep->is_in) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) memcpy(eprambase, bufferptr, bytestosend);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) udc->write_fn(udc->addr, ep->offset +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) XUSB_EP_BUF0COUNT_OFFSET, bufferlen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) memcpy(bufferptr, eprambase, bytestosend);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) * Enable the buffer for transmission.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) udc->write_fn(udc->addr, XUSB_BUFFREADY_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) 1 << ep->epnumber);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) ep->buffer0ready = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) ep->curbufnum = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) } else if (ep->curbufnum && !ep->buffer1ready) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) /* Get the Buffer address and copy the transmit data.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) eprambase = (u32 __force *)(udc->addr + ep->rambase +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) ep->ep_usb.maxpacket);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) if (ep->is_in) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) memcpy(eprambase, bufferptr, bytestosend);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) udc->write_fn(udc->addr, ep->offset +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) XUSB_EP_BUF1COUNT_OFFSET, bufferlen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) memcpy(bufferptr, eprambase, bytestosend);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) * Enable the buffer for transmission.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) udc->write_fn(udc->addr, XUSB_BUFFREADY_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) 1 << (ep->epnumber + XUSB_STATUS_EP_BUFF2_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) ep->buffer1ready = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) ep->curbufnum = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) /* None of the ping-pong buffers are ready currently */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) * xudc_done - Exeutes the endpoint data transfer completion tasks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) * @ep: pointer to the usb device endpoint structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) * @req: pointer to the usb request structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) * @status: Status of the data transfer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) * Deletes the message from the queue and updates data transfer completion
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) * status.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) static void xudc_done(struct xusb_ep *ep, struct xusb_req *req, int status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) struct xusb_udc *udc = ep->udc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) list_del_init(&req->queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) if (req->usb_req.status == -EINPROGRESS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) req->usb_req.status = status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) status = req->usb_req.status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) if (status && status != -ESHUTDOWN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) dev_dbg(udc->dev, "%s done %p, status %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) ep->ep_usb.name, req, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) /* unmap request if DMA is present*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) if (udc->dma_enabled && ep->epnumber && req->usb_req.length)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) usb_gadget_unmap_request(&udc->gadget, &req->usb_req,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) ep->is_in);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) if (req->usb_req.complete) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) spin_unlock(&udc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) req->usb_req.complete(&ep->ep_usb, &req->usb_req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) spin_lock(&udc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) * xudc_read_fifo - Reads the data from the given endpoint buffer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) * @ep: pointer to the usb device endpoint structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) * @req: pointer to the usb request structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) * Return: 0 if request is completed and -EAGAIN if not completed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) * Pulls OUT packet data from the endpoint buffer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) static int xudc_read_fifo(struct xusb_ep *ep, struct xusb_req *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) u8 *buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) u32 is_short, count, bufferspace;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) u8 bufoffset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) u8 two_pkts = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) int retval = -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) struct xusb_udc *udc = ep->udc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) if (ep->buffer0ready && ep->buffer1ready) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) dev_dbg(udc->dev, "Packet NOT ready!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) top:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) if (ep->curbufnum)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) bufoffset = XUSB_EP_BUF1COUNT_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) bufoffset = XUSB_EP_BUF0COUNT_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) count = udc->read_fn(udc->addr + ep->offset + bufoffset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) if (!ep->buffer0ready && !ep->buffer1ready)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) two_pkts = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) buf = req->usb_req.buf + req->usb_req.actual;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) prefetchw(buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) bufferspace = req->usb_req.length - req->usb_req.actual;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) is_short = count < ep->ep_usb.maxpacket;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) if (unlikely(!bufferspace)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) * This happens when the driver's buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) * is smaller than what the host sent.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) * discard the extra data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) if (req->usb_req.status != -EOVERFLOW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) dev_dbg(udc->dev, "%s overflow %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) ep->ep_usb.name, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) req->usb_req.status = -EOVERFLOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) xudc_done(ep, req, -EOVERFLOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) ret = xudc_eptxrx(ep, req, buf, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) switch (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) req->usb_req.actual += min(count, bufferspace);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) dev_dbg(udc->dev, "read %s, %d bytes%s req %p %d/%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) ep->ep_usb.name, count, is_short ? "/S" : "", req,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) req->usb_req.actual, req->usb_req.length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) bufferspace -= count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) /* Completion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) if ((req->usb_req.actual == req->usb_req.length) || is_short) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) if (udc->dma_enabled && req->usb_req.length)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) dma_sync_single_for_cpu(udc->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) req->usb_req.dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) req->usb_req.actual,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) xudc_done(ep, req, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) if (two_pkts) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) two_pkts = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) goto top;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) case -EAGAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) dev_dbg(udc->dev, "receive busy\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) case -EINVAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) case -ETIMEDOUT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) /* DMA error, dequeue the request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) xudc_done(ep, req, -ECONNRESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) retval = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) * xudc_write_fifo - Writes data into the given endpoint buffer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) * @ep: pointer to the usb device endpoint structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) * @req: pointer to the usb request structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) * Return: 0 if request is completed and -EAGAIN if not completed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) * Loads endpoint buffer for an IN packet.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) static int xudc_write_fifo(struct xusb_ep *ep, struct xusb_req *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) u32 max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) u32 length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) int retval = -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) struct xusb_udc *udc = ep->udc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) int is_last, is_short = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) u8 *buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) max = le16_to_cpu(ep->desc->wMaxPacketSize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) buf = req->usb_req.buf + req->usb_req.actual;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) prefetch(buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) length = req->usb_req.length - req->usb_req.actual;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) length = min(length, max);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) ret = xudc_eptxrx(ep, req, buf, length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) switch (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) req->usb_req.actual += length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) if (unlikely(length != max)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) is_last = is_short = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) if (likely(req->usb_req.length !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) req->usb_req.actual) || req->usb_req.zero)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) is_last = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) is_last = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) dev_dbg(udc->dev, "%s: wrote %s %d bytes%s%s %d left %p\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) __func__, ep->ep_usb.name, length, is_last ? "/L" : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) is_short ? "/S" : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) req->usb_req.length - req->usb_req.actual, req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) /* completion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) if (is_last) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) xudc_done(ep, req, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) retval = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) case -EAGAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) dev_dbg(udc->dev, "Send busy\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) case -EINVAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) case -ETIMEDOUT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) /* DMA error, dequeue the request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) xudc_done(ep, req, -ECONNRESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) retval = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) * xudc_nuke - Cleans up the data transfer message list.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) * @ep: pointer to the usb device endpoint structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) * @status: Status of the data transfer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) static void xudc_nuke(struct xusb_ep *ep, int status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) struct xusb_req *req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) while (!list_empty(&ep->queue)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) req = list_first_entry(&ep->queue, struct xusb_req, queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) xudc_done(ep, req, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) * xudc_ep_set_halt - Stalls/unstalls the given endpoint.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) * @_ep: pointer to the usb device endpoint structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) * @value: value to indicate stall/unstall.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) * Return: 0 for success and error value on failure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) static int xudc_ep_set_halt(struct usb_ep *_ep, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) struct xusb_ep *ep = to_xusb_ep(_ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) struct xusb_udc *udc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) u32 epcfgreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) if (!_ep || (!ep->desc && ep->epnumber)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) pr_debug("%s: bad ep or descriptor\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) udc = ep->udc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) if (ep->is_in && (!list_empty(&ep->queue)) && value) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) dev_dbg(udc->dev, "requests pending can't halt\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) if (ep->buffer0ready || ep->buffer1ready) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) dev_dbg(udc->dev, "HW buffers busy can't halt\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) spin_lock_irqsave(&udc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) if (value) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) /* Stall the device.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) epcfgreg = udc->read_fn(udc->addr + ep->offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) epcfgreg |= XUSB_EP_CFG_STALL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) udc->write_fn(udc->addr, ep->offset, epcfgreg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) /* Unstall the device.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) epcfgreg = udc->read_fn(udc->addr + ep->offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) epcfgreg &= ~XUSB_EP_CFG_STALL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) udc->write_fn(udc->addr, ep->offset, epcfgreg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) if (ep->epnumber) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) /* Reset the toggle bit.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) epcfgreg = udc->read_fn(ep->udc->addr + ep->offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) epcfgreg &= ~XUSB_EP_CFG_DATA_TOGGLE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) udc->write_fn(udc->addr, ep->offset, epcfgreg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) spin_unlock_irqrestore(&udc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) * xudc_ep_enable - Enables the given endpoint.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) * @ep: pointer to the xusb endpoint structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) * @desc: pointer to usb endpoint descriptor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) * Return: 0 for success and error value on failure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) static int __xudc_ep_enable(struct xusb_ep *ep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) const struct usb_endpoint_descriptor *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) struct xusb_udc *udc = ep->udc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) u32 epcfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) u32 ier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) u16 maxpacket;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) ep->is_in = ((desc->bEndpointAddress & USB_DIR_IN) != 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) /* Bit 3...0:endpoint number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) ep->epnumber = (desc->bEndpointAddress & 0x0f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) ep->desc = desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) ep->ep_usb.desc = desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) tmp = desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) ep->ep_usb.maxpacket = maxpacket = le16_to_cpu(desc->wMaxPacketSize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) switch (tmp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) case USB_ENDPOINT_XFER_CONTROL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) dev_dbg(udc->dev, "only one control endpoint\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) /* NON- ISO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) ep->is_iso = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) case USB_ENDPOINT_XFER_INT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) /* NON- ISO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) ep->is_iso = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) if (maxpacket > 64) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) dev_dbg(udc->dev, "bogus maxpacket %d\n", maxpacket);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) case USB_ENDPOINT_XFER_BULK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) /* NON- ISO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) ep->is_iso = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) if (!(is_power_of_2(maxpacket) && maxpacket >= 8 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) maxpacket <= 512)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) dev_dbg(udc->dev, "bogus maxpacket %d\n", maxpacket);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) case USB_ENDPOINT_XFER_ISOC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) /* ISO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) ep->is_iso = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) ep->buffer0ready = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) ep->buffer1ready = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) ep->curbufnum = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) ep->rambase = rambase[ep->epnumber];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) xudc_epconfig(ep, udc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) dev_dbg(udc->dev, "Enable Endpoint %d max pkt is %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) ep->epnumber, maxpacket);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) /* Enable the End point.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) epcfg = udc->read_fn(udc->addr + ep->offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) epcfg |= XUSB_EP_CFG_VALID_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) udc->write_fn(udc->addr, ep->offset, epcfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) if (ep->epnumber)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) ep->rambase <<= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) /* Enable buffer completion interrupts for endpoint */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) ier = udc->read_fn(udc->addr + XUSB_IER_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) ier |= (XUSB_STATUS_INTR_BUFF_COMP_SHIFT_MASK << ep->epnumber);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) udc->write_fn(udc->addr, XUSB_IER_OFFSET, ier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) /* for OUT endpoint set buffers ready to receive */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) if (ep->epnumber && !ep->is_in) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) udc->write_fn(udc->addr, XUSB_BUFFREADY_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) 1 << ep->epnumber);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) ep->buffer0ready = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) udc->write_fn(udc->addr, XUSB_BUFFREADY_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) (1 << (ep->epnumber +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) XUSB_STATUS_EP_BUFF2_SHIFT)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) ep->buffer1ready = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) * xudc_ep_enable - Enables the given endpoint.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) * @_ep: pointer to the usb endpoint structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) * @desc: pointer to usb endpoint descriptor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) * Return: 0 for success and error value on failure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) static int xudc_ep_enable(struct usb_ep *_ep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) const struct usb_endpoint_descriptor *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) struct xusb_ep *ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) struct xusb_udc *udc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) if (!_ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) pr_debug("%s: bad ep or descriptor\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) ep = to_xusb_ep(_ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) udc = ep->udc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) dev_dbg(udc->dev, "bogus device state\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) return -ESHUTDOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) spin_lock_irqsave(&udc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) ret = __xudc_ep_enable(ep, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) spin_unlock_irqrestore(&udc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) * xudc_ep_disable - Disables the given endpoint.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) * @_ep: pointer to the usb endpoint structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) * Return: 0 for success and error value on failure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) static int xudc_ep_disable(struct usb_ep *_ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) struct xusb_ep *ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) u32 epcfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) struct xusb_udc *udc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) if (!_ep) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) pr_debug("%s: invalid ep\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) ep = to_xusb_ep(_ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) udc = ep->udc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) spin_lock_irqsave(&udc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) xudc_nuke(ep, -ESHUTDOWN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) /* Restore the endpoint's pristine config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) ep->desc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) ep->ep_usb.desc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) dev_dbg(udc->dev, "USB Ep %d disable\n ", ep->epnumber);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) /* Disable the endpoint.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) epcfg = udc->read_fn(udc->addr + ep->offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) epcfg &= ~XUSB_EP_CFG_VALID_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) udc->write_fn(udc->addr, ep->offset, epcfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) spin_unlock_irqrestore(&udc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) * xudc_ep_alloc_request - Initializes the request queue.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) * @_ep: pointer to the usb endpoint structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) * @gfp_flags: Flags related to the request call.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) * Return: pointer to request structure on success and a NULL on failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) static struct usb_request *xudc_ep_alloc_request(struct usb_ep *_ep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) gfp_t gfp_flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) struct xusb_ep *ep = to_xusb_ep(_ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) struct xusb_req *req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) req = kzalloc(sizeof(*req), gfp_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) if (!req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) req->ep = ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) INIT_LIST_HEAD(&req->queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) return &req->usb_req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) * xudc_free_request - Releases the request from queue.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) * @_ep: pointer to the usb device endpoint structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) * @_req: pointer to the usb request structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) static void xudc_free_request(struct usb_ep *_ep, struct usb_request *_req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) struct xusb_req *req = to_xusb_req(_req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) kfree(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) * xudc_ep0_queue - Adds the request to endpoint 0 queue.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) * @ep0: pointer to the xusb endpoint 0 structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) * @req: pointer to the xusb request structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) * Return: 0 for success and error value on failure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) static int __xudc_ep0_queue(struct xusb_ep *ep0, struct xusb_req *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) struct xusb_udc *udc = ep0->udc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) u32 length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) u8 *corebuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) dev_dbg(udc->dev, "%s, bogus device state\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) if (!list_empty(&ep0->queue)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) dev_dbg(udc->dev, "%s:ep0 busy\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) req->usb_req.status = -EINPROGRESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) req->usb_req.actual = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) list_add_tail(&req->queue, &ep0->queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) if (udc->setup.bRequestType & USB_DIR_IN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) prefetch(req->usb_req.buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) length = req->usb_req.length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) corebuf = (void __force *) ((ep0->rambase << 2) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) udc->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) length = req->usb_req.actual = min_t(u32, length,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) EP0_MAX_PACKET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) memcpy(corebuf, req->usb_req.buf, length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) udc->write_fn(udc->addr, XUSB_EP_BUF0COUNT_OFFSET, length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) udc->write_fn(udc->addr, XUSB_BUFFREADY_OFFSET, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) if (udc->setup.wLength) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) /* Enable EP0 buffer to receive data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) udc->write_fn(udc->addr, XUSB_EP_BUF0COUNT_OFFSET, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) udc->write_fn(udc->addr, XUSB_BUFFREADY_OFFSET, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) xudc_wrstatus(udc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) * xudc_ep0_queue - Adds the request to endpoint 0 queue.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) * @_ep: pointer to the usb endpoint 0 structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) * @_req: pointer to the usb request structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) * @gfp_flags: Flags related to the request call.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) * Return: 0 for success and error value on failure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) static int xudc_ep0_queue(struct usb_ep *_ep, struct usb_request *_req,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) gfp_t gfp_flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) struct xusb_req *req = to_xusb_req(_req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) struct xusb_ep *ep0 = to_xusb_ep(_ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) struct xusb_udc *udc = ep0->udc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) spin_lock_irqsave(&udc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) ret = __xudc_ep0_queue(ep0, req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) spin_unlock_irqrestore(&udc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) * xudc_ep_queue - Adds the request to endpoint queue.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) * @_ep: pointer to the usb endpoint structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) * @_req: pointer to the usb request structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) * @gfp_flags: Flags related to the request call.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) * Return: 0 for success and error value on failure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) static int xudc_ep_queue(struct usb_ep *_ep, struct usb_request *_req,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) gfp_t gfp_flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) struct xusb_req *req = to_xusb_req(_req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) struct xusb_ep *ep = to_xusb_ep(_ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) struct xusb_udc *udc = ep->udc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) if (!ep->desc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) dev_dbg(udc->dev, "%s: queuing request to disabled %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) __func__, ep->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) return -ESHUTDOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) dev_dbg(udc->dev, "%s, bogus device state\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) spin_lock_irqsave(&udc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) _req->status = -EINPROGRESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) _req->actual = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) if (udc->dma_enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) ret = usb_gadget_map_request(&udc->gadget, &req->usb_req,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) ep->is_in);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) dev_dbg(udc->dev, "gadget_map failed ep%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) ep->epnumber);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) spin_unlock_irqrestore(&udc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) if (list_empty(&ep->queue)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) if (ep->is_in) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) dev_dbg(udc->dev, "xudc_write_fifo from ep_queue\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) if (!xudc_write_fifo(ep, req))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) req = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) dev_dbg(udc->dev, "xudc_read_fifo from ep_queue\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) if (!xudc_read_fifo(ep, req))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) req = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) if (req != NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) list_add_tail(&req->queue, &ep->queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) spin_unlock_irqrestore(&udc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) * xudc_ep_dequeue - Removes the request from the queue.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) * @_ep: pointer to the usb device endpoint structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) * @_req: pointer to the usb request structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) * Return: 0 for success and error value on failure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) static int xudc_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) struct xusb_ep *ep = to_xusb_ep(_ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) struct xusb_req *req = to_xusb_req(_req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) struct xusb_udc *udc = ep->udc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) spin_lock_irqsave(&udc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) /* Make sure it's actually queued on this endpoint */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) list_for_each_entry(req, &ep->queue, queue) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) if (&req->usb_req == _req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) if (&req->usb_req != _req) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) spin_unlock_irqrestore(&udc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) xudc_done(ep, req, -ECONNRESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) spin_unlock_irqrestore(&udc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) * xudc_ep0_enable - Enables the given endpoint.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) * @ep: pointer to the usb endpoint structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) * @desc: pointer to usb endpoint descriptor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) * Return: error always.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) * endpoint 0 enable should not be called by gadget layer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) static int xudc_ep0_enable(struct usb_ep *ep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) const struct usb_endpoint_descriptor *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) * xudc_ep0_disable - Disables the given endpoint.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) * @ep: pointer to the usb endpoint structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) * Return: error always.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) * endpoint 0 disable should not be called by gadget layer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) static int xudc_ep0_disable(struct usb_ep *ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) static const struct usb_ep_ops xusb_ep0_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) .enable = xudc_ep0_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) .disable = xudc_ep0_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) .alloc_request = xudc_ep_alloc_request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) .free_request = xudc_free_request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) .queue = xudc_ep0_queue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) .dequeue = xudc_ep_dequeue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) .set_halt = xudc_ep_set_halt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) static const struct usb_ep_ops xusb_ep_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) .enable = xudc_ep_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) .disable = xudc_ep_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) .alloc_request = xudc_ep_alloc_request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) .free_request = xudc_free_request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) .queue = xudc_ep_queue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) .dequeue = xudc_ep_dequeue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) .set_halt = xudc_ep_set_halt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) * xudc_get_frame - Reads the current usb frame number.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) * @gadget: pointer to the usb gadget structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) * Return: current frame number for success and error value on failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) static int xudc_get_frame(struct usb_gadget *gadget)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) struct xusb_udc *udc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) int frame;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) if (!gadget)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) udc = to_udc(gadget);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) frame = udc->read_fn(udc->addr + XUSB_FRAMENUM_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) return frame;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) * xudc_wakeup - Send remote wakeup signal to host
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) * @gadget: pointer to the usb gadget structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) * Return: 0 on success and error on failure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) static int xudc_wakeup(struct usb_gadget *gadget)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) struct xusb_udc *udc = to_udc(gadget);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) u32 crtlreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) int status = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) spin_lock_irqsave(&udc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) /* Remote wake up not enabled by host */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) if (!udc->remote_wkp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) crtlreg = udc->read_fn(udc->addr + XUSB_CONTROL_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) crtlreg |= XUSB_CONTROL_USB_RMTWAKE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) /* set remote wake up bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) udc->write_fn(udc->addr, XUSB_CONTROL_OFFSET, crtlreg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) * wait for a while and reset remote wake up bit since this bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) * is not cleared by HW after sending remote wakeup to host.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) mdelay(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) crtlreg &= ~XUSB_CONTROL_USB_RMTWAKE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) udc->write_fn(udc->addr, XUSB_CONTROL_OFFSET, crtlreg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) spin_unlock_irqrestore(&udc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) * xudc_pullup - start/stop USB traffic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) * @gadget: pointer to the usb gadget structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) * @is_on: flag to start or stop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) * Return: 0 always
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) * This function starts/stops SIE engine of IP based on is_on.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) static int xudc_pullup(struct usb_gadget *gadget, int is_on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) struct xusb_udc *udc = to_udc(gadget);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) u32 crtlreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) spin_lock_irqsave(&udc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) crtlreg = udc->read_fn(udc->addr + XUSB_CONTROL_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) if (is_on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) crtlreg |= XUSB_CONTROL_USB_READY_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) crtlreg &= ~XUSB_CONTROL_USB_READY_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) udc->write_fn(udc->addr, XUSB_CONTROL_OFFSET, crtlreg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) spin_unlock_irqrestore(&udc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) * xudc_eps_init - initialize endpoints.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) * @udc: pointer to the usb device controller structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) static void xudc_eps_init(struct xusb_udc *udc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) u32 ep_number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) INIT_LIST_HEAD(&udc->gadget.ep_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) for (ep_number = 0; ep_number < XUSB_MAX_ENDPOINTS; ep_number++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) struct xusb_ep *ep = &udc->ep[ep_number];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) if (ep_number) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) list_add_tail(&ep->ep_usb.ep_list,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) &udc->gadget.ep_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) usb_ep_set_maxpacket_limit(&ep->ep_usb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) (unsigned short) ~0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) snprintf(ep->name, EPNAME_SIZE, "ep%d", ep_number);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) ep->ep_usb.name = ep->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) ep->ep_usb.ops = &xusb_ep_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) ep->ep_usb.caps.type_iso = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) ep->ep_usb.caps.type_bulk = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) ep->ep_usb.caps.type_int = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) ep->ep_usb.name = ep0name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) usb_ep_set_maxpacket_limit(&ep->ep_usb, EP0_MAX_PACKET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) ep->ep_usb.ops = &xusb_ep0_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) ep->ep_usb.caps.type_control = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) ep->ep_usb.caps.dir_in = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) ep->ep_usb.caps.dir_out = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) ep->udc = udc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) ep->epnumber = ep_number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) ep->desc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) * The configuration register address offset between
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) * each endpoint is 0x10.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) ep->offset = XUSB_EP0_CONFIG_OFFSET + (ep_number * 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) ep->is_in = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) ep->is_iso = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) ep->maxpacket = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) xudc_epconfig(ep, udc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) /* Initialize one queue per endpoint */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) INIT_LIST_HEAD(&ep->queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) * xudc_stop_activity - Stops any further activity on the device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) * @udc: pointer to the usb device controller structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) static void xudc_stop_activity(struct xusb_udc *udc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) struct xusb_ep *ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) for (i = 0; i < XUSB_MAX_ENDPOINTS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) ep = &udc->ep[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) xudc_nuke(ep, -ESHUTDOWN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) * xudc_start - Starts the device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) * @gadget: pointer to the usb gadget structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) * @driver: pointer to gadget driver structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) * Return: zero on success and error on failure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) static int xudc_start(struct usb_gadget *gadget,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) struct usb_gadget_driver *driver)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) struct xusb_udc *udc = to_udc(gadget);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) struct xusb_ep *ep0 = &udc->ep[XUSB_EP_NUMBER_ZERO];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) const struct usb_endpoint_descriptor *desc = &config_bulk_out_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) spin_lock_irqsave(&udc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) if (udc->driver) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) dev_err(udc->dev, "%s is already bound to %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) udc->gadget.name, udc->driver->driver.name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) ret = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) /* hook up the driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) udc->driver = driver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) udc->gadget.speed = driver->max_speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) /* Enable the control endpoint. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) ret = __xudc_ep_enable(ep0, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) /* Set device address and remote wakeup to 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) udc->write_fn(udc->addr, XUSB_ADDRESS_OFFSET, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) udc->remote_wkp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) spin_unlock_irqrestore(&udc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) * xudc_stop - stops the device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) * @gadget: pointer to the usb gadget structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) * Return: zero always
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) static int xudc_stop(struct usb_gadget *gadget)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) struct xusb_udc *udc = to_udc(gadget);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) spin_lock_irqsave(&udc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) udc->gadget.speed = USB_SPEED_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) udc->driver = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) /* Set device address and remote wakeup to 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) udc->write_fn(udc->addr, XUSB_ADDRESS_OFFSET, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) udc->remote_wkp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) xudc_stop_activity(udc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) spin_unlock_irqrestore(&udc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) static const struct usb_gadget_ops xusb_udc_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) .get_frame = xudc_get_frame,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) .wakeup = xudc_wakeup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) .pullup = xudc_pullup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) .udc_start = xudc_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) .udc_stop = xudc_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) * xudc_clear_stall_all_ep - clears stall of every endpoint.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) * @udc: pointer to the udc structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) static void xudc_clear_stall_all_ep(struct xusb_udc *udc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) struct xusb_ep *ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) u32 epcfgreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) for (i = 0; i < XUSB_MAX_ENDPOINTS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) ep = &udc->ep[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) epcfgreg = udc->read_fn(udc->addr + ep->offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) epcfgreg &= ~XUSB_EP_CFG_STALL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) udc->write_fn(udc->addr, ep->offset, epcfgreg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) if (ep->epnumber) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) /* Reset the toggle bit.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) epcfgreg = udc->read_fn(udc->addr + ep->offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) epcfgreg &= ~XUSB_EP_CFG_DATA_TOGGLE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) udc->write_fn(udc->addr, ep->offset, epcfgreg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) * xudc_startup_handler - The usb device controller interrupt handler.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) * @udc: pointer to the udc structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) * @intrstatus: The mask value containing the interrupt sources.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) * This function handles the RESET,SUSPEND,RESUME and DISCONNECT interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) static void xudc_startup_handler(struct xusb_udc *udc, u32 intrstatus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) u32 intrreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) if (intrstatus & XUSB_STATUS_RESET_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) dev_dbg(udc->dev, "Reset\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) if (intrstatus & XUSB_STATUS_HIGH_SPEED_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) udc->gadget.speed = USB_SPEED_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) udc->gadget.speed = USB_SPEED_FULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) xudc_stop_activity(udc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) xudc_clear_stall_all_ep(udc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) udc->write_fn(udc->addr, XUSB_TESTMODE_OFFSET, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) /* Set device address and remote wakeup to 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) udc->write_fn(udc->addr, XUSB_ADDRESS_OFFSET, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) udc->remote_wkp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) /* Enable the suspend, resume and disconnect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) intrreg = udc->read_fn(udc->addr + XUSB_IER_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) intrreg |= XUSB_STATUS_SUSPEND_MASK | XUSB_STATUS_RESUME_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) XUSB_STATUS_DISCONNECT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) udc->write_fn(udc->addr, XUSB_IER_OFFSET, intrreg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) if (intrstatus & XUSB_STATUS_SUSPEND_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) dev_dbg(udc->dev, "Suspend\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) /* Enable the reset, resume and disconnect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) intrreg = udc->read_fn(udc->addr + XUSB_IER_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) intrreg |= XUSB_STATUS_RESET_MASK | XUSB_STATUS_RESUME_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) XUSB_STATUS_DISCONNECT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) udc->write_fn(udc->addr, XUSB_IER_OFFSET, intrreg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) udc->usb_state = USB_STATE_SUSPENDED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) if (udc->driver->suspend) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) spin_unlock(&udc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) udc->driver->suspend(&udc->gadget);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) spin_lock(&udc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) if (intrstatus & XUSB_STATUS_RESUME_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) bool condition = (udc->usb_state != USB_STATE_SUSPENDED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) dev_WARN_ONCE(udc->dev, condition,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) "Resume IRQ while not suspended\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) dev_dbg(udc->dev, "Resume\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) /* Enable the reset, suspend and disconnect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) intrreg = udc->read_fn(udc->addr + XUSB_IER_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) intrreg |= XUSB_STATUS_RESET_MASK | XUSB_STATUS_SUSPEND_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) XUSB_STATUS_DISCONNECT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) udc->write_fn(udc->addr, XUSB_IER_OFFSET, intrreg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) udc->usb_state = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) if (udc->driver->resume) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) spin_unlock(&udc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) udc->driver->resume(&udc->gadget);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) spin_lock(&udc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) if (intrstatus & XUSB_STATUS_DISCONNECT_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) dev_dbg(udc->dev, "Disconnect\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) /* Enable the reset, resume and suspend */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) intrreg = udc->read_fn(udc->addr + XUSB_IER_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) intrreg |= XUSB_STATUS_RESET_MASK | XUSB_STATUS_RESUME_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) XUSB_STATUS_SUSPEND_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) udc->write_fn(udc->addr, XUSB_IER_OFFSET, intrreg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) if (udc->driver && udc->driver->disconnect) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) spin_unlock(&udc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) udc->driver->disconnect(&udc->gadget);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) spin_lock(&udc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) * xudc_ep0_stall - Stall endpoint zero.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) * @udc: pointer to the udc structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) * This function stalls endpoint zero.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) static void xudc_ep0_stall(struct xusb_udc *udc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) u32 epcfgreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) struct xusb_ep *ep0 = &udc->ep[XUSB_EP_NUMBER_ZERO];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) epcfgreg = udc->read_fn(udc->addr + ep0->offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) epcfgreg |= XUSB_EP_CFG_STALL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) udc->write_fn(udc->addr, ep0->offset, epcfgreg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) * xudc_setaddress - executes SET_ADDRESS command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) * @udc: pointer to the udc structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) * This function executes USB SET_ADDRESS command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) static void xudc_setaddress(struct xusb_udc *udc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) struct xusb_ep *ep0 = &udc->ep[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) struct xusb_req *req = udc->req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) req->usb_req.length = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) ret = __xudc_ep0_queue(ep0, req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) if (ret == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) dev_err(udc->dev, "Can't respond to SET ADDRESS request\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) xudc_ep0_stall(udc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) * xudc_getstatus - executes GET_STATUS command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) * @udc: pointer to the udc structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) * This function executes USB GET_STATUS command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) static void xudc_getstatus(struct xusb_udc *udc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) struct xusb_ep *ep0 = &udc->ep[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) struct xusb_req *req = udc->req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) struct xusb_ep *target_ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) u16 status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) u32 epcfgreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) int epnum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) u32 halt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) switch (udc->setup.bRequestType & USB_RECIP_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) case USB_RECIP_DEVICE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) /* Get device status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) status = 1 << USB_DEVICE_SELF_POWERED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) if (udc->remote_wkp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) status |= (1 << USB_DEVICE_REMOTE_WAKEUP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) case USB_RECIP_INTERFACE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) case USB_RECIP_ENDPOINT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) epnum = udc->setup.wIndex & USB_ENDPOINT_NUMBER_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) if (epnum >= XUSB_MAX_ENDPOINTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) goto stall;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) target_ep = &udc->ep[epnum];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) epcfgreg = udc->read_fn(udc->addr + target_ep->offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) halt = epcfgreg & XUSB_EP_CFG_STALL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) if (udc->setup.wIndex & USB_DIR_IN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) if (!target_ep->is_in)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) goto stall;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) if (target_ep->is_in)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) goto stall;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) if (halt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) status = 1 << USB_ENDPOINT_HALT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) goto stall;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) req->usb_req.length = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) *(u16 *)req->usb_req.buf = cpu_to_le16(status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) ret = __xudc_ep0_queue(ep0, req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) if (ret == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) stall:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) dev_err(udc->dev, "Can't respond to getstatus request\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) xudc_ep0_stall(udc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) * xudc_set_clear_feature - Executes the set feature and clear feature commands.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) * @udc: pointer to the usb device controller structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) * Processes the SET_FEATURE and CLEAR_FEATURE commands.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) static void xudc_set_clear_feature(struct xusb_udc *udc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) struct xusb_ep *ep0 = &udc->ep[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) struct xusb_req *req = udc->req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) struct xusb_ep *target_ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) u8 endpoint;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) u8 outinbit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) u32 epcfgreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) int flag = (udc->setup.bRequest == USB_REQ_SET_FEATURE ? 1 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) switch (udc->setup.bRequestType) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) case USB_RECIP_DEVICE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) switch (udc->setup.wValue) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) case USB_DEVICE_TEST_MODE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) * The Test Mode will be executed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) * after the status phase.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) case USB_DEVICE_REMOTE_WAKEUP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) if (flag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) udc->remote_wkp = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) udc->remote_wkp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) xudc_ep0_stall(udc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) case USB_RECIP_ENDPOINT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) if (!udc->setup.wValue) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) endpoint = udc->setup.wIndex & USB_ENDPOINT_NUMBER_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) if (endpoint >= XUSB_MAX_ENDPOINTS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) xudc_ep0_stall(udc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) target_ep = &udc->ep[endpoint];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) outinbit = udc->setup.wIndex & USB_ENDPOINT_DIR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) outinbit = outinbit >> 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) /* Make sure direction matches.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) if (outinbit != target_ep->is_in) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) xudc_ep0_stall(udc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) epcfgreg = udc->read_fn(udc->addr + target_ep->offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) if (!endpoint) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) /* Clear the stall.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) epcfgreg &= ~XUSB_EP_CFG_STALL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) udc->write_fn(udc->addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) target_ep->offset, epcfgreg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) if (flag) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) epcfgreg |= XUSB_EP_CFG_STALL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) udc->write_fn(udc->addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) target_ep->offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) epcfgreg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) /* Unstall the endpoint.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) epcfgreg &= ~(XUSB_EP_CFG_STALL_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) XUSB_EP_CFG_DATA_TOGGLE_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) udc->write_fn(udc->addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) target_ep->offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) epcfgreg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) xudc_ep0_stall(udc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) req->usb_req.length = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) ret = __xudc_ep0_queue(ep0, req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) if (ret == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) dev_err(udc->dev, "Can't respond to SET/CLEAR FEATURE\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) xudc_ep0_stall(udc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) * xudc_handle_setup - Processes the setup packet.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) * @udc: pointer to the usb device controller structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) * Process setup packet and delegate to gadget layer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) static void xudc_handle_setup(struct xusb_udc *udc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) __must_hold(&udc->lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) struct xusb_ep *ep0 = &udc->ep[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) struct usb_ctrlrequest setup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) u32 *ep0rambase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) /* Load up the chapter 9 command buffer.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) ep0rambase = (u32 __force *) (udc->addr + XUSB_SETUP_PKT_ADDR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) memcpy(&setup, ep0rambase, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) udc->setup = setup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) udc->setup.wValue = cpu_to_le16(setup.wValue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) udc->setup.wIndex = cpu_to_le16(setup.wIndex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) udc->setup.wLength = cpu_to_le16(setup.wLength);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) /* Clear previous requests */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) xudc_nuke(ep0, -ECONNRESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) if (udc->setup.bRequestType & USB_DIR_IN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) /* Execute the get command.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) udc->setupseqrx = STATUS_PHASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) udc->setupseqtx = DATA_PHASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) /* Execute the put command.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) udc->setupseqrx = DATA_PHASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) udc->setupseqtx = STATUS_PHASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) switch (udc->setup.bRequest) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) case USB_REQ_GET_STATUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) /* Data+Status phase form udc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) if ((udc->setup.bRequestType &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) (USB_DIR_IN | USB_TYPE_MASK)) !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) (USB_DIR_IN | USB_TYPE_STANDARD))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) xudc_getstatus(udc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) case USB_REQ_SET_ADDRESS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) /* Status phase from udc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) if (udc->setup.bRequestType != (USB_DIR_OUT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) USB_TYPE_STANDARD | USB_RECIP_DEVICE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) xudc_setaddress(udc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) case USB_REQ_CLEAR_FEATURE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) case USB_REQ_SET_FEATURE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) /* Requests with no data phase, status phase from udc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) if ((udc->setup.bRequestType & USB_TYPE_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) != USB_TYPE_STANDARD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) xudc_set_clear_feature(udc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) spin_unlock(&udc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) if (udc->driver->setup(&udc->gadget, &setup) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) xudc_ep0_stall(udc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) spin_lock(&udc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) * xudc_ep0_out - Processes the endpoint 0 OUT token.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) * @udc: pointer to the usb device controller structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) static void xudc_ep0_out(struct xusb_udc *udc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) struct xusb_ep *ep0 = &udc->ep[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) struct xusb_req *req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) u8 *ep0rambase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) unsigned int bytes_to_rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) void *buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) req = list_first_entry(&ep0->queue, struct xusb_req, queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) switch (udc->setupseqrx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) case STATUS_PHASE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) * This resets both state machines for the next
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) * Setup packet.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) udc->setupseqrx = SETUP_PHASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) udc->setupseqtx = SETUP_PHASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) req->usb_req.actual = req->usb_req.length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) xudc_done(ep0, req, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) case DATA_PHASE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) bytes_to_rx = udc->read_fn(udc->addr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) XUSB_EP_BUF0COUNT_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) /* Copy the data to be received from the DPRAM. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) ep0rambase = (u8 __force *) (udc->addr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) (ep0->rambase << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) buffer = req->usb_req.buf + req->usb_req.actual;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) req->usb_req.actual = req->usb_req.actual + bytes_to_rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) memcpy(buffer, ep0rambase, bytes_to_rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) if (req->usb_req.length == req->usb_req.actual) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) /* Data transfer completed get ready for Status stage */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) xudc_wrstatus(udc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) /* Enable EP0 buffer to receive data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) udc->write_fn(udc->addr, XUSB_EP_BUF0COUNT_OFFSET, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) udc->write_fn(udc->addr, XUSB_BUFFREADY_OFFSET, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) * xudc_ep0_in - Processes the endpoint 0 IN token.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) * @udc: pointer to the usb device controller structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) static void xudc_ep0_in(struct xusb_udc *udc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) struct xusb_ep *ep0 = &udc->ep[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) struct xusb_req *req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) unsigned int bytes_to_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) void *buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) u32 epcfgreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) u16 count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) u16 length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) u8 *ep0rambase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) u8 test_mode = udc->setup.wIndex >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) req = list_first_entry(&ep0->queue, struct xusb_req, queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) bytes_to_tx = req->usb_req.length - req->usb_req.actual;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) switch (udc->setupseqtx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) case STATUS_PHASE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) switch (udc->setup.bRequest) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) case USB_REQ_SET_ADDRESS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) /* Set the address of the device.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) udc->write_fn(udc->addr, XUSB_ADDRESS_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) udc->setup.wValue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) case USB_REQ_SET_FEATURE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) if (udc->setup.bRequestType ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) USB_RECIP_DEVICE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) if (udc->setup.wValue ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) USB_DEVICE_TEST_MODE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) udc->write_fn(udc->addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) XUSB_TESTMODE_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) test_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) req->usb_req.actual = req->usb_req.length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) xudc_done(ep0, req, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) case DATA_PHASE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) if (!bytes_to_tx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) * We're done with data transfer, next
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) * will be zero length OUT with data toggle of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) * 1. Setup data_toggle.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) epcfgreg = udc->read_fn(udc->addr + ep0->offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) epcfgreg |= XUSB_EP_CFG_DATA_TOGGLE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) udc->write_fn(udc->addr, ep0->offset, epcfgreg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) udc->setupseqtx = STATUS_PHASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) length = count = min_t(u32, bytes_to_tx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) EP0_MAX_PACKET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) /* Copy the data to be transmitted into the DPRAM. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) ep0rambase = (u8 __force *) (udc->addr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) (ep0->rambase << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) buffer = req->usb_req.buf + req->usb_req.actual;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) req->usb_req.actual = req->usb_req.actual + length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) memcpy(ep0rambase, buffer, length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) udc->write_fn(udc->addr, XUSB_EP_BUF0COUNT_OFFSET, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) udc->write_fn(udc->addr, XUSB_BUFFREADY_OFFSET, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) * xudc_ctrl_ep_handler - Endpoint 0 interrupt handler.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) * @udc: pointer to the udc structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) * @intrstatus: It's the mask value for the interrupt sources on endpoint 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) * Processes the commands received during enumeration phase.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) static void xudc_ctrl_ep_handler(struct xusb_udc *udc, u32 intrstatus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) if (intrstatus & XUSB_STATUS_SETUP_PACKET_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) xudc_handle_setup(udc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) if (intrstatus & XUSB_STATUS_FIFO_BUFF_RDY_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) xudc_ep0_out(udc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) else if (intrstatus & XUSB_STATUS_FIFO_BUFF_FREE_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) xudc_ep0_in(udc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) * xudc_nonctrl_ep_handler - Non control endpoint interrupt handler.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) * @udc: pointer to the udc structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) * @epnum: End point number for which the interrupt is to be processed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) * @intrstatus: mask value for interrupt sources of endpoints other
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) * than endpoint 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) * Processes the buffer completion interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) static void xudc_nonctrl_ep_handler(struct xusb_udc *udc, u8 epnum,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) u32 intrstatus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) struct xusb_req *req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) struct xusb_ep *ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) ep = &udc->ep[epnum];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) /* Process the End point interrupts.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) if (intrstatus & (XUSB_STATUS_EP0_BUFF1_COMP_MASK << epnum))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) ep->buffer0ready = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) if (intrstatus & (XUSB_STATUS_EP0_BUFF2_COMP_MASK << epnum))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) ep->buffer1ready = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) if (list_empty(&ep->queue))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) req = list_first_entry(&ep->queue, struct xusb_req, queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) if (ep->is_in)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) xudc_write_fifo(ep, req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) xudc_read_fifo(ep, req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) * xudc_irq - The main interrupt handler.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) * @irq: The interrupt number.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) * @_udc: pointer to the usb device controller structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) * Return: IRQ_HANDLED after the interrupt is handled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) static irqreturn_t xudc_irq(int irq, void *_udc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) struct xusb_udc *udc = _udc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) u32 intrstatus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) u32 ier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) u8 index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) u32 bufintr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) spin_lock_irqsave(&udc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) * Event interrupts are level sensitive hence first disable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) * IER, read ISR and figure out active interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) ier = udc->read_fn(udc->addr + XUSB_IER_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) ier &= ~XUSB_STATUS_INTR_EVENT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) udc->write_fn(udc->addr, XUSB_IER_OFFSET, ier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) /* Read the Interrupt Status Register.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) intrstatus = udc->read_fn(udc->addr + XUSB_STATUS_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) /* Call the handler for the event interrupt.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) if (intrstatus & XUSB_STATUS_INTR_EVENT_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) * Check if there is any action to be done for :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) * - USB Reset received {XUSB_STATUS_RESET_MASK}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) * - USB Suspend received {XUSB_STATUS_SUSPEND_MASK}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) * - USB Resume received {XUSB_STATUS_RESUME_MASK}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) * - USB Disconnect received {XUSB_STATUS_DISCONNECT_MASK}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) xudc_startup_handler(udc, intrstatus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) /* Check the buffer completion interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) if (intrstatus & XUSB_STATUS_INTR_BUFF_COMP_ALL_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) /* Enable Reset, Suspend, Resume and Disconnect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) ier = udc->read_fn(udc->addr + XUSB_IER_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) ier |= XUSB_STATUS_INTR_EVENT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) udc->write_fn(udc->addr, XUSB_IER_OFFSET, ier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) if (intrstatus & XUSB_STATUS_EP0_BUFF1_COMP_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) xudc_ctrl_ep_handler(udc, intrstatus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) for (index = 1; index < 8; index++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) bufintr = ((intrstatus &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) (XUSB_STATUS_EP1_BUFF1_COMP_MASK <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) (index - 1))) || (intrstatus &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) (XUSB_STATUS_EP1_BUFF2_COMP_MASK <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) (index - 1))));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) if (bufintr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) xudc_nonctrl_ep_handler(udc, index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) intrstatus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) spin_unlock_irqrestore(&udc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) * xudc_probe - The device probe function for driver initialization.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) * @pdev: pointer to the platform device structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) * Return: 0 for success and error value on failure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) static int xudc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) struct xusb_udc *udc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) u32 ier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) u8 *buff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) udc = devm_kzalloc(&pdev->dev, sizeof(*udc), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) if (!udc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) /* Create a dummy request for GET_STATUS, SET_ADDRESS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) udc->req = devm_kzalloc(&pdev->dev, sizeof(struct xusb_req),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) if (!udc->req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) buff = devm_kzalloc(&pdev->dev, STATUSBUFF_SIZE, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) if (!buff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) udc->req->usb_req.buf = buff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) /* Map the registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) udc->addr = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) if (IS_ERR(udc->addr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) return PTR_ERR(udc->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) if (irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) ret = devm_request_irq(&pdev->dev, irq, xudc_irq, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) dev_name(&pdev->dev), udc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) dev_dbg(&pdev->dev, "unable to request irq %d", irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) udc->dma_enabled = of_property_read_bool(np, "xlnx,has-builtin-dma");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) /* Setup gadget structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) udc->gadget.ops = &xusb_udc_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) udc->gadget.max_speed = USB_SPEED_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) udc->gadget.speed = USB_SPEED_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) udc->gadget.ep0 = &udc->ep[XUSB_EP_NUMBER_ZERO].ep_usb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) udc->gadget.name = driver_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) spin_lock_init(&udc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) /* Check for IP endianness */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) udc->write_fn = xudc_write32_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) udc->read_fn = xudc_read32_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) udc->write_fn(udc->addr, XUSB_TESTMODE_OFFSET, USB_TEST_J);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) if ((udc->read_fn(udc->addr + XUSB_TESTMODE_OFFSET))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) != USB_TEST_J) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) udc->write_fn = xudc_write32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) udc->read_fn = xudc_read32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) udc->write_fn(udc->addr, XUSB_TESTMODE_OFFSET, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) xudc_eps_init(udc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) /* Set device address to 0.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) udc->write_fn(udc->addr, XUSB_ADDRESS_OFFSET, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) ret = usb_add_gadget_udc(&pdev->dev, &udc->gadget);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) udc->dev = &udc->gadget.dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) /* Enable the interrupts.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) ier = XUSB_STATUS_GLOBAL_INTR_MASK | XUSB_STATUS_INTR_EVENT_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) XUSB_STATUS_FIFO_BUFF_RDY_MASK | XUSB_STATUS_FIFO_BUFF_FREE_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) XUSB_STATUS_SETUP_PACKET_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) XUSB_STATUS_INTR_BUFF_COMP_ALL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) udc->write_fn(udc->addr, XUSB_IER_OFFSET, ier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) platform_set_drvdata(pdev, udc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) dev_vdbg(&pdev->dev, "%s at 0x%08X mapped to %p %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) driver_name, (u32)res->start, udc->addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) udc->dma_enabled ? "with DMA" : "without DMA");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) dev_err(&pdev->dev, "probe failed, %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) * xudc_remove - Releases the resources allocated during the initialization.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) * @pdev: pointer to the platform device structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) * Return: 0 always
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) static int xudc_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) struct xusb_udc *udc = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) usb_del_gadget_udc(&udc->gadget);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) /* Match table for of_platform binding */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) static const struct of_device_id usb_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) { .compatible = "xlnx,usb2-device-4.00.a", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) { /* end of list */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) MODULE_DEVICE_TABLE(of, usb_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) static struct platform_driver xudc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) .name = driver_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) .of_match_table = usb_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) .probe = xudc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) .remove = xudc_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) module_platform_driver(xudc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) MODULE_DESCRIPTION("Xilinx udc driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) MODULE_AUTHOR("Xilinx, Inc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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