^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * NVIDIA Tegra XUSB device mode controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2013-2019, NVIDIA CORPORATION. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (c) 2015, Google Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/completion.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/dmapool.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/iopoll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/phy/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/phy/tegra/xusb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/pm_domain.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/usb/ch9.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/usb/gadget.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/usb/otg.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/usb/role.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/usb/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/workqueue.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /* XUSB_DEV registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define SPARAM 0x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SPARAM_ERSTMAX_MASK GENMASK(20, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define SPARAM_ERSTMAX(x) (((x) << 16) & SPARAM_ERSTMAX_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define DB 0x004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define DB_TARGET_MASK GENMASK(15, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define DB_TARGET(x) (((x) << 8) & DB_TARGET_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define DB_STREAMID_MASK GENMASK(31, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define DB_STREAMID(x) (((x) << 16) & DB_STREAMID_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define ERSTSZ 0x008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define ERSTSZ_ERSTXSZ_SHIFT(x) ((x) * 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define ERSTSZ_ERSTXSZ_MASK GENMASK(15, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define ERSTXBALO(x) (0x010 + 8 * (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define ERSTXBAHI(x) (0x014 + 8 * (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define ERDPLO 0x020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define ERDPLO_EHB BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define ERDPHI 0x024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define EREPLO 0x028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define EREPLO_ECS BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define EREPLO_SEGI BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define EREPHI 0x02c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define CTRL 0x030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define CTRL_RUN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define CTRL_LSE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define CTRL_IE BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define CTRL_SMI_EVT BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define CTRL_SMI_DSE BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define CTRL_EWE BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define CTRL_DEVADDR_MASK GENMASK(30, 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define CTRL_DEVADDR(x) (((x) << 24) & CTRL_DEVADDR_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define CTRL_ENABLE BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define ST 0x034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define ST_RC BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define ST_IP BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define RT_IMOD 0x038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define RT_IMOD_IMODI_MASK GENMASK(15, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define RT_IMOD_IMODI(x) ((x) & RT_IMOD_IMODI_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define RT_IMOD_IMODC_MASK GENMASK(31, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define RT_IMOD_IMODC(x) (((x) << 16) & RT_IMOD_IMODC_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define PORTSC 0x03c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define PORTSC_CCS BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define PORTSC_PED BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define PORTSC_PR BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define PORTSC_PLS_SHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define PORTSC_PLS_MASK GENMASK(8, 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define PORTSC_PLS_U0 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define PORTSC_PLS_U2 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define PORTSC_PLS_U3 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define PORTSC_PLS_DISABLED 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define PORTSC_PLS_RXDETECT 0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define PORTSC_PLS_INACTIVE 0x6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define PORTSC_PLS_RESUME 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define PORTSC_PLS(x) (((x) << PORTSC_PLS_SHIFT) & PORTSC_PLS_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define PORTSC_PS_SHIFT 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define PORTSC_PS_MASK GENMASK(13, 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define PORTSC_PS_UNDEFINED 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define PORTSC_PS_FS 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define PORTSC_PS_LS 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define PORTSC_PS_HS 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define PORTSC_PS_SS 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define PORTSC_LWS BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define PORTSC_CSC BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define PORTSC_WRC BIT(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define PORTSC_PRC BIT(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define PORTSC_PLC BIT(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define PORTSC_CEC BIT(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define PORTSC_WPR BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define PORTSC_CHANGE_MASK (PORTSC_CSC | PORTSC_WRC | PORTSC_PRC | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) PORTSC_PLC | PORTSC_CEC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define ECPLO 0x040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define ECPHI 0x044
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define MFINDEX 0x048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define MFINDEX_FRAME_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define MFINDEX_FRAME_MASK GENMASK(13, 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define PORTPM 0x04c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define PORTPM_L1S_MASK GENMASK(1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define PORTPM_L1S_DROP 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define PORTPM_L1S_ACCEPT 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define PORTPM_L1S_NYET 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define PORTPM_L1S_STALL 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define PORTPM_L1S(x) ((x) & PORTPM_L1S_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define PORTPM_RWE BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define PORTPM_U2TIMEOUT_MASK GENMASK(15, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define PORTPM_U1TIMEOUT_MASK GENMASK(23, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define PORTPM_FLA BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define PORTPM_VBA BIT(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define PORTPM_WOC BIT(26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define PORTPM_WOD BIT(27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define PORTPM_U1E BIT(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define PORTPM_U2E BIT(29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define PORTPM_FRWE BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define PORTPM_PNG_CYA BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define EP_HALT 0x050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define EP_PAUSE 0x054
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define EP_RELOAD 0x058
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define EP_STCHG 0x05c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define DEVNOTIF_LO 0x064
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define DEVNOTIF_LO_TRIG BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define DEVNOTIF_LO_TYPE_MASK GENMASK(7, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define DEVNOTIF_LO_TYPE(x) (((x) << 4) & DEVNOTIF_LO_TYPE_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define DEVNOTIF_LO_TYPE_FUNCTION_WAKE 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define DEVNOTIF_HI 0x068
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define PORTHALT 0x06c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define PORTHALT_HALT_LTSSM BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define PORTHALT_HALT_REJECT BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define PORTHALT_STCHG_REQ BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define PORTHALT_STCHG_INTR_EN BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define PORT_TM 0x070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define EP_THREAD_ACTIVE 0x074
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define EP_STOPPED 0x078
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define HSFSPI_COUNT0 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define HSFSPI_COUNT13 0x134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define HSFSPI_COUNT13_U2_RESUME_K_DURATION_MASK GENMASK(29, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define HSFSPI_COUNT13_U2_RESUME_K_DURATION(x) ((x) & \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) HSFSPI_COUNT13_U2_RESUME_K_DURATION_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define BLCG 0x840
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define SSPX_CORE_CNT0 0x610
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define SSPX_CORE_CNT0_PING_TBURST_MASK GENMASK(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define SSPX_CORE_CNT0_PING_TBURST(x) ((x) & SSPX_CORE_CNT0_PING_TBURST_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define SSPX_CORE_CNT30 0x688
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define SSPX_CORE_CNT30_LMPITP_TIMER_MASK GENMASK(19, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define SSPX_CORE_CNT30_LMPITP_TIMER(x) ((x) & \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) SSPX_CORE_CNT30_LMPITP_TIMER_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define SSPX_CORE_CNT32 0x690
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define SSPX_CORE_CNT32_POLL_TBURST_MAX_MASK GENMASK(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define SSPX_CORE_CNT32_POLL_TBURST_MAX(x) ((x) & \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) SSPX_CORE_CNT32_POLL_TBURST_MAX_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define SSPX_CORE_CNT56 0x6fc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define SSPX_CORE_CNT56_SCD_BIT0_TRPT_MAX_MASK GENMASK(19, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define SSPX_CORE_CNT56_SCD_BIT0_TRPT_MAX(x) ((x) & \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) SSPX_CORE_CNT56_SCD_BIT0_TRPT_MAX_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define SSPX_CORE_CNT57 0x700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define SSPX_CORE_CNT57_SCD_BIT1_TRPT_MAX_MASK GENMASK(19, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define SSPX_CORE_CNT57_SCD_BIT1_TRPT_MAX(x) ((x) & \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) SSPX_CORE_CNT57_SCD_BIT1_TRPT_MAX_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define SSPX_CORE_CNT65 0x720
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define SSPX_CORE_CNT65_TX_SCD_END_TRPT_MID_MASK GENMASK(19, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define SSPX_CORE_CNT65_TX_SCD_END_TRPT_MID(x) ((x) & \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) SSPX_CORE_CNT65_TX_SCD_END_TRPT_MID_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define SSPX_CORE_CNT66 0x724
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define SSPX_CORE_CNT66_TX_SCD_BIT0_TRPT_MID_MASK GENMASK(19, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define SSPX_CORE_CNT66_TX_SCD_BIT0_TRPT_MID(x) ((x) & \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) SSPX_CORE_CNT66_TX_SCD_BIT0_TRPT_MID_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define SSPX_CORE_CNT67 0x728
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define SSPX_CORE_CNT67_TX_SCD_BIT1_TRPT_MID_MASK GENMASK(19, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define SSPX_CORE_CNT67_TX_SCD_BIT1_TRPT_MID(x) ((x) & \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) SSPX_CORE_CNT67_TX_SCD_BIT1_TRPT_MID_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define SSPX_CORE_CNT72 0x73c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define SSPX_CORE_CNT72_SCD_LFPS_TIMEOUT_MASK GENMASK(19, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define SSPX_CORE_CNT72_SCD_LFPS_TIMEOUT(x) ((x) & \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) SSPX_CORE_CNT72_SCD_LFPS_TIMEOUT_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define SSPX_CORE_PADCTL4 0x750
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define SSPX_CORE_PADCTL4_RXDAT_VLD_TIMEOUT_U3_MASK GENMASK(19, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define SSPX_CORE_PADCTL4_RXDAT_VLD_TIMEOUT_U3(x) ((x) & \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) SSPX_CORE_PADCTL4_RXDAT_VLD_TIMEOUT_U3_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define BLCG_DFPCI BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define BLCG_UFPCI BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define BLCG_FE BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define BLCG_COREPLL_PWRDN BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define BLCG_IOPLL_0_PWRDN BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define BLCG_IOPLL_1_PWRDN BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define BLCG_IOPLL_2_PWRDN BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define BLCG_ALL 0x1ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define CFG_DEV_SSPI_XFER 0x858
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define CFG_DEV_SSPI_XFER_ACKTIMEOUT_MASK GENMASK(31, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define CFG_DEV_SSPI_XFER_ACKTIMEOUT(x) ((x) & \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) CFG_DEV_SSPI_XFER_ACKTIMEOUT_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define CFG_DEV_FE 0x85c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define CFG_DEV_FE_PORTREGSEL_MASK GENMASK(1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define CFG_DEV_FE_PORTREGSEL_SS_PI 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define CFG_DEV_FE_PORTREGSEL_HSFS_PI 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define CFG_DEV_FE_PORTREGSEL(x) ((x) & CFG_DEV_FE_PORTREGSEL_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define CFG_DEV_FE_INFINITE_SS_RETRY BIT(29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) /* FPCI registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define XUSB_DEV_CFG_1 0x004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define XUSB_DEV_CFG_1_IO_SPACE_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define XUSB_DEV_CFG_1_MEMORY_SPACE_EN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define XUSB_DEV_CFG_1_BUS_MASTER_EN BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define XUSB_DEV_CFG_4 0x010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define XUSB_DEV_CFG_4_BASE_ADDR_MASK GENMASK(31, 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define XUSB_DEV_CFG_5 0x014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /* IPFS registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define XUSB_DEV_CONFIGURATION_0 0x180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define XUSB_DEV_CONFIGURATION_0_EN_FPCI BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define XUSB_DEV_INTR_MASK_0 0x188
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define XUSB_DEV_INTR_MASK_0_IP_INT_MASK BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) struct tegra_xudc_ep_context {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) __le32 info0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) __le32 info1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) __le32 deq_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) __le32 deq_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) __le32 tx_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) __le32 rsvd[11];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define EP_STATE_DISABLED 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define EP_STATE_RUNNING 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define EP_STATE_HALTED 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define EP_STATE_STOPPED 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define EP_STATE_ERROR 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define EP_TYPE_INVALID 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define EP_TYPE_ISOCH_OUT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define EP_TYPE_BULK_OUT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define EP_TYPE_INTERRUPT_OUT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define EP_TYPE_CONTROL 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define EP_TYPE_ISCOH_IN 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define EP_TYPE_BULK_IN 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define EP_TYPE_INTERRUPT_IN 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define BUILD_EP_CONTEXT_RW(name, member, shift, mask) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) static inline u32 ep_ctx_read_##name(struct tegra_xudc_ep_context *ctx) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) return (le32_to_cpu(ctx->member) >> (shift)) & (mask); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) static inline void \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) ep_ctx_write_##name(struct tegra_xudc_ep_context *ctx, u32 val) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) u32 tmp; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) tmp = le32_to_cpu(ctx->member) & ~((mask) << (shift)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) tmp |= (val & (mask)) << (shift); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) ctx->member = cpu_to_le32(tmp); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) BUILD_EP_CONTEXT_RW(state, info0, 0, 0x7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) BUILD_EP_CONTEXT_RW(mult, info0, 8, 0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) BUILD_EP_CONTEXT_RW(max_pstreams, info0, 10, 0x1f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) BUILD_EP_CONTEXT_RW(lsa, info0, 15, 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) BUILD_EP_CONTEXT_RW(interval, info0, 16, 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) BUILD_EP_CONTEXT_RW(cerr, info1, 1, 0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) BUILD_EP_CONTEXT_RW(type, info1, 3, 0x7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) BUILD_EP_CONTEXT_RW(hid, info1, 7, 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) BUILD_EP_CONTEXT_RW(max_burst_size, info1, 8, 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) BUILD_EP_CONTEXT_RW(max_packet_size, info1, 16, 0xffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) BUILD_EP_CONTEXT_RW(dcs, deq_lo, 0, 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) BUILD_EP_CONTEXT_RW(deq_lo, deq_lo, 4, 0xfffffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) BUILD_EP_CONTEXT_RW(deq_hi, deq_hi, 0, 0xffffffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) BUILD_EP_CONTEXT_RW(avg_trb_len, tx_info, 0, 0xffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) BUILD_EP_CONTEXT_RW(max_esit_payload, tx_info, 16, 0xffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) BUILD_EP_CONTEXT_RW(edtla, rsvd[0], 0, 0xffffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) BUILD_EP_CONTEXT_RW(seq_num, rsvd[0], 24, 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) BUILD_EP_CONTEXT_RW(partial_td, rsvd[0], 25, 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) BUILD_EP_CONTEXT_RW(cerrcnt, rsvd[1], 18, 0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) BUILD_EP_CONTEXT_RW(data_offset, rsvd[2], 0, 0x1ffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) BUILD_EP_CONTEXT_RW(numtrbs, rsvd[2], 22, 0x1f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) BUILD_EP_CONTEXT_RW(devaddr, rsvd[6], 0, 0x7f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) static inline u64 ep_ctx_read_deq_ptr(struct tegra_xudc_ep_context *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) return ((u64)ep_ctx_read_deq_hi(ctx) << 32) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) (ep_ctx_read_deq_lo(ctx) << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) ep_ctx_write_deq_ptr(struct tegra_xudc_ep_context *ctx, u64 addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) ep_ctx_write_deq_lo(ctx, lower_32_bits(addr) >> 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) ep_ctx_write_deq_hi(ctx, upper_32_bits(addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) struct tegra_xudc_trb {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) __le32 data_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) __le32 data_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) __le32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) __le32 control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define TRB_TYPE_RSVD 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define TRB_TYPE_NORMAL 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define TRB_TYPE_SETUP_STAGE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define TRB_TYPE_DATA_STAGE 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define TRB_TYPE_STATUS_STAGE 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define TRB_TYPE_ISOCH 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define TRB_TYPE_LINK 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define TRB_TYPE_TRANSFER_EVENT 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define TRB_TYPE_PORT_STATUS_CHANGE_EVENT 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define TRB_TYPE_STREAM 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define TRB_TYPE_SETUP_PACKET_EVENT 63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define TRB_CMPL_CODE_INVALID 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define TRB_CMPL_CODE_SUCCESS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define TRB_CMPL_CODE_DATA_BUFFER_ERR 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define TRB_CMPL_CODE_BABBLE_DETECTED_ERR 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define TRB_CMPL_CODE_USB_TRANS_ERR 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define TRB_CMPL_CODE_TRB_ERR 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define TRB_CMPL_CODE_STALL 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define TRB_CMPL_CODE_INVALID_STREAM_TYPE_ERR 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define TRB_CMPL_CODE_SHORT_PACKET 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define TRB_CMPL_CODE_RING_UNDERRUN 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define TRB_CMPL_CODE_RING_OVERRUN 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define TRB_CMPL_CODE_EVENT_RING_FULL_ERR 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define TRB_CMPL_CODE_STOPPED 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define TRB_CMPL_CODE_ISOCH_BUFFER_OVERRUN 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define TRB_CMPL_CODE_STREAM_NUMP_ERROR 219
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define TRB_CMPL_CODE_PRIME_PIPE_RECEIVED 220
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define TRB_CMPL_CODE_HOST_REJECTED 221
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define TRB_CMPL_CODE_CTRL_DIR_ERR 222
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define TRB_CMPL_CODE_CTRL_SEQNUM_ERR 223
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define BUILD_TRB_RW(name, member, shift, mask) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) static inline u32 trb_read_##name(struct tegra_xudc_trb *trb) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) return (le32_to_cpu(trb->member) >> (shift)) & (mask); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) static inline void \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) trb_write_##name(struct tegra_xudc_trb *trb, u32 val) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) u32 tmp; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) tmp = le32_to_cpu(trb->member) & ~((mask) << (shift)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) tmp |= (val & (mask)) << (shift); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) trb->member = cpu_to_le32(tmp); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) BUILD_TRB_RW(data_lo, data_lo, 0, 0xffffffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) BUILD_TRB_RW(data_hi, data_hi, 0, 0xffffffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) BUILD_TRB_RW(seq_num, status, 0, 0xffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) BUILD_TRB_RW(transfer_len, status, 0, 0xffffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) BUILD_TRB_RW(td_size, status, 17, 0x1f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) BUILD_TRB_RW(cmpl_code, status, 24, 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) BUILD_TRB_RW(cycle, control, 0, 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) BUILD_TRB_RW(toggle_cycle, control, 1, 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) BUILD_TRB_RW(isp, control, 2, 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) BUILD_TRB_RW(chain, control, 4, 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) BUILD_TRB_RW(ioc, control, 5, 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) BUILD_TRB_RW(type, control, 10, 0x3f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) BUILD_TRB_RW(stream_id, control, 16, 0xffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) BUILD_TRB_RW(endpoint_id, control, 16, 0x1f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) BUILD_TRB_RW(tlbpc, control, 16, 0xf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) BUILD_TRB_RW(data_stage_dir, control, 16, 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) BUILD_TRB_RW(frame_id, control, 20, 0x7ff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) BUILD_TRB_RW(sia, control, 31, 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) static inline u64 trb_read_data_ptr(struct tegra_xudc_trb *trb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) return ((u64)trb_read_data_hi(trb) << 32) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) trb_read_data_lo(trb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) static inline void trb_write_data_ptr(struct tegra_xudc_trb *trb, u64 addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) trb_write_data_lo(trb, lower_32_bits(addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) trb_write_data_hi(trb, upper_32_bits(addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) struct tegra_xudc_request {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) struct usb_request usb_req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) size_t buf_queued;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) unsigned int trbs_queued;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) unsigned int trbs_needed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) bool need_zlp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) struct tegra_xudc_trb *first_trb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) struct tegra_xudc_trb *last_trb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) struct list_head list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) struct tegra_xudc_ep {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) struct tegra_xudc *xudc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) struct usb_ep usb_ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) unsigned int index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) char name[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) struct tegra_xudc_ep_context *context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #define XUDC_TRANSFER_RING_SIZE 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) struct tegra_xudc_trb *transfer_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) dma_addr_t transfer_ring_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) unsigned int enq_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) unsigned int deq_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) bool pcs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) bool ring_full;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) bool stream_rejected;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) struct list_head queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) const struct usb_endpoint_descriptor *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) const struct usb_ss_ep_comp_descriptor *comp_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) struct tegra_xudc_sel_timing {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) __u8 u1sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) __u8 u1pel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) __le16 u2sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) __le16 u2pel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) enum tegra_xudc_setup_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) WAIT_FOR_SETUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) DATA_STAGE_XFER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) DATA_STAGE_RECV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) STATUS_STAGE_XFER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) STATUS_STAGE_RECV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) struct tegra_xudc_setup_packet {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) struct usb_ctrlrequest ctrl_req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) unsigned int seq_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) struct tegra_xudc_save_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) u32 ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) u32 portpm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) struct tegra_xudc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) const struct tegra_xudc_soc *soc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) struct tegra_xusb_padctl *padctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) struct usb_gadget gadget;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) struct usb_gadget_driver *driver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) #define XUDC_NR_EVENT_RINGS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) #define XUDC_EVENT_RING_SIZE 4096
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) struct tegra_xudc_trb *event_ring[XUDC_NR_EVENT_RINGS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) dma_addr_t event_ring_phys[XUDC_NR_EVENT_RINGS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) unsigned int event_ring_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) unsigned int event_ring_deq_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) bool ccs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) #define XUDC_NR_EPS 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) struct tegra_xudc_ep ep[XUDC_NR_EPS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) struct tegra_xudc_ep_context *ep_context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) dma_addr_t ep_context_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) struct device *genpd_dev_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) struct device *genpd_dev_ss;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) struct device_link *genpd_dl_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) struct device_link *genpd_dl_ss;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) struct dma_pool *transfer_ring_pool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) bool queued_setup_packet;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) struct tegra_xudc_setup_packet setup_packet;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) enum tegra_xudc_setup_state setup_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) u16 setup_seq_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) u16 dev_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) u16 isoch_delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) struct tegra_xudc_sel_timing sel_timing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) u8 test_mode_pattern;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) u16 status_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) struct tegra_xudc_request *ep0_req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) bool pullup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) unsigned int nr_enabled_eps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) unsigned int nr_isoch_eps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) unsigned int device_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) unsigned int resume_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) resource_size_t phys_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) void __iomem *ipfs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) void __iomem *fpci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) struct regulator_bulk_data *supplies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) struct clk_bulk_data *clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) bool device_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) struct work_struct usb_role_sw_work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) struct phy **usb3_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) struct phy *curr_usb3_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) struct phy **utmi_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) struct phy *curr_utmi_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) struct tegra_xudc_save_regs saved_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) bool suspended;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) bool powergated;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) struct usb_phy **usbphy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) struct usb_phy *curr_usbphy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) struct notifier_block vbus_nb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) struct completion disconnect_complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) bool selfpowered;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) #define TOGGLE_VBUS_WAIT_MS 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) struct delayed_work plc_reset_work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) bool wait_csc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) struct delayed_work port_reset_war_work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) bool wait_for_sec_prc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) #define XUDC_TRB_MAX_BUFFER_SIZE 65536
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) #define XUDC_MAX_ISOCH_EPS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) #define XUDC_INTERRUPT_MODERATION_US 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) static struct usb_endpoint_descriptor tegra_xudc_ep0_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) .bLength = USB_DT_ENDPOINT_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) .bDescriptorType = USB_DT_ENDPOINT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) .bEndpointAddress = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) .wMaxPacketSize = cpu_to_le16(64),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) struct tegra_xudc_soc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) const char * const *supply_names;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) unsigned int num_supplies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) const char * const *clock_names;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) unsigned int num_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) unsigned int num_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) bool u1_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) bool u2_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) bool lpm_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) bool invalid_seq_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) bool pls_quirk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) bool port_reset_quirk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) bool port_speed_quirk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) bool has_ipfs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) static inline u32 fpci_readl(struct tegra_xudc *xudc, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) return readl(xudc->fpci + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) static inline void fpci_writel(struct tegra_xudc *xudc, u32 val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) writel(val, xudc->fpci + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) static inline u32 ipfs_readl(struct tegra_xudc *xudc, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) return readl(xudc->ipfs + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) static inline void ipfs_writel(struct tegra_xudc *xudc, u32 val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) writel(val, xudc->ipfs + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) static inline u32 xudc_readl(struct tegra_xudc *xudc, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) return readl(xudc->base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) static inline void xudc_writel(struct tegra_xudc *xudc, u32 val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) writel(val, xudc->base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) static inline int xudc_readl_poll(struct tegra_xudc *xudc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) unsigned int offset, u32 mask, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) u32 regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) return readl_poll_timeout_atomic(xudc->base + offset, regval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) (regval & mask) == val, 1, 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) static inline struct tegra_xudc *to_xudc(struct usb_gadget *gadget)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) return container_of(gadget, struct tegra_xudc, gadget);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) static inline struct tegra_xudc_ep *to_xudc_ep(struct usb_ep *ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) return container_of(ep, struct tegra_xudc_ep, usb_ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) static inline struct tegra_xudc_request *to_xudc_req(struct usb_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) return container_of(req, struct tegra_xudc_request, usb_req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) static inline void dump_trb(struct tegra_xudc *xudc, const char *type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) struct tegra_xudc_trb *trb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) dev_dbg(xudc->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) "%s: %p, lo = %#x, hi = %#x, status = %#x, control = %#x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) type, trb, trb->data_lo, trb->data_hi, trb->status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) trb->control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) static void tegra_xudc_limit_port_speed(struct tegra_xudc *xudc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) /* limit port speed to gen 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) val = xudc_readl(xudc, SSPX_CORE_CNT56);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) val &= ~(SSPX_CORE_CNT56_SCD_BIT0_TRPT_MAX_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) val |= SSPX_CORE_CNT56_SCD_BIT0_TRPT_MAX(0x260);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) xudc_writel(xudc, val, SSPX_CORE_CNT56);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) val = xudc_readl(xudc, SSPX_CORE_CNT57);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) val &= ~(SSPX_CORE_CNT57_SCD_BIT1_TRPT_MAX_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) val |= SSPX_CORE_CNT57_SCD_BIT1_TRPT_MAX(0x6D6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) xudc_writel(xudc, val, SSPX_CORE_CNT57);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) val = xudc_readl(xudc, SSPX_CORE_CNT65);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) val &= ~(SSPX_CORE_CNT65_TX_SCD_END_TRPT_MID_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) val |= SSPX_CORE_CNT65_TX_SCD_END_TRPT_MID(0x4B0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) xudc_writel(xudc, val, SSPX_CORE_CNT66);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) val = xudc_readl(xudc, SSPX_CORE_CNT66);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) val &= ~(SSPX_CORE_CNT66_TX_SCD_BIT0_TRPT_MID_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) val |= SSPX_CORE_CNT66_TX_SCD_BIT0_TRPT_MID(0x4B0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) xudc_writel(xudc, val, SSPX_CORE_CNT66);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) val = xudc_readl(xudc, SSPX_CORE_CNT67);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) val &= ~(SSPX_CORE_CNT67_TX_SCD_BIT1_TRPT_MID_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) val |= SSPX_CORE_CNT67_TX_SCD_BIT1_TRPT_MID(0x4B0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) xudc_writel(xudc, val, SSPX_CORE_CNT67);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) val = xudc_readl(xudc, SSPX_CORE_CNT72);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) val &= ~(SSPX_CORE_CNT72_SCD_LFPS_TIMEOUT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) val |= SSPX_CORE_CNT72_SCD_LFPS_TIMEOUT(0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) xudc_writel(xudc, val, SSPX_CORE_CNT72);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) static void tegra_xudc_restore_port_speed(struct tegra_xudc *xudc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) /* restore port speed to gen2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) val = xudc_readl(xudc, SSPX_CORE_CNT56);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) val &= ~(SSPX_CORE_CNT56_SCD_BIT0_TRPT_MAX_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) val |= SSPX_CORE_CNT56_SCD_BIT0_TRPT_MAX(0x438);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) xudc_writel(xudc, val, SSPX_CORE_CNT56);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) val = xudc_readl(xudc, SSPX_CORE_CNT57);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) val &= ~(SSPX_CORE_CNT57_SCD_BIT1_TRPT_MAX_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) val |= SSPX_CORE_CNT57_SCD_BIT1_TRPT_MAX(0x528);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) xudc_writel(xudc, val, SSPX_CORE_CNT57);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) val = xudc_readl(xudc, SSPX_CORE_CNT65);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) val &= ~(SSPX_CORE_CNT65_TX_SCD_END_TRPT_MID_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) val |= SSPX_CORE_CNT65_TX_SCD_END_TRPT_MID(0xE10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) xudc_writel(xudc, val, SSPX_CORE_CNT66);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) val = xudc_readl(xudc, SSPX_CORE_CNT66);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) val &= ~(SSPX_CORE_CNT66_TX_SCD_BIT0_TRPT_MID_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) val |= SSPX_CORE_CNT66_TX_SCD_BIT0_TRPT_MID(0x348);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) xudc_writel(xudc, val, SSPX_CORE_CNT66);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) val = xudc_readl(xudc, SSPX_CORE_CNT67);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) val &= ~(SSPX_CORE_CNT67_TX_SCD_BIT1_TRPT_MID_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) val |= SSPX_CORE_CNT67_TX_SCD_BIT1_TRPT_MID(0x5a0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) xudc_writel(xudc, val, SSPX_CORE_CNT67);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) val = xudc_readl(xudc, SSPX_CORE_CNT72);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) val &= ~(SSPX_CORE_CNT72_SCD_LFPS_TIMEOUT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) val |= SSPX_CORE_CNT72_SCD_LFPS_TIMEOUT(0x1c21);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) xudc_writel(xudc, val, SSPX_CORE_CNT72);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) static void tegra_xudc_device_mode_on(struct tegra_xudc *xudc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) pm_runtime_get_sync(xudc->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) err = phy_power_on(xudc->curr_utmi_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) dev_err(xudc->dev, "UTMI power on failed: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) err = phy_power_on(xudc->curr_usb3_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) dev_err(xudc->dev, "USB3 PHY power on failed: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) dev_dbg(xudc->dev, "device mode on\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) phy_set_mode_ext(xudc->curr_utmi_phy, PHY_MODE_USB_OTG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) USB_ROLE_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) static void tegra_xudc_device_mode_off(struct tegra_xudc *xudc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) bool connected = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) u32 pls, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) dev_dbg(xudc->dev, "device mode off\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) connected = !!(xudc_readl(xudc, PORTSC) & PORTSC_CCS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) reinit_completion(&xudc->disconnect_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) if (xudc->soc->port_speed_quirk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) tegra_xudc_restore_port_speed(xudc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) phy_set_mode_ext(xudc->curr_utmi_phy, PHY_MODE_USB_OTG, USB_ROLE_NONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) pls = (xudc_readl(xudc, PORTSC) & PORTSC_PLS_MASK) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) PORTSC_PLS_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) /* Direct link to U0 if disconnected in RESUME or U2. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) if (xudc->soc->pls_quirk && xudc->gadget.speed == USB_SPEED_SUPER &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) (pls == PORTSC_PLS_RESUME || pls == PORTSC_PLS_U2)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) val = xudc_readl(xudc, PORTPM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) val |= PORTPM_FRWE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) xudc_writel(xudc, val, PORTPM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) val = xudc_readl(xudc, PORTSC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) val &= ~(PORTSC_CHANGE_MASK | PORTSC_PLS_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) val |= PORTSC_LWS | PORTSC_PLS(PORTSC_PLS_U0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) xudc_writel(xudc, val, PORTSC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) /* Wait for disconnect event. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) if (connected)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) wait_for_completion(&xudc->disconnect_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) /* Make sure interrupt handler has completed before powergating. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) synchronize_irq(xudc->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) err = phy_power_off(xudc->curr_utmi_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) dev_err(xudc->dev, "UTMI PHY power off failed: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) err = phy_power_off(xudc->curr_usb3_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) dev_err(xudc->dev, "USB3 PHY power off failed: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) pm_runtime_put(xudc->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) static void tegra_xudc_usb_role_sw_work(struct work_struct *work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) struct tegra_xudc *xudc = container_of(work, struct tegra_xudc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) usb_role_sw_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) if (xudc->device_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) tegra_xudc_device_mode_on(xudc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) tegra_xudc_device_mode_off(xudc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) static int tegra_xudc_get_phy_index(struct tegra_xudc *xudc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) struct usb_phy *usbphy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) for (i = 0; i < xudc->soc->num_phys; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) if (xudc->usbphy[i] && usbphy == xudc->usbphy[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) return i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) dev_info(xudc->dev, "phy index could not be found for shared USB PHY");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) static int tegra_xudc_vbus_notify(struct notifier_block *nb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) unsigned long action, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) struct tegra_xudc *xudc = container_of(nb, struct tegra_xudc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) vbus_nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) struct usb_phy *usbphy = (struct usb_phy *)data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) int phy_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) dev_dbg(xudc->dev, "%s(): event is %d\n", __func__, usbphy->last_event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) if ((xudc->device_mode && usbphy->last_event == USB_EVENT_VBUS) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) (!xudc->device_mode && usbphy->last_event != USB_EVENT_VBUS)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) dev_dbg(xudc->dev, "Same role(%d) received. Ignore",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) xudc->device_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) return NOTIFY_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) xudc->device_mode = (usbphy->last_event == USB_EVENT_VBUS) ? true :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) phy_index = tegra_xudc_get_phy_index(xudc, usbphy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) dev_dbg(xudc->dev, "%s(): current phy index is %d\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) phy_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) if (!xudc->suspended && phy_index != -1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) xudc->curr_utmi_phy = xudc->utmi_phy[phy_index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) xudc->curr_usb3_phy = xudc->usb3_phy[phy_index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) xudc->curr_usbphy = usbphy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) schedule_work(&xudc->usb_role_sw_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) return NOTIFY_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) static void tegra_xudc_plc_reset_work(struct work_struct *work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) struct delayed_work *dwork = to_delayed_work(work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) struct tegra_xudc *xudc = container_of(dwork, struct tegra_xudc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) plc_reset_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) spin_lock_irqsave(&xudc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) if (xudc->wait_csc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) u32 pls = (xudc_readl(xudc, PORTSC) & PORTSC_PLS_MASK) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) PORTSC_PLS_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) if (pls == PORTSC_PLS_INACTIVE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) dev_info(xudc->dev, "PLS = Inactive. Toggle VBUS\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) phy_set_mode_ext(xudc->curr_utmi_phy, PHY_MODE_USB_OTG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) USB_ROLE_NONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) phy_set_mode_ext(xudc->curr_utmi_phy, PHY_MODE_USB_OTG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) USB_ROLE_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) xudc->wait_csc = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) spin_unlock_irqrestore(&xudc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) static void tegra_xudc_port_reset_war_work(struct work_struct *work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) struct delayed_work *dwork = to_delayed_work(work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) struct tegra_xudc *xudc =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) container_of(dwork, struct tegra_xudc, port_reset_war_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) u32 pls;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) spin_lock_irqsave(&xudc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) if (xudc->device_mode && xudc->wait_for_sec_prc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) pls = (xudc_readl(xudc, PORTSC) & PORTSC_PLS_MASK) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) PORTSC_PLS_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) dev_dbg(xudc->dev, "pls = %x\n", pls);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) if (pls == PORTSC_PLS_DISABLED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) dev_dbg(xudc->dev, "toggle vbus\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) /* PRC doesn't complete in 100ms, toggle the vbus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) ret = tegra_phy_xusb_utmi_port_reset(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) xudc->curr_utmi_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) if (ret == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) xudc->wait_for_sec_prc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) spin_unlock_irqrestore(&xudc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) static dma_addr_t trb_virt_to_phys(struct tegra_xudc_ep *ep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) struct tegra_xudc_trb *trb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) unsigned int index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) index = trb - ep->transfer_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) if (WARN_ON(index >= XUDC_TRANSFER_RING_SIZE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) return (ep->transfer_ring_phys + index * sizeof(*trb));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) static struct tegra_xudc_trb *trb_phys_to_virt(struct tegra_xudc_ep *ep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) dma_addr_t addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) struct tegra_xudc_trb *trb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) unsigned int index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) index = (addr - ep->transfer_ring_phys) / sizeof(*trb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) if (WARN_ON(index >= XUDC_TRANSFER_RING_SIZE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) trb = &ep->transfer_ring[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) return trb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) static void ep_reload(struct tegra_xudc *xudc, unsigned int ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) xudc_writel(xudc, BIT(ep), EP_RELOAD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) xudc_readl_poll(xudc, EP_RELOAD, BIT(ep), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) static void ep_pause(struct tegra_xudc *xudc, unsigned int ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) val = xudc_readl(xudc, EP_PAUSE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) if (val & BIT(ep))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) val |= BIT(ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) xudc_writel(xudc, val, EP_PAUSE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) xudc_readl_poll(xudc, EP_STCHG, BIT(ep), BIT(ep));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) xudc_writel(xudc, BIT(ep), EP_STCHG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) static void ep_unpause(struct tegra_xudc *xudc, unsigned int ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) val = xudc_readl(xudc, EP_PAUSE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) if (!(val & BIT(ep)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) val &= ~BIT(ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) xudc_writel(xudc, val, EP_PAUSE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) xudc_readl_poll(xudc, EP_STCHG, BIT(ep), BIT(ep));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) xudc_writel(xudc, BIT(ep), EP_STCHG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) static void ep_unpause_all(struct tegra_xudc *xudc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) val = xudc_readl(xudc, EP_PAUSE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) xudc_writel(xudc, 0, EP_PAUSE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) xudc_readl_poll(xudc, EP_STCHG, val, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) xudc_writel(xudc, val, EP_STCHG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) static void ep_halt(struct tegra_xudc *xudc, unsigned int ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) val = xudc_readl(xudc, EP_HALT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) if (val & BIT(ep))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) val |= BIT(ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) xudc_writel(xudc, val, EP_HALT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) xudc_readl_poll(xudc, EP_STCHG, BIT(ep), BIT(ep));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) xudc_writel(xudc, BIT(ep), EP_STCHG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) static void ep_unhalt(struct tegra_xudc *xudc, unsigned int ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) val = xudc_readl(xudc, EP_HALT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) if (!(val & BIT(ep)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) val &= ~BIT(ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) xudc_writel(xudc, val, EP_HALT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) xudc_readl_poll(xudc, EP_STCHG, BIT(ep), BIT(ep));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) xudc_writel(xudc, BIT(ep), EP_STCHG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) static void ep_unhalt_all(struct tegra_xudc *xudc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) val = xudc_readl(xudc, EP_HALT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) if (!val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) xudc_writel(xudc, 0, EP_HALT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) xudc_readl_poll(xudc, EP_STCHG, val, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) xudc_writel(xudc, val, EP_STCHG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) static void ep_wait_for_stopped(struct tegra_xudc *xudc, unsigned int ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) xudc_readl_poll(xudc, EP_STOPPED, BIT(ep), BIT(ep));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) xudc_writel(xudc, BIT(ep), EP_STOPPED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) static void ep_wait_for_inactive(struct tegra_xudc *xudc, unsigned int ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) xudc_readl_poll(xudc, EP_THREAD_ACTIVE, BIT(ep), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) static void tegra_xudc_req_done(struct tegra_xudc_ep *ep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) struct tegra_xudc_request *req, int status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) struct tegra_xudc *xudc = ep->xudc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) dev_dbg(xudc->dev, "completing request %p on EP %u with status %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) req, ep->index, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) if (likely(req->usb_req.status == -EINPROGRESS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) req->usb_req.status = status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) list_del_init(&req->list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) if (usb_endpoint_xfer_control(ep->desc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) usb_gadget_unmap_request(&xudc->gadget, &req->usb_req,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) (xudc->setup_state ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) DATA_STAGE_XFER));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) usb_gadget_unmap_request(&xudc->gadget, &req->usb_req,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) usb_endpoint_dir_in(ep->desc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) spin_unlock(&xudc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) usb_gadget_giveback_request(&ep->usb_ep, &req->usb_req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) spin_lock(&xudc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) static void tegra_xudc_ep_nuke(struct tegra_xudc_ep *ep, int status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) struct tegra_xudc_request *req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) while (!list_empty(&ep->queue)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) req = list_first_entry(&ep->queue, struct tegra_xudc_request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) tegra_xudc_req_done(ep, req, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) static unsigned int ep_available_trbs(struct tegra_xudc_ep *ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) if (ep->ring_full)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) if (ep->deq_ptr > ep->enq_ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) return ep->deq_ptr - ep->enq_ptr - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) return XUDC_TRANSFER_RING_SIZE - (ep->enq_ptr - ep->deq_ptr) - 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) static void tegra_xudc_queue_one_trb(struct tegra_xudc_ep *ep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) struct tegra_xudc_request *req,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) struct tegra_xudc_trb *trb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) bool ioc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) struct tegra_xudc *xudc = ep->xudc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) dma_addr_t buf_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) size_t len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) len = min_t(size_t, XUDC_TRB_MAX_BUFFER_SIZE, req->usb_req.length -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) req->buf_queued);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) if (len > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) buf_addr = req->usb_req.dma + req->buf_queued;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) buf_addr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) trb_write_data_ptr(trb, buf_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) trb_write_transfer_len(trb, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) trb_write_td_size(trb, req->trbs_needed - req->trbs_queued - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) if (req->trbs_queued == req->trbs_needed - 1 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) (req->need_zlp && req->trbs_queued == req->trbs_needed - 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) trb_write_chain(trb, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) trb_write_chain(trb, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) trb_write_ioc(trb, ioc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) if (usb_endpoint_dir_out(ep->desc) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) (usb_endpoint_xfer_control(ep->desc) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) (xudc->setup_state == DATA_STAGE_RECV)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) trb_write_isp(trb, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) trb_write_isp(trb, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) if (usb_endpoint_xfer_control(ep->desc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) if (xudc->setup_state == DATA_STAGE_XFER ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) xudc->setup_state == DATA_STAGE_RECV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) trb_write_type(trb, TRB_TYPE_DATA_STAGE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) trb_write_type(trb, TRB_TYPE_STATUS_STAGE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) if (xudc->setup_state == DATA_STAGE_XFER ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) xudc->setup_state == STATUS_STAGE_XFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) trb_write_data_stage_dir(trb, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) trb_write_data_stage_dir(trb, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) } else if (usb_endpoint_xfer_isoc(ep->desc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) trb_write_type(trb, TRB_TYPE_ISOCH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) trb_write_sia(trb, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) trb_write_frame_id(trb, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) trb_write_tlbpc(trb, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) } else if (usb_ss_max_streams(ep->comp_desc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) trb_write_type(trb, TRB_TYPE_STREAM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) trb_write_stream_id(trb, req->usb_req.stream_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) trb_write_type(trb, TRB_TYPE_NORMAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) trb_write_stream_id(trb, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) trb_write_cycle(trb, ep->pcs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) req->trbs_queued++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) req->buf_queued += len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) dump_trb(xudc, "TRANSFER", trb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) static unsigned int tegra_xudc_queue_trbs(struct tegra_xudc_ep *ep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) struct tegra_xudc_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) unsigned int i, count, available;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) bool wait_td = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) available = ep_available_trbs(ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) count = req->trbs_needed - req->trbs_queued;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) if (available < count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) count = available;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) ep->ring_full = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) * To generate zero-length packet on USB bus, SW needs schedule a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) * standalone zero-length TD. According to HW's behavior, SW needs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) * to schedule TDs in different ways for different endpoint types.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) * For control endpoint:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) * - Data stage TD (IOC = 1, CH = 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) * - Ring doorbell and wait transfer event
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) * - Data stage TD for ZLP (IOC = 1, CH = 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) * - Ring doorbell
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) * For bulk and interrupt endpoints:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) * - Normal transfer TD (IOC = 0, CH = 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) * - Normal transfer TD for ZLP (IOC = 1, CH = 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) * - Ring doorbell
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) if (req->need_zlp && usb_endpoint_xfer_control(ep->desc) && count > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) wait_td = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) if (!req->first_trb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) req->first_trb = &ep->transfer_ring[ep->enq_ptr];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) for (i = 0; i < count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) struct tegra_xudc_trb *trb = &ep->transfer_ring[ep->enq_ptr];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) bool ioc = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) if ((i == count - 1) || (wait_td && i == count - 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) ioc = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) tegra_xudc_queue_one_trb(ep, req, trb, ioc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) req->last_trb = trb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) ep->enq_ptr++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) if (ep->enq_ptr == XUDC_TRANSFER_RING_SIZE - 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) trb = &ep->transfer_ring[ep->enq_ptr];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) trb_write_cycle(trb, ep->pcs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) ep->pcs = !ep->pcs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) ep->enq_ptr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) if (ioc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) static void tegra_xudc_ep_ring_doorbell(struct tegra_xudc_ep *ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) struct tegra_xudc *xudc = ep->xudc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) if (list_empty(&ep->queue))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) val = DB_TARGET(ep->index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) if (usb_endpoint_xfer_control(ep->desc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) val |= DB_STREAMID(xudc->setup_seq_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) } else if (usb_ss_max_streams(ep->comp_desc) > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) struct tegra_xudc_request *req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) /* Don't ring doorbell if the stream has been rejected. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) if (ep->stream_rejected)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) req = list_first_entry(&ep->queue, struct tegra_xudc_request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) val |= DB_STREAMID(req->usb_req.stream_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) dev_dbg(xudc->dev, "ring doorbell: %#x\n", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) xudc_writel(xudc, val, DB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) static void tegra_xudc_ep_kick_queue(struct tegra_xudc_ep *ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) struct tegra_xudc_request *req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) bool trbs_queued = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) list_for_each_entry(req, &ep->queue, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) if (ep->ring_full)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) if (tegra_xudc_queue_trbs(ep, req) > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) trbs_queued = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) if (trbs_queued)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) tegra_xudc_ep_ring_doorbell(ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) __tegra_xudc_ep_queue(struct tegra_xudc_ep *ep, struct tegra_xudc_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) struct tegra_xudc *xudc = ep->xudc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) if (usb_endpoint_xfer_control(ep->desc) && !list_empty(&ep->queue)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) dev_err(xudc->dev, "control EP has pending transfers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) if (usb_endpoint_xfer_control(ep->desc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) err = usb_gadget_map_request(&xudc->gadget, &req->usb_req,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) (xudc->setup_state ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) DATA_STAGE_XFER));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) err = usb_gadget_map_request(&xudc->gadget, &req->usb_req,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) usb_endpoint_dir_in(ep->desc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) dev_err(xudc->dev, "failed to map request: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) req->first_trb = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) req->last_trb = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) req->buf_queued = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) req->trbs_queued = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) req->need_zlp = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) req->trbs_needed = DIV_ROUND_UP(req->usb_req.length,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) XUDC_TRB_MAX_BUFFER_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) if (req->usb_req.length == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) req->trbs_needed++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) if (!usb_endpoint_xfer_isoc(ep->desc) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) req->usb_req.zero && req->usb_req.length &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) ((req->usb_req.length % ep->usb_ep.maxpacket) == 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) req->trbs_needed++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) req->need_zlp = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) req->usb_req.status = -EINPROGRESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) req->usb_req.actual = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) list_add_tail(&req->list, &ep->queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) tegra_xudc_ep_kick_queue(ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) tegra_xudc_ep_queue(struct usb_ep *usb_ep, struct usb_request *usb_req,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) gfp_t gfp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) struct tegra_xudc_request *req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) struct tegra_xudc_ep *ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) struct tegra_xudc *xudc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) if (!usb_ep || !usb_req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) ep = to_xudc_ep(usb_ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) req = to_xudc_req(usb_req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) xudc = ep->xudc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) spin_lock_irqsave(&xudc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) if (xudc->powergated || !ep->desc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) ret = -ESHUTDOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) ret = __tegra_xudc_ep_queue(ep, req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) spin_unlock_irqrestore(&xudc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) static void squeeze_transfer_ring(struct tegra_xudc_ep *ep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) struct tegra_xudc_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) struct tegra_xudc_trb *trb = req->first_trb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) bool pcs_enq = trb_read_cycle(trb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) bool pcs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) * Clear out all the TRBs part of or after the cancelled request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) * and must correct trb cycle bit to the last un-enqueued state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) while (trb != &ep->transfer_ring[ep->enq_ptr]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) pcs = trb_read_cycle(trb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) memset(trb, 0, sizeof(*trb));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) trb_write_cycle(trb, !pcs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) trb++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) if (trb_read_type(trb) == TRB_TYPE_LINK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) trb = ep->transfer_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) /* Requests will be re-queued at the start of the cancelled request. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) ep->enq_ptr = req->first_trb - ep->transfer_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) * Retrieve the correct cycle bit state from the first trb of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) * the cancelled request.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) ep->pcs = pcs_enq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) ep->ring_full = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) list_for_each_entry_continue(req, &ep->queue, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) req->usb_req.status = -EINPROGRESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) req->usb_req.actual = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) req->first_trb = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) req->last_trb = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) req->buf_queued = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) req->trbs_queued = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) * Determine if the given TRB is in the range [first trb, last trb] for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) * given request.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) static bool trb_in_request(struct tegra_xudc_ep *ep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) struct tegra_xudc_request *req,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) struct tegra_xudc_trb *trb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) dev_dbg(ep->xudc->dev, "%s: request %p -> %p; trb %p\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) req->first_trb, req->last_trb, trb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) if (trb >= req->first_trb && (trb <= req->last_trb ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) req->last_trb < req->first_trb))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) if (trb < req->first_trb && trb <= req->last_trb &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) req->last_trb < req->first_trb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) * Determine if the given TRB is in the range [EP enqueue pointer, first TRB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) * for the given endpoint and request.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) static bool trb_before_request(struct tegra_xudc_ep *ep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) struct tegra_xudc_request *req,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) struct tegra_xudc_trb *trb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) struct tegra_xudc_trb *enq_trb = &ep->transfer_ring[ep->enq_ptr];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) dev_dbg(ep->xudc->dev, "%s: request %p -> %p; enq ptr: %p; trb %p\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) __func__, req->first_trb, req->last_trb, enq_trb, trb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) if (trb < req->first_trb && (enq_trb <= trb ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) req->first_trb < enq_trb))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) if (trb > req->first_trb && req->first_trb < enq_trb && enq_trb <= trb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) __tegra_xudc_ep_dequeue(struct tegra_xudc_ep *ep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) struct tegra_xudc_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) struct tegra_xudc *xudc = ep->xudc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) struct tegra_xudc_request *r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) struct tegra_xudc_trb *deq_trb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) bool busy, kick_queue = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) /* Make sure the request is actually queued to this endpoint. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) list_for_each_entry(r, &ep->queue, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) if (r == req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) if (r != req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) /* Request hasn't been queued in the transfer ring yet. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) if (!req->trbs_queued) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) tegra_xudc_req_done(ep, req, -ECONNRESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) /* Halt DMA for this endpiont. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) if (ep_ctx_read_state(ep->context) == EP_STATE_RUNNING) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) ep_pause(xudc, ep->index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) ep_wait_for_inactive(xudc, ep->index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) deq_trb = trb_phys_to_virt(ep, ep_ctx_read_deq_ptr(ep->context));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) /* Is the hardware processing the TRB at the dequeue pointer? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) busy = (trb_read_cycle(deq_trb) == ep_ctx_read_dcs(ep->context));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) if (trb_in_request(ep, req, deq_trb) && busy) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) * Request has been partially completed or it hasn't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) * started processing yet.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) dma_addr_t deq_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) squeeze_transfer_ring(ep, req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) req->usb_req.actual = ep_ctx_read_edtla(ep->context);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) tegra_xudc_req_done(ep, req, -ECONNRESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) kick_queue = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) /* EDTLA is > 0: request has been partially completed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) if (req->usb_req.actual > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) * Abort the pending transfer and update the dequeue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) * pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) ep_ctx_write_edtla(ep->context, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) ep_ctx_write_partial_td(ep->context, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) ep_ctx_write_data_offset(ep->context, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) deq_ptr = trb_virt_to_phys(ep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) &ep->transfer_ring[ep->enq_ptr]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) if (dma_mapping_error(xudc->dev, deq_ptr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) ep_ctx_write_deq_ptr(ep->context, deq_ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) ep_ctx_write_dcs(ep->context, ep->pcs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) ep_reload(xudc, ep->index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) } else if (trb_before_request(ep, req, deq_trb) && busy) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) /* Request hasn't started processing yet. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) squeeze_transfer_ring(ep, req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) tegra_xudc_req_done(ep, req, -ECONNRESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) kick_queue = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) * Request has completed, but we haven't processed the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) * completion event yet.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) tegra_xudc_req_done(ep, req, -ECONNRESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) /* Resume the endpoint. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) ep_unpause(xudc, ep->index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) if (kick_queue)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) tegra_xudc_ep_kick_queue(ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) tegra_xudc_ep_dequeue(struct usb_ep *usb_ep, struct usb_request *usb_req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) struct tegra_xudc_request *req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) struct tegra_xudc_ep *ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) struct tegra_xudc *xudc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) if (!usb_ep || !usb_req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) ep = to_xudc_ep(usb_ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) req = to_xudc_req(usb_req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) xudc = ep->xudc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) spin_lock_irqsave(&xudc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) if (xudc->powergated || !ep->desc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) ret = -ESHUTDOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) ret = __tegra_xudc_ep_dequeue(ep, req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) spin_unlock_irqrestore(&xudc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) static int __tegra_xudc_ep_set_halt(struct tegra_xudc_ep *ep, bool halt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) struct tegra_xudc *xudc = ep->xudc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) if (!ep->desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) if (usb_endpoint_xfer_isoc(ep->desc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) dev_err(xudc->dev, "can't halt isochronous EP\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) if (!!(xudc_readl(xudc, EP_HALT) & BIT(ep->index)) == halt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) dev_dbg(xudc->dev, "EP %u already %s\n", ep->index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) halt ? "halted" : "not halted");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) if (halt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) ep_halt(xudc, ep->index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) ep_ctx_write_state(ep->context, EP_STATE_DISABLED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) ep_reload(xudc, ep->index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) ep_ctx_write_state(ep->context, EP_STATE_RUNNING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) ep_ctx_write_seq_num(ep->context, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) ep_reload(xudc, ep->index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) ep_unpause(xudc, ep->index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) ep_unhalt(xudc, ep->index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) tegra_xudc_ep_ring_doorbell(ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) static int tegra_xudc_ep_set_halt(struct usb_ep *usb_ep, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) struct tegra_xudc_ep *ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) struct tegra_xudc *xudc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) if (!usb_ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) ep = to_xudc_ep(usb_ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) xudc = ep->xudc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) spin_lock_irqsave(&xudc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) if (xudc->powergated) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) ret = -ESHUTDOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) if (value && usb_endpoint_dir_in(ep->desc) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) !list_empty(&ep->queue)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) dev_err(xudc->dev, "can't halt EP with requests pending\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) ret = -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) ret = __tegra_xudc_ep_set_halt(ep, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) spin_unlock_irqrestore(&xudc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) static void tegra_xudc_ep_context_setup(struct tegra_xudc_ep *ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) const struct usb_endpoint_descriptor *desc = ep->desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) const struct usb_ss_ep_comp_descriptor *comp_desc = ep->comp_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) struct tegra_xudc *xudc = ep->xudc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) u16 maxpacket, maxburst = 0, esit = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) maxpacket = usb_endpoint_maxp(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) if (xudc->gadget.speed == USB_SPEED_SUPER) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) if (!usb_endpoint_xfer_control(desc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) maxburst = comp_desc->bMaxBurst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) if (usb_endpoint_xfer_int(desc) || usb_endpoint_xfer_isoc(desc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) esit = le16_to_cpu(comp_desc->wBytesPerInterval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) } else if ((xudc->gadget.speed < USB_SPEED_SUPER) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) (usb_endpoint_xfer_int(desc) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) usb_endpoint_xfer_isoc(desc))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) if (xudc->gadget.speed == USB_SPEED_HIGH) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) maxburst = usb_endpoint_maxp_mult(desc) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) if (maxburst == 0x3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) dev_warn(xudc->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) "invalid endpoint maxburst\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) maxburst = 0x2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) esit = maxpacket * (maxburst + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) memset(ep->context, 0, sizeof(*ep->context));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) ep_ctx_write_state(ep->context, EP_STATE_RUNNING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) ep_ctx_write_interval(ep->context, desc->bInterval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) if (xudc->gadget.speed == USB_SPEED_SUPER) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) if (usb_endpoint_xfer_isoc(desc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) ep_ctx_write_mult(ep->context,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) comp_desc->bmAttributes & 0x3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) if (usb_endpoint_xfer_bulk(desc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) ep_ctx_write_max_pstreams(ep->context,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) comp_desc->bmAttributes &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) 0x1f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) ep_ctx_write_lsa(ep->context, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) if (!usb_endpoint_xfer_control(desc) && usb_endpoint_dir_out(desc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) val = usb_endpoint_type(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) val = usb_endpoint_type(desc) + EP_TYPE_CONTROL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) ep_ctx_write_type(ep->context, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) ep_ctx_write_cerr(ep->context, 0x3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) ep_ctx_write_max_packet_size(ep->context, maxpacket);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) ep_ctx_write_max_burst_size(ep->context, maxburst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) ep_ctx_write_deq_ptr(ep->context, ep->transfer_ring_phys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) ep_ctx_write_dcs(ep->context, ep->pcs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) /* Select a reasonable average TRB length based on endpoint type. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) switch (usb_endpoint_type(desc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) case USB_ENDPOINT_XFER_CONTROL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) val = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) case USB_ENDPOINT_XFER_INT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) val = 1024;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) case USB_ENDPOINT_XFER_BULK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) case USB_ENDPOINT_XFER_ISOC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) val = 3072;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) ep_ctx_write_avg_trb_len(ep->context, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) ep_ctx_write_max_esit_payload(ep->context, esit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) ep_ctx_write_cerrcnt(ep->context, 0x3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) static void setup_link_trb(struct tegra_xudc_ep *ep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) struct tegra_xudc_trb *trb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) trb_write_data_ptr(trb, ep->transfer_ring_phys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) trb_write_type(trb, TRB_TYPE_LINK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) trb_write_toggle_cycle(trb, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) static int __tegra_xudc_ep_disable(struct tegra_xudc_ep *ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) struct tegra_xudc *xudc = ep->xudc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) if (ep_ctx_read_state(ep->context) == EP_STATE_DISABLED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) dev_err(xudc->dev, "endpoint %u already disabled\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) ep->index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) ep_ctx_write_state(ep->context, EP_STATE_DISABLED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) ep_reload(xudc, ep->index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) tegra_xudc_ep_nuke(ep, -ESHUTDOWN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) xudc->nr_enabled_eps--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) if (usb_endpoint_xfer_isoc(ep->desc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) xudc->nr_isoch_eps--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) ep->desc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) ep->comp_desc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) memset(ep->context, 0, sizeof(*ep->context));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) ep_unpause(xudc, ep->index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) ep_unhalt(xudc, ep->index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) if (xudc_readl(xudc, EP_STOPPED) & BIT(ep->index))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) xudc_writel(xudc, BIT(ep->index), EP_STOPPED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) * If this is the last endpoint disabled in a de-configure request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) * switch back to address state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) if ((xudc->device_state == USB_STATE_CONFIGURED) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) (xudc->nr_enabled_eps == 1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) xudc->device_state = USB_STATE_ADDRESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) usb_gadget_set_state(&xudc->gadget, xudc->device_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) val = xudc_readl(xudc, CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) val &= ~CTRL_RUN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) xudc_writel(xudc, val, CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) dev_info(xudc->dev, "ep %u disabled\n", ep->index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) static int tegra_xudc_ep_disable(struct usb_ep *usb_ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) struct tegra_xudc_ep *ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) struct tegra_xudc *xudc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) if (!usb_ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) ep = to_xudc_ep(usb_ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) xudc = ep->xudc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) spin_lock_irqsave(&xudc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) if (xudc->powergated) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) ret = -ESHUTDOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) ret = __tegra_xudc_ep_disable(ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) spin_unlock_irqrestore(&xudc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) static int __tegra_xudc_ep_enable(struct tegra_xudc_ep *ep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) const struct usb_endpoint_descriptor *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) struct tegra_xudc *xudc = ep->xudc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) if (xudc->gadget.speed == USB_SPEED_SUPER &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) !usb_endpoint_xfer_control(desc) && !ep->usb_ep.comp_desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) /* Disable the EP if it is not disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) if (ep_ctx_read_state(ep->context) != EP_STATE_DISABLED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) __tegra_xudc_ep_disable(ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) ep->desc = desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) ep->comp_desc = ep->usb_ep.comp_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) if (usb_endpoint_xfer_isoc(desc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) if (xudc->nr_isoch_eps > XUDC_MAX_ISOCH_EPS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) dev_err(xudc->dev, "too many isochronous endpoints\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) xudc->nr_isoch_eps++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) memset(ep->transfer_ring, 0, XUDC_TRANSFER_RING_SIZE *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) sizeof(*ep->transfer_ring));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) setup_link_trb(ep, &ep->transfer_ring[XUDC_TRANSFER_RING_SIZE - 1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) ep->enq_ptr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) ep->deq_ptr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) ep->pcs = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) ep->ring_full = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) xudc->nr_enabled_eps++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) tegra_xudc_ep_context_setup(ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) * No need to reload and un-halt EP0. This will be done automatically
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) * once a valid SETUP packet is received.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) if (usb_endpoint_xfer_control(desc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) * Transition to configured state once the first non-control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) * endpoint is enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) if (xudc->device_state == USB_STATE_ADDRESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) val = xudc_readl(xudc, CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) val |= CTRL_RUN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) xudc_writel(xudc, val, CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) xudc->device_state = USB_STATE_CONFIGURED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) usb_gadget_set_state(&xudc->gadget, xudc->device_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) if (usb_endpoint_xfer_isoc(desc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) * Pause all bulk endpoints when enabling an isoch endpoint
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) * to ensure the isoch endpoint is allocated enough bandwidth.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) for (i = 0; i < ARRAY_SIZE(xudc->ep); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) if (xudc->ep[i].desc &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) usb_endpoint_xfer_bulk(xudc->ep[i].desc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) ep_pause(xudc, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) ep_reload(xudc, ep->index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) ep_unpause(xudc, ep->index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) ep_unhalt(xudc, ep->index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) if (usb_endpoint_xfer_isoc(desc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) for (i = 0; i < ARRAY_SIZE(xudc->ep); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) if (xudc->ep[i].desc &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) usb_endpoint_xfer_bulk(xudc->ep[i].desc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) ep_unpause(xudc, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) dev_info(xudc->dev, "EP %u (type: %s, dir: %s) enabled\n", ep->index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) usb_ep_type_string(usb_endpoint_type(ep->desc)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) usb_endpoint_dir_in(ep->desc) ? "in" : "out");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) static int tegra_xudc_ep_enable(struct usb_ep *usb_ep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) const struct usb_endpoint_descriptor *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) struct tegra_xudc_ep *ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) struct tegra_xudc *xudc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) if (!usb_ep || !desc || (desc->bDescriptorType != USB_DT_ENDPOINT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) ep = to_xudc_ep(usb_ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) xudc = ep->xudc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) spin_lock_irqsave(&xudc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) if (xudc->powergated) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) ret = -ESHUTDOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) ret = __tegra_xudc_ep_enable(ep, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) spin_unlock_irqrestore(&xudc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) static struct usb_request *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) tegra_xudc_ep_alloc_request(struct usb_ep *usb_ep, gfp_t gfp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) struct tegra_xudc_request *req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) req = kzalloc(sizeof(*req), gfp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) if (!req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) INIT_LIST_HEAD(&req->list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) return &req->usb_req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) static void tegra_xudc_ep_free_request(struct usb_ep *usb_ep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) struct usb_request *usb_req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) struct tegra_xudc_request *req = to_xudc_req(usb_req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) kfree(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) static struct usb_ep_ops tegra_xudc_ep_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) .enable = tegra_xudc_ep_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) .disable = tegra_xudc_ep_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) .alloc_request = tegra_xudc_ep_alloc_request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) .free_request = tegra_xudc_ep_free_request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) .queue = tegra_xudc_ep_queue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) .dequeue = tegra_xudc_ep_dequeue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) .set_halt = tegra_xudc_ep_set_halt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) static int tegra_xudc_ep0_enable(struct usb_ep *usb_ep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) const struct usb_endpoint_descriptor *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) static int tegra_xudc_ep0_disable(struct usb_ep *usb_ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) static struct usb_ep_ops tegra_xudc_ep0_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) .enable = tegra_xudc_ep0_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) .disable = tegra_xudc_ep0_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) .alloc_request = tegra_xudc_ep_alloc_request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) .free_request = tegra_xudc_ep_free_request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) .queue = tegra_xudc_ep_queue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) .dequeue = tegra_xudc_ep_dequeue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) .set_halt = tegra_xudc_ep_set_halt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) static int tegra_xudc_gadget_get_frame(struct usb_gadget *gadget)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) struct tegra_xudc *xudc = to_xudc(gadget);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) spin_lock_irqsave(&xudc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) if (xudc->powergated) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) ret = -ESHUTDOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) ret = (xudc_readl(xudc, MFINDEX) & MFINDEX_FRAME_MASK) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) MFINDEX_FRAME_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) spin_unlock_irqrestore(&xudc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) static void tegra_xudc_resume_device_state(struct tegra_xudc *xudc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) ep_unpause_all(xudc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) /* Direct link to U0. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) val = xudc_readl(xudc, PORTSC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) if (((val & PORTSC_PLS_MASK) >> PORTSC_PLS_SHIFT) != PORTSC_PLS_U0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) val &= ~(PORTSC_CHANGE_MASK | PORTSC_PLS_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) val |= PORTSC_LWS | PORTSC_PLS(PORTSC_PLS_U0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) xudc_writel(xudc, val, PORTSC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) if (xudc->device_state == USB_STATE_SUSPENDED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) xudc->device_state = xudc->resume_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) usb_gadget_set_state(&xudc->gadget, xudc->device_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) xudc->resume_state = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) * Doorbells may be dropped if they are sent too soon (< ~200ns)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) * after unpausing the endpoint. Wait for 500ns just to be safe.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) ndelay(500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) for (i = 0; i < ARRAY_SIZE(xudc->ep); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) tegra_xudc_ep_ring_doorbell(&xudc->ep[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) static int tegra_xudc_gadget_wakeup(struct usb_gadget *gadget)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) struct tegra_xudc *xudc = to_xudc(gadget);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) spin_lock_irqsave(&xudc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) if (xudc->powergated) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) ret = -ESHUTDOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) val = xudc_readl(xudc, PORTPM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) dev_dbg(xudc->dev, "%s: PORTPM=%#x, speed=%x\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) val, gadget->speed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) if (((xudc->gadget.speed <= USB_SPEED_HIGH) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) (val & PORTPM_RWE)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) ((xudc->gadget.speed == USB_SPEED_SUPER) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) (val & PORTPM_FRWE))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) tegra_xudc_resume_device_state(xudc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) /* Send Device Notification packet. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) if (xudc->gadget.speed == USB_SPEED_SUPER) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) val = DEVNOTIF_LO_TYPE(DEVNOTIF_LO_TYPE_FUNCTION_WAKE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) | DEVNOTIF_LO_TRIG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) xudc_writel(xudc, 0, DEVNOTIF_HI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) xudc_writel(xudc, val, DEVNOTIF_LO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) dev_dbg(xudc->dev, "%s: ret value is %d", __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) spin_unlock_irqrestore(&xudc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) static int tegra_xudc_gadget_pullup(struct usb_gadget *gadget, int is_on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) struct tegra_xudc *xudc = to_xudc(gadget);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) pm_runtime_get_sync(xudc->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) spin_lock_irqsave(&xudc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) if (is_on != xudc->pullup) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) val = xudc_readl(xudc, CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) if (is_on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) val |= CTRL_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) val &= ~CTRL_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) xudc_writel(xudc, val, CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) xudc->pullup = is_on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) dev_dbg(xudc->dev, "%s: pullup:%d", __func__, is_on);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) spin_unlock_irqrestore(&xudc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) pm_runtime_put(xudc->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) static int tegra_xudc_gadget_start(struct usb_gadget *gadget,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) struct usb_gadget_driver *driver)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) struct tegra_xudc *xudc = to_xudc(gadget);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) if (!driver)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) pm_runtime_get_sync(xudc->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) spin_lock_irqsave(&xudc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) if (xudc->driver) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) ret = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) xudc->setup_state = WAIT_FOR_SETUP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) xudc->device_state = USB_STATE_DEFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) usb_gadget_set_state(&xudc->gadget, xudc->device_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) ret = __tegra_xudc_ep_enable(&xudc->ep[0], &tegra_xudc_ep0_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) val = xudc_readl(xudc, CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) val |= CTRL_IE | CTRL_LSE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) xudc_writel(xudc, val, CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) val = xudc_readl(xudc, PORTHALT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) val |= PORTHALT_STCHG_INTR_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) xudc_writel(xudc, val, PORTHALT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) if (xudc->pullup) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) val = xudc_readl(xudc, CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) val |= CTRL_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) xudc_writel(xudc, val, CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) for (i = 0; i < xudc->soc->num_phys; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) if (xudc->usbphy[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) otg_set_peripheral(xudc->usbphy[i]->otg, gadget);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) xudc->driver = driver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) dev_dbg(xudc->dev, "%s: ret value is %d", __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) spin_unlock_irqrestore(&xudc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) pm_runtime_put(xudc->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) static int tegra_xudc_gadget_stop(struct usb_gadget *gadget)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) struct tegra_xudc *xudc = to_xudc(gadget);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) pm_runtime_get_sync(xudc->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) spin_lock_irqsave(&xudc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) for (i = 0; i < xudc->soc->num_phys; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) if (xudc->usbphy[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) otg_set_peripheral(xudc->usbphy[i]->otg, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) val = xudc_readl(xudc, CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) val &= ~(CTRL_IE | CTRL_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) xudc_writel(xudc, val, CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) __tegra_xudc_ep_disable(&xudc->ep[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) xudc->driver = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) dev_dbg(xudc->dev, "Gadget stopped");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) spin_unlock_irqrestore(&xudc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) pm_runtime_put(xudc->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) static int tegra_xudc_gadget_vbus_draw(struct usb_gadget *gadget,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) unsigned int m_a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) struct tegra_xudc *xudc = to_xudc(gadget);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) dev_dbg(xudc->dev, "%s: %u mA\n", __func__, m_a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) if (xudc->curr_usbphy->chg_type == SDP_TYPE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) ret = usb_phy_set_power(xudc->curr_usbphy, m_a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) static int tegra_xudc_set_selfpowered(struct usb_gadget *gadget, int is_on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) struct tegra_xudc *xudc = to_xudc(gadget);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) dev_dbg(xudc->dev, "%s: %d\n", __func__, is_on);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) xudc->selfpowered = !!is_on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) static struct usb_gadget_ops tegra_xudc_gadget_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) .get_frame = tegra_xudc_gadget_get_frame,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) .wakeup = tegra_xudc_gadget_wakeup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) .pullup = tegra_xudc_gadget_pullup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) .udc_start = tegra_xudc_gadget_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) .udc_stop = tegra_xudc_gadget_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) .vbus_draw = tegra_xudc_gadget_vbus_draw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) .set_selfpowered = tegra_xudc_set_selfpowered,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) static void no_op_complete(struct usb_ep *ep, struct usb_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) tegra_xudc_ep0_queue_status(struct tegra_xudc *xudc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) void (*cmpl)(struct usb_ep *, struct usb_request *))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) xudc->ep0_req->usb_req.buf = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) xudc->ep0_req->usb_req.dma = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) xudc->ep0_req->usb_req.length = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) xudc->ep0_req->usb_req.complete = cmpl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) xudc->ep0_req->usb_req.context = xudc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) return __tegra_xudc_ep_queue(&xudc->ep[0], xudc->ep0_req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) tegra_xudc_ep0_queue_data(struct tegra_xudc *xudc, void *buf, size_t len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) void (*cmpl)(struct usb_ep *, struct usb_request *))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) xudc->ep0_req->usb_req.buf = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) xudc->ep0_req->usb_req.length = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) xudc->ep0_req->usb_req.complete = cmpl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) xudc->ep0_req->usb_req.context = xudc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) return __tegra_xudc_ep_queue(&xudc->ep[0], xudc->ep0_req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) static void tegra_xudc_ep0_req_done(struct tegra_xudc *xudc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) switch (xudc->setup_state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) case DATA_STAGE_XFER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) xudc->setup_state = STATUS_STAGE_RECV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) tegra_xudc_ep0_queue_status(xudc, no_op_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) case DATA_STAGE_RECV:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) xudc->setup_state = STATUS_STAGE_XFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) tegra_xudc_ep0_queue_status(xudc, no_op_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) xudc->setup_state = WAIT_FOR_SETUP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) static int tegra_xudc_ep0_delegate_req(struct tegra_xudc *xudc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) struct usb_ctrlrequest *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) spin_unlock(&xudc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) ret = xudc->driver->setup(&xudc->gadget, ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) spin_lock(&xudc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) static void set_feature_complete(struct usb_ep *ep, struct usb_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) struct tegra_xudc *xudc = req->context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) if (xudc->test_mode_pattern) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) xudc_writel(xudc, xudc->test_mode_pattern, PORT_TM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) xudc->test_mode_pattern = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) static int tegra_xudc_ep0_set_feature(struct tegra_xudc *xudc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) struct usb_ctrlrequest *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) bool set = (ctrl->bRequest == USB_REQ_SET_FEATURE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) u32 feature = le16_to_cpu(ctrl->wValue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) u32 index = le16_to_cpu(ctrl->wIndex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) u32 val, ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) if (le16_to_cpu(ctrl->wLength) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) switch (ctrl->bRequestType & USB_RECIP_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) case USB_RECIP_DEVICE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) switch (feature) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) case USB_DEVICE_REMOTE_WAKEUP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) if ((xudc->gadget.speed == USB_SPEED_SUPER) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) (xudc->device_state == USB_STATE_DEFAULT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) val = xudc_readl(xudc, PORTPM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) if (set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) val |= PORTPM_RWE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) val &= ~PORTPM_RWE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) xudc_writel(xudc, val, PORTPM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) case USB_DEVICE_U1_ENABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) case USB_DEVICE_U2_ENABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) if ((xudc->device_state != USB_STATE_CONFIGURED) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) (xudc->gadget.speed != USB_SPEED_SUPER))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) val = xudc_readl(xudc, PORTPM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) if ((feature == USB_DEVICE_U1_ENABLE) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) xudc->soc->u1_enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) if (set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) val |= PORTPM_U1E;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) val &= ~PORTPM_U1E;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) if ((feature == USB_DEVICE_U2_ENABLE) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) xudc->soc->u2_enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) if (set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) val |= PORTPM_U2E;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) val &= ~PORTPM_U2E;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) xudc_writel(xudc, val, PORTPM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) case USB_DEVICE_TEST_MODE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) if (xudc->gadget.speed != USB_SPEED_HIGH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) if (!set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) xudc->test_mode_pattern = index >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) case USB_RECIP_INTERFACE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) if (xudc->device_state != USB_STATE_CONFIGURED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) switch (feature) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) case USB_INTRF_FUNC_SUSPEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) if (set) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) val = xudc_readl(xudc, PORTPM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) if (index & USB_INTRF_FUNC_SUSPEND_RW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) val |= PORTPM_FRWE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) val &= ~PORTPM_FRWE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) xudc_writel(xudc, val, PORTPM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) return tegra_xudc_ep0_delegate_req(xudc, ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) case USB_RECIP_ENDPOINT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) ep = (index & USB_ENDPOINT_NUMBER_MASK) * 2 +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) ((index & USB_DIR_IN) ? 1 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) if ((xudc->device_state == USB_STATE_DEFAULT) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) ((xudc->device_state == USB_STATE_ADDRESS) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) (index != 0)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) ret = __tegra_xudc_ep_set_halt(&xudc->ep[ep], set);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) return tegra_xudc_ep0_queue_status(xudc, set_feature_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) static int tegra_xudc_ep0_get_status(struct tegra_xudc *xudc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) struct usb_ctrlrequest *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) struct tegra_xudc_ep_context *ep_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) u32 val, ep, index = le16_to_cpu(ctrl->wIndex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) u16 status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) if (!(ctrl->bRequestType & USB_DIR_IN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) if ((le16_to_cpu(ctrl->wValue) != 0) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) (le16_to_cpu(ctrl->wLength) != 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) switch (ctrl->bRequestType & USB_RECIP_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) case USB_RECIP_DEVICE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) val = xudc_readl(xudc, PORTPM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) if (xudc->selfpowered)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) status |= BIT(USB_DEVICE_SELF_POWERED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) if ((xudc->gadget.speed < USB_SPEED_SUPER) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) (val & PORTPM_RWE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) status |= BIT(USB_DEVICE_REMOTE_WAKEUP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) if (xudc->gadget.speed == USB_SPEED_SUPER) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) if (val & PORTPM_U1E)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) status |= BIT(USB_DEV_STAT_U1_ENABLED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) if (val & PORTPM_U2E)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) status |= BIT(USB_DEV_STAT_U2_ENABLED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) case USB_RECIP_INTERFACE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) if (xudc->gadget.speed == USB_SPEED_SUPER) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) status |= USB_INTRF_STAT_FUNC_RW_CAP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) val = xudc_readl(xudc, PORTPM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) if (val & PORTPM_FRWE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) status |= USB_INTRF_STAT_FUNC_RW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) case USB_RECIP_ENDPOINT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) ep = (index & USB_ENDPOINT_NUMBER_MASK) * 2 +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) ((index & USB_DIR_IN) ? 1 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) ep_ctx = &xudc->ep_context[ep];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) if ((xudc->device_state != USB_STATE_CONFIGURED) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) ((xudc->device_state != USB_STATE_ADDRESS) || (ep != 0)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) if (ep_ctx_read_state(ep_ctx) == EP_STATE_DISABLED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) if (xudc_readl(xudc, EP_HALT) & BIT(ep))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) status |= BIT(USB_ENDPOINT_HALT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) xudc->status_buf = cpu_to_le16(status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) return tegra_xudc_ep0_queue_data(xudc, &xudc->status_buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) sizeof(xudc->status_buf),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) no_op_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) static void set_sel_complete(struct usb_ep *ep, struct usb_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) /* Nothing to do with SEL values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) static int tegra_xudc_ep0_set_sel(struct tegra_xudc *xudc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) struct usb_ctrlrequest *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) if (ctrl->bRequestType != (USB_DIR_OUT | USB_RECIP_DEVICE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) USB_TYPE_STANDARD))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) if (xudc->device_state == USB_STATE_DEFAULT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) if ((le16_to_cpu(ctrl->wIndex) != 0) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) (le16_to_cpu(ctrl->wValue) != 0) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) (le16_to_cpu(ctrl->wLength) != 6))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) return tegra_xudc_ep0_queue_data(xudc, &xudc->sel_timing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) sizeof(xudc->sel_timing),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) set_sel_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) static void set_isoch_delay_complete(struct usb_ep *ep, struct usb_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) /* Nothing to do with isoch delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) static int tegra_xudc_ep0_set_isoch_delay(struct tegra_xudc *xudc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) struct usb_ctrlrequest *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) u32 delay = le16_to_cpu(ctrl->wValue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) if (ctrl->bRequestType != (USB_DIR_OUT | USB_RECIP_DEVICE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) USB_TYPE_STANDARD))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) if ((delay > 65535) || (le16_to_cpu(ctrl->wIndex) != 0) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) (le16_to_cpu(ctrl->wLength) != 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) xudc->isoch_delay = delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) return tegra_xudc_ep0_queue_status(xudc, set_isoch_delay_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) static void set_address_complete(struct usb_ep *ep, struct usb_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) struct tegra_xudc *xudc = req->context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) if ((xudc->device_state == USB_STATE_DEFAULT) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) (xudc->dev_addr != 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) xudc->device_state = USB_STATE_ADDRESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) usb_gadget_set_state(&xudc->gadget, xudc->device_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) } else if ((xudc->device_state == USB_STATE_ADDRESS) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) (xudc->dev_addr == 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) xudc->device_state = USB_STATE_DEFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483) usb_gadget_set_state(&xudc->gadget, xudc->device_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) static int tegra_xudc_ep0_set_address(struct tegra_xudc *xudc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) struct usb_ctrlrequest *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490) struct tegra_xudc_ep *ep0 = &xudc->ep[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) u32 val, addr = le16_to_cpu(ctrl->wValue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) if (ctrl->bRequestType != (USB_DIR_OUT | USB_RECIP_DEVICE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) USB_TYPE_STANDARD))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497) if ((addr > 127) || (le16_to_cpu(ctrl->wIndex) != 0) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) (le16_to_cpu(ctrl->wLength) != 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501) if (xudc->device_state == USB_STATE_CONFIGURED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504) dev_dbg(xudc->dev, "set address: %u\n", addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) xudc->dev_addr = addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507) val = xudc_readl(xudc, CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) val &= ~(CTRL_DEVADDR_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) val |= CTRL_DEVADDR(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) xudc_writel(xudc, val, CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) ep_ctx_write_devaddr(ep0->context, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514) return tegra_xudc_ep0_queue_status(xudc, set_address_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517) static int tegra_xudc_ep0_standard_req(struct tegra_xudc *xudc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) struct usb_ctrlrequest *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) switch (ctrl->bRequest) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) case USB_REQ_GET_STATUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524) dev_dbg(xudc->dev, "USB_REQ_GET_STATUS\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) ret = tegra_xudc_ep0_get_status(xudc, ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) case USB_REQ_SET_ADDRESS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528) dev_dbg(xudc->dev, "USB_REQ_SET_ADDRESS\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) ret = tegra_xudc_ep0_set_address(xudc, ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531) case USB_REQ_SET_SEL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532) dev_dbg(xudc->dev, "USB_REQ_SET_SEL\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) ret = tegra_xudc_ep0_set_sel(xudc, ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535) case USB_REQ_SET_ISOCH_DELAY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) dev_dbg(xudc->dev, "USB_REQ_SET_ISOCH_DELAY\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537) ret = tegra_xudc_ep0_set_isoch_delay(xudc, ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539) case USB_REQ_CLEAR_FEATURE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540) case USB_REQ_SET_FEATURE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) dev_dbg(xudc->dev, "USB_REQ_CLEAR/SET_FEATURE\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542) ret = tegra_xudc_ep0_set_feature(xudc, ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) case USB_REQ_SET_CONFIGURATION:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545) dev_dbg(xudc->dev, "USB_REQ_SET_CONFIGURATION\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547) * In theory we need to clear RUN bit before status stage of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) * deconfig request sent, but this seems to be causing problems.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549) * Clear RUN once all endpoints are disabled instead.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553) ret = tegra_xudc_ep0_delegate_req(xudc, ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560) static void tegra_xudc_handle_ep0_setup_packet(struct tegra_xudc *xudc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561) struct usb_ctrlrequest *ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562) u16 seq_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566) xudc->setup_seq_num = seq_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568) /* Ensure EP0 is unhalted. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569) ep_unhalt(xudc, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572) * On Tegra210, setup packets with sequence numbers 0xfffe or 0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) * are invalid. Halt EP0 until we get a valid packet.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575) if (xudc->soc->invalid_seq_num &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576) (seq_num == 0xfffe || seq_num == 0xffff)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577) dev_warn(xudc->dev, "invalid sequence number detected\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578) ep_halt(xudc, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582) if (ctrl->wLength)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583) xudc->setup_state = (ctrl->bRequestType & USB_DIR_IN) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584) DATA_STAGE_XFER : DATA_STAGE_RECV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586) xudc->setup_state = STATUS_STAGE_XFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588) if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589) ret = tegra_xudc_ep0_standard_req(xudc, ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591) ret = tegra_xudc_ep0_delegate_req(xudc, ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) dev_warn(xudc->dev, "setup request failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595) xudc->setup_state = WAIT_FOR_SETUP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596) ep_halt(xudc, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600) static void tegra_xudc_handle_ep0_event(struct tegra_xudc *xudc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601) struct tegra_xudc_trb *event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603) struct usb_ctrlrequest *ctrl = (struct usb_ctrlrequest *)event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604) u16 seq_num = trb_read_seq_num(event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606) if (xudc->setup_state != WAIT_FOR_SETUP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608) * The controller is in the process of handling another
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609) * setup request. Queue subsequent requests and handle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610) * the last one once the controller reports a sequence
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611) * number error.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613) memcpy(&xudc->setup_packet.ctrl_req, ctrl, sizeof(*ctrl));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614) xudc->setup_packet.seq_num = seq_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615) xudc->queued_setup_packet = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617) tegra_xudc_handle_ep0_setup_packet(xudc, ctrl, seq_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621) static struct tegra_xudc_request *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622) trb_to_request(struct tegra_xudc_ep *ep, struct tegra_xudc_trb *trb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624) struct tegra_xudc_request *req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626) list_for_each_entry(req, &ep->queue, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627) if (!req->trbs_queued)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630) if (trb_in_request(ep, req, trb))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631) return req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637) static void tegra_xudc_handle_transfer_completion(struct tegra_xudc *xudc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638) struct tegra_xudc_ep *ep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639) struct tegra_xudc_trb *event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641) struct tegra_xudc_request *req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642) struct tegra_xudc_trb *trb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643) bool short_packet;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645) short_packet = (trb_read_cmpl_code(event) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646) TRB_CMPL_CODE_SHORT_PACKET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648) trb = trb_phys_to_virt(ep, trb_read_data_ptr(event));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649) req = trb_to_request(ep, trb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652) * TDs are complete on short packet or when the completed TRB is the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653) * last TRB in the TD (the CHAIN bit is unset).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655) if (req && (short_packet || (!trb_read_chain(trb) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656) (req->trbs_needed == req->trbs_queued)))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657) struct tegra_xudc_trb *last = req->last_trb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658) unsigned int residual;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660) residual = trb_read_transfer_len(event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661) req->usb_req.actual = req->usb_req.length - residual;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663) dev_dbg(xudc->dev, "bytes transferred %u / %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664) req->usb_req.actual, req->usb_req.length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666) tegra_xudc_req_done(ep, req, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668) if (ep->desc && usb_endpoint_xfer_control(ep->desc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669) tegra_xudc_ep0_req_done(xudc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672) * Advance the dequeue pointer past the end of the current TD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673) * on short packet completion.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675) if (short_packet) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2676) ep->deq_ptr = (last - ep->transfer_ring) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2677) if (ep->deq_ptr == XUDC_TRANSFER_RING_SIZE - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2678) ep->deq_ptr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2679) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2680) } else if (!req) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2681) dev_warn(xudc->dev, "transfer event on dequeued request\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2682) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2684) if (ep->desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2685) tegra_xudc_ep_kick_queue(ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2686) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2688) static void tegra_xudc_handle_transfer_event(struct tegra_xudc *xudc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2689) struct tegra_xudc_trb *event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2690) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2691) unsigned int ep_index = trb_read_endpoint_id(event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2692) struct tegra_xudc_ep *ep = &xudc->ep[ep_index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2693) struct tegra_xudc_trb *trb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2694) u16 comp_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2696) if (ep_ctx_read_state(ep->context) == EP_STATE_DISABLED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2697) dev_warn(xudc->dev, "transfer event on disabled EP %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2698) ep_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2699) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2700) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2702) /* Update transfer ring dequeue pointer. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2703) trb = trb_phys_to_virt(ep, trb_read_data_ptr(event));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2704) comp_code = trb_read_cmpl_code(event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2705) if (comp_code != TRB_CMPL_CODE_BABBLE_DETECTED_ERR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2706) ep->deq_ptr = (trb - ep->transfer_ring) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2708) if (ep->deq_ptr == XUDC_TRANSFER_RING_SIZE - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2709) ep->deq_ptr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2710) ep->ring_full = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2711) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2713) switch (comp_code) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2714) case TRB_CMPL_CODE_SUCCESS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2715) case TRB_CMPL_CODE_SHORT_PACKET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2716) tegra_xudc_handle_transfer_completion(xudc, ep, event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2717) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2718) case TRB_CMPL_CODE_HOST_REJECTED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2719) dev_info(xudc->dev, "stream rejected on EP %u\n", ep_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2721) ep->stream_rejected = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2722) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2723) case TRB_CMPL_CODE_PRIME_PIPE_RECEIVED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2724) dev_info(xudc->dev, "prime pipe received on EP %u\n", ep_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2726) if (ep->stream_rejected) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2727) ep->stream_rejected = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2728) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2729) * An EP is stopped when a stream is rejected. Wait
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2730) * for the EP to report that it is stopped and then
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2731) * un-stop it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2732) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2733) ep_wait_for_stopped(xudc, ep_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2734) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2735) tegra_xudc_ep_ring_doorbell(ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2736) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2737) case TRB_CMPL_CODE_BABBLE_DETECTED_ERR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2738) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2739) * Wait for the EP to be stopped so the controller stops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2740) * processing doorbells.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2741) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2742) ep_wait_for_stopped(xudc, ep_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2743) ep->enq_ptr = ep->deq_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2744) tegra_xudc_ep_nuke(ep, -EIO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2745) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2746) case TRB_CMPL_CODE_STREAM_NUMP_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2747) case TRB_CMPL_CODE_CTRL_DIR_ERR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2748) case TRB_CMPL_CODE_INVALID_STREAM_TYPE_ERR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2749) case TRB_CMPL_CODE_RING_UNDERRUN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2750) case TRB_CMPL_CODE_RING_OVERRUN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2751) case TRB_CMPL_CODE_ISOCH_BUFFER_OVERRUN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2752) case TRB_CMPL_CODE_USB_TRANS_ERR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2753) case TRB_CMPL_CODE_TRB_ERR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2754) dev_err(xudc->dev, "completion error %#x on EP %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2755) comp_code, ep_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2757) ep_halt(xudc, ep_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2758) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2759) case TRB_CMPL_CODE_CTRL_SEQNUM_ERR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2760) dev_info(xudc->dev, "sequence number error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2762) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2763) * Kill any queued control request and skip to the last
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2764) * setup packet we received.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2765) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2766) tegra_xudc_ep_nuke(ep, -EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2767) xudc->setup_state = WAIT_FOR_SETUP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2768) if (!xudc->queued_setup_packet)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2769) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2771) tegra_xudc_handle_ep0_setup_packet(xudc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2772) &xudc->setup_packet.ctrl_req,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2773) xudc->setup_packet.seq_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2774) xudc->queued_setup_packet = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2775) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2776) case TRB_CMPL_CODE_STOPPED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2777) dev_dbg(xudc->dev, "stop completion code on EP %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2778) ep_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2780) /* Disconnected. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2781) tegra_xudc_ep_nuke(ep, -ECONNREFUSED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2782) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2783) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2784) dev_dbg(xudc->dev, "completion event %#x on EP %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2785) comp_code, ep_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2786) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2787) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2788) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2790) static void tegra_xudc_reset(struct tegra_xudc *xudc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2791) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2792) struct tegra_xudc_ep *ep0 = &xudc->ep[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2793) dma_addr_t deq_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2794) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2796) xudc->setup_state = WAIT_FOR_SETUP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2797) xudc->device_state = USB_STATE_DEFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2798) usb_gadget_set_state(&xudc->gadget, xudc->device_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2800) ep_unpause_all(xudc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2802) for (i = 0; i < ARRAY_SIZE(xudc->ep); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2803) tegra_xudc_ep_nuke(&xudc->ep[i], -ESHUTDOWN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2805) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2806) * Reset sequence number and dequeue pointer to flush the transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2807) * ring.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2808) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2809) ep0->deq_ptr = ep0->enq_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2810) ep0->ring_full = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2812) xudc->setup_seq_num = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2813) xudc->queued_setup_packet = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2815) ep_ctx_write_seq_num(ep0->context, xudc->setup_seq_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2817) deq_ptr = trb_virt_to_phys(ep0, &ep0->transfer_ring[ep0->deq_ptr]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2819) if (!dma_mapping_error(xudc->dev, deq_ptr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2820) ep_ctx_write_deq_ptr(ep0->context, deq_ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2821) ep_ctx_write_dcs(ep0->context, ep0->pcs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2822) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2824) ep_unhalt_all(xudc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2825) ep_reload(xudc, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2826) ep_unpause(xudc, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2827) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2829) static void tegra_xudc_port_connect(struct tegra_xudc *xudc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2830) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2831) struct tegra_xudc_ep *ep0 = &xudc->ep[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2832) u16 maxpacket;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2833) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2835) val = (xudc_readl(xudc, PORTSC) & PORTSC_PS_MASK) >> PORTSC_PS_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2836) switch (val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2837) case PORTSC_PS_LS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2838) xudc->gadget.speed = USB_SPEED_LOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2839) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2840) case PORTSC_PS_FS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2841) xudc->gadget.speed = USB_SPEED_FULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2842) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2843) case PORTSC_PS_HS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2844) xudc->gadget.speed = USB_SPEED_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2845) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2846) case PORTSC_PS_SS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2847) xudc->gadget.speed = USB_SPEED_SUPER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2848) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2849) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2850) xudc->gadget.speed = USB_SPEED_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2851) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2852) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2854) xudc->device_state = USB_STATE_DEFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2855) usb_gadget_set_state(&xudc->gadget, xudc->device_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2857) xudc->setup_state = WAIT_FOR_SETUP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2859) if (xudc->gadget.speed == USB_SPEED_SUPER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2860) maxpacket = 512;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2861) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2862) maxpacket = 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2864) ep_ctx_write_max_packet_size(ep0->context, maxpacket);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2865) tegra_xudc_ep0_desc.wMaxPacketSize = cpu_to_le16(maxpacket);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2866) usb_ep_set_maxpacket_limit(&ep0->usb_ep, maxpacket);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2868) if (!xudc->soc->u1_enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2869) val = xudc_readl(xudc, PORTPM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2870) val &= ~(PORTPM_U1TIMEOUT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2871) xudc_writel(xudc, val, PORTPM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2872) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2874) if (!xudc->soc->u2_enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2875) val = xudc_readl(xudc, PORTPM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2876) val &= ~(PORTPM_U2TIMEOUT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2877) xudc_writel(xudc, val, PORTPM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2878) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2880) if (xudc->gadget.speed <= USB_SPEED_HIGH) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2881) val = xudc_readl(xudc, PORTPM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2882) val &= ~(PORTPM_L1S_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2883) if (xudc->soc->lpm_enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2884) val |= PORTPM_L1S(PORTPM_L1S_ACCEPT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2885) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2886) val |= PORTPM_L1S(PORTPM_L1S_NYET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2887) xudc_writel(xudc, val, PORTPM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2888) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2890) val = xudc_readl(xudc, ST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2891) if (val & ST_RC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2892) xudc_writel(xudc, ST_RC, ST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2893) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2895) static void tegra_xudc_port_disconnect(struct tegra_xudc *xudc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2896) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2897) tegra_xudc_reset(xudc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2899) if (xudc->driver && xudc->driver->disconnect) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2900) spin_unlock(&xudc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2901) xudc->driver->disconnect(&xudc->gadget);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2902) spin_lock(&xudc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2903) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2905) xudc->device_state = USB_STATE_NOTATTACHED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2906) usb_gadget_set_state(&xudc->gadget, xudc->device_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2908) complete(&xudc->disconnect_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2909) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2911) static void tegra_xudc_port_reset(struct tegra_xudc *xudc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2912) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2913) tegra_xudc_reset(xudc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2915) if (xudc->driver) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2916) spin_unlock(&xudc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2917) usb_gadget_udc_reset(&xudc->gadget, xudc->driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2918) spin_lock(&xudc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2919) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2921) tegra_xudc_port_connect(xudc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2922) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2924) static void tegra_xudc_port_suspend(struct tegra_xudc *xudc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2925) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2926) dev_dbg(xudc->dev, "port suspend\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2928) xudc->resume_state = xudc->device_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2929) xudc->device_state = USB_STATE_SUSPENDED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2930) usb_gadget_set_state(&xudc->gadget, xudc->device_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2932) if (xudc->driver->suspend) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2933) spin_unlock(&xudc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2934) xudc->driver->suspend(&xudc->gadget);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2935) spin_lock(&xudc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2936) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2937) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2939) static void tegra_xudc_port_resume(struct tegra_xudc *xudc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2940) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2941) dev_dbg(xudc->dev, "port resume\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2943) tegra_xudc_resume_device_state(xudc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2945) if (xudc->driver->resume) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2946) spin_unlock(&xudc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2947) xudc->driver->resume(&xudc->gadget);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2948) spin_lock(&xudc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2949) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2950) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2952) static inline void clear_port_change(struct tegra_xudc *xudc, u32 flag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2953) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2954) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2956) val = xudc_readl(xudc, PORTSC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2957) val &= ~PORTSC_CHANGE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2958) val |= flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2959) xudc_writel(xudc, val, PORTSC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2960) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2962) static void __tegra_xudc_handle_port_status(struct tegra_xudc *xudc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2963) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2964) u32 portsc, porthalt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2966) porthalt = xudc_readl(xudc, PORTHALT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2967) if ((porthalt & PORTHALT_STCHG_REQ) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2968) (porthalt & PORTHALT_HALT_LTSSM)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2969) dev_dbg(xudc->dev, "STCHG_REQ, PORTHALT = %#x\n", porthalt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2970) porthalt &= ~PORTHALT_HALT_LTSSM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2971) xudc_writel(xudc, porthalt, PORTHALT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2972) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2974) portsc = xudc_readl(xudc, PORTSC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2975) if ((portsc & PORTSC_PRC) && (portsc & PORTSC_PR)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2976) dev_dbg(xudc->dev, "PRC, PR, PORTSC = %#x\n", portsc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2977) clear_port_change(xudc, PORTSC_PRC | PORTSC_PED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2978) #define TOGGLE_VBUS_WAIT_MS 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2979) if (xudc->soc->port_reset_quirk) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2980) schedule_delayed_work(&xudc->port_reset_war_work,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2981) msecs_to_jiffies(TOGGLE_VBUS_WAIT_MS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2982) xudc->wait_for_sec_prc = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2983) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2984) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2986) if ((portsc & PORTSC_PRC) && !(portsc & PORTSC_PR)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2987) dev_dbg(xudc->dev, "PRC, Not PR, PORTSC = %#x\n", portsc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2988) clear_port_change(xudc, PORTSC_PRC | PORTSC_PED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2989) tegra_xudc_port_reset(xudc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2990) cancel_delayed_work(&xudc->port_reset_war_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2991) xudc->wait_for_sec_prc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2992) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2994) portsc = xudc_readl(xudc, PORTSC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2995) if (portsc & PORTSC_WRC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2996) dev_dbg(xudc->dev, "WRC, PORTSC = %#x\n", portsc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2997) clear_port_change(xudc, PORTSC_WRC | PORTSC_PED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2998) if (!(xudc_readl(xudc, PORTSC) & PORTSC_WPR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2999) tegra_xudc_port_reset(xudc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3000) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3002) portsc = xudc_readl(xudc, PORTSC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3003) if (portsc & PORTSC_CSC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3004) dev_dbg(xudc->dev, "CSC, PORTSC = %#x\n", portsc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3005) clear_port_change(xudc, PORTSC_CSC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3007) if (portsc & PORTSC_CCS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3008) tegra_xudc_port_connect(xudc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3009) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3010) tegra_xudc_port_disconnect(xudc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3012) if (xudc->wait_csc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3013) cancel_delayed_work(&xudc->plc_reset_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3014) xudc->wait_csc = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3015) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3016) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3018) portsc = xudc_readl(xudc, PORTSC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3019) if (portsc & PORTSC_PLC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3020) u32 pls = (portsc & PORTSC_PLS_MASK) >> PORTSC_PLS_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3022) dev_dbg(xudc->dev, "PLC, PORTSC = %#x\n", portsc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3023) clear_port_change(xudc, PORTSC_PLC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3024) switch (pls) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3025) case PORTSC_PLS_U3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3026) tegra_xudc_port_suspend(xudc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3027) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3028) case PORTSC_PLS_U0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3029) if (xudc->gadget.speed < USB_SPEED_SUPER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3030) tegra_xudc_port_resume(xudc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3031) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3032) case PORTSC_PLS_RESUME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3033) if (xudc->gadget.speed == USB_SPEED_SUPER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3034) tegra_xudc_port_resume(xudc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3035) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3036) case PORTSC_PLS_INACTIVE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3037) schedule_delayed_work(&xudc->plc_reset_work,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3038) msecs_to_jiffies(TOGGLE_VBUS_WAIT_MS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3039) xudc->wait_csc = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3040) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3041) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3042) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3043) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3044) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3046) if (portsc & PORTSC_CEC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3047) dev_warn(xudc->dev, "CEC, PORTSC = %#x\n", portsc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3048) clear_port_change(xudc, PORTSC_CEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3049) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3051) dev_dbg(xudc->dev, "PORTSC = %#x\n", xudc_readl(xudc, PORTSC));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3052) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3054) static void tegra_xudc_handle_port_status(struct tegra_xudc *xudc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3055) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3056) while ((xudc_readl(xudc, PORTSC) & PORTSC_CHANGE_MASK) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3057) (xudc_readl(xudc, PORTHALT) & PORTHALT_STCHG_REQ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3058) __tegra_xudc_handle_port_status(xudc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3059) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3061) static void tegra_xudc_handle_event(struct tegra_xudc *xudc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3062) struct tegra_xudc_trb *event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3063) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3064) u32 type = trb_read_type(event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3066) dump_trb(xudc, "EVENT", event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3068) switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3069) case TRB_TYPE_PORT_STATUS_CHANGE_EVENT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3070) tegra_xudc_handle_port_status(xudc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3071) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3072) case TRB_TYPE_TRANSFER_EVENT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3073) tegra_xudc_handle_transfer_event(xudc, event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3074) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3075) case TRB_TYPE_SETUP_PACKET_EVENT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3076) tegra_xudc_handle_ep0_event(xudc, event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3077) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3078) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3079) dev_info(xudc->dev, "Unrecognized TRB type = %#x\n", type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3080) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3081) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3082) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3084) static void tegra_xudc_process_event_ring(struct tegra_xudc *xudc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3085) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3086) struct tegra_xudc_trb *event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3087) dma_addr_t erdp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3089) while (true) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3090) event = xudc->event_ring[xudc->event_ring_index] +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3091) xudc->event_ring_deq_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3093) if (trb_read_cycle(event) != xudc->ccs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3094) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3096) tegra_xudc_handle_event(xudc, event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3098) xudc->event_ring_deq_ptr++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3099) if (xudc->event_ring_deq_ptr == XUDC_EVENT_RING_SIZE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3100) xudc->event_ring_deq_ptr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3101) xudc->event_ring_index++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3104) if (xudc->event_ring_index == XUDC_NR_EVENT_RINGS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3105) xudc->event_ring_index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3106) xudc->ccs = !xudc->ccs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3110) erdp = xudc->event_ring_phys[xudc->event_ring_index] +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3111) xudc->event_ring_deq_ptr * sizeof(*event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3113) xudc_writel(xudc, upper_32_bits(erdp), ERDPHI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3114) xudc_writel(xudc, lower_32_bits(erdp) | ERDPLO_EHB, ERDPLO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3117) static irqreturn_t tegra_xudc_irq(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3118) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3119) struct tegra_xudc *xudc = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3120) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3121) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3123) val = xudc_readl(xudc, ST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3124) if (!(val & ST_IP))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3125) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3126) xudc_writel(xudc, ST_IP, ST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3128) spin_lock_irqsave(&xudc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3129) tegra_xudc_process_event_ring(xudc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3130) spin_unlock_irqrestore(&xudc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3132) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3135) static int tegra_xudc_alloc_ep(struct tegra_xudc *xudc, unsigned int index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3137) struct tegra_xudc_ep *ep = &xudc->ep[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3139) ep->xudc = xudc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3140) ep->index = index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3141) ep->context = &xudc->ep_context[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3142) INIT_LIST_HEAD(&ep->queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3144) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3145) * EP1 would be the input endpoint corresponding to EP0, but since
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3146) * EP0 is bi-directional, EP1 is unused.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3147) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3148) if (index == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3149) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3151) ep->transfer_ring = dma_pool_alloc(xudc->transfer_ring_pool,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3152) GFP_KERNEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3153) &ep->transfer_ring_phys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3154) if (!ep->transfer_ring)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3155) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3157) if (index) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3158) snprintf(ep->name, sizeof(ep->name), "ep%u%s", index / 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3159) (index % 2 == 0) ? "out" : "in");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3160) ep->usb_ep.name = ep->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3161) usb_ep_set_maxpacket_limit(&ep->usb_ep, 1024);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3162) ep->usb_ep.max_streams = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3163) ep->usb_ep.ops = &tegra_xudc_ep_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3164) ep->usb_ep.caps.type_bulk = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3165) ep->usb_ep.caps.type_int = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3166) if (index & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3167) ep->usb_ep.caps.dir_in = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3168) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3169) ep->usb_ep.caps.dir_out = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3170) list_add_tail(&ep->usb_ep.ep_list, &xudc->gadget.ep_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3171) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3172) strscpy(ep->name, "ep0", 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3173) ep->usb_ep.name = ep->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3174) usb_ep_set_maxpacket_limit(&ep->usb_ep, 512);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3175) ep->usb_ep.ops = &tegra_xudc_ep0_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3176) ep->usb_ep.caps.type_control = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3177) ep->usb_ep.caps.dir_in = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3178) ep->usb_ep.caps.dir_out = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3181) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3184) static void tegra_xudc_free_ep(struct tegra_xudc *xudc, unsigned int index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3185) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3186) struct tegra_xudc_ep *ep = &xudc->ep[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3188) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3189) * EP1 would be the input endpoint corresponding to EP0, but since
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3190) * EP0 is bi-directional, EP1 is unused.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3191) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3192) if (index == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3193) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3195) dma_pool_free(xudc->transfer_ring_pool, ep->transfer_ring,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3196) ep->transfer_ring_phys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3199) static int tegra_xudc_alloc_eps(struct tegra_xudc *xudc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3200) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3201) struct usb_request *req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3202) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3203) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3205) xudc->ep_context =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3206) dma_alloc_coherent(xudc->dev, XUDC_NR_EPS *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3207) sizeof(*xudc->ep_context),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3208) &xudc->ep_context_phys, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3209) if (!xudc->ep_context)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3210) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3212) xudc->transfer_ring_pool =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3213) dmam_pool_create(dev_name(xudc->dev), xudc->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3214) XUDC_TRANSFER_RING_SIZE *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3215) sizeof(struct tegra_xudc_trb),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3216) sizeof(struct tegra_xudc_trb), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3217) if (!xudc->transfer_ring_pool) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3218) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3219) goto free_ep_context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3222) INIT_LIST_HEAD(&xudc->gadget.ep_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3223) for (i = 0; i < ARRAY_SIZE(xudc->ep); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3224) err = tegra_xudc_alloc_ep(xudc, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3225) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3226) goto free_eps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3229) req = tegra_xudc_ep_alloc_request(&xudc->ep[0].usb_ep, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3230) if (!req) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3231) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3232) goto free_eps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3234) xudc->ep0_req = to_xudc_req(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3236) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3238) free_eps:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3239) for (; i > 0; i--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3240) tegra_xudc_free_ep(xudc, i - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3241) free_ep_context:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3242) dma_free_coherent(xudc->dev, XUDC_NR_EPS * sizeof(*xudc->ep_context),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3243) xudc->ep_context, xudc->ep_context_phys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3244) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3247) static void tegra_xudc_init_eps(struct tegra_xudc *xudc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3248) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3249) xudc_writel(xudc, lower_32_bits(xudc->ep_context_phys), ECPLO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3250) xudc_writel(xudc, upper_32_bits(xudc->ep_context_phys), ECPHI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3253) static void tegra_xudc_free_eps(struct tegra_xudc *xudc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3254) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3255) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3257) tegra_xudc_ep_free_request(&xudc->ep[0].usb_ep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3258) &xudc->ep0_req->usb_req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3260) for (i = 0; i < ARRAY_SIZE(xudc->ep); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3261) tegra_xudc_free_ep(xudc, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3263) dma_free_coherent(xudc->dev, XUDC_NR_EPS * sizeof(*xudc->ep_context),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3264) xudc->ep_context, xudc->ep_context_phys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3267) static int tegra_xudc_alloc_event_ring(struct tegra_xudc *xudc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3268) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3269) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3271) for (i = 0; i < ARRAY_SIZE(xudc->event_ring); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3272) xudc->event_ring[i] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3273) dma_alloc_coherent(xudc->dev, XUDC_EVENT_RING_SIZE *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3274) sizeof(*xudc->event_ring[i]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3275) &xudc->event_ring_phys[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3276) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3277) if (!xudc->event_ring[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3278) goto free_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3281) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3283) free_dma:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3284) for (; i > 0; i--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3285) dma_free_coherent(xudc->dev, XUDC_EVENT_RING_SIZE *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3286) sizeof(*xudc->event_ring[i - 1]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3287) xudc->event_ring[i - 1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3288) xudc->event_ring_phys[i - 1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3290) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3291) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3293) static void tegra_xudc_init_event_ring(struct tegra_xudc *xudc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3294) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3295) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3296) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3298) val = xudc_readl(xudc, SPARAM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3299) val &= ~(SPARAM_ERSTMAX_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3300) val |= SPARAM_ERSTMAX(XUDC_NR_EVENT_RINGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3301) xudc_writel(xudc, val, SPARAM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3303) for (i = 0; i < ARRAY_SIZE(xudc->event_ring); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3304) memset(xudc->event_ring[i], 0, XUDC_EVENT_RING_SIZE *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3305) sizeof(*xudc->event_ring[i]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3307) val = xudc_readl(xudc, ERSTSZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3308) val &= ~(ERSTSZ_ERSTXSZ_MASK << ERSTSZ_ERSTXSZ_SHIFT(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3309) val |= XUDC_EVENT_RING_SIZE << ERSTSZ_ERSTXSZ_SHIFT(i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3310) xudc_writel(xudc, val, ERSTSZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3312) xudc_writel(xudc, lower_32_bits(xudc->event_ring_phys[i]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3313) ERSTXBALO(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3314) xudc_writel(xudc, upper_32_bits(xudc->event_ring_phys[i]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3315) ERSTXBAHI(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3318) val = lower_32_bits(xudc->event_ring_phys[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3319) xudc_writel(xudc, val, ERDPLO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3320) val |= EREPLO_ECS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3321) xudc_writel(xudc, val, EREPLO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3323) val = upper_32_bits(xudc->event_ring_phys[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3324) xudc_writel(xudc, val, ERDPHI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3325) xudc_writel(xudc, val, EREPHI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3327) xudc->ccs = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3328) xudc->event_ring_index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3329) xudc->event_ring_deq_ptr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3332) static void tegra_xudc_free_event_ring(struct tegra_xudc *xudc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3333) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3334) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3336) for (i = 0; i < ARRAY_SIZE(xudc->event_ring); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3337) dma_free_coherent(xudc->dev, XUDC_EVENT_RING_SIZE *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3338) sizeof(*xudc->event_ring[i]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3339) xudc->event_ring[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3340) xudc->event_ring_phys[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3344) static void tegra_xudc_fpci_ipfs_init(struct tegra_xudc *xudc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3345) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3346) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3348) if (xudc->soc->has_ipfs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3349) val = ipfs_readl(xudc, XUSB_DEV_CONFIGURATION_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3350) val |= XUSB_DEV_CONFIGURATION_0_EN_FPCI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3351) ipfs_writel(xudc, val, XUSB_DEV_CONFIGURATION_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3352) usleep_range(10, 15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3355) /* Enable bus master */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3356) val = XUSB_DEV_CFG_1_IO_SPACE_EN | XUSB_DEV_CFG_1_MEMORY_SPACE_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3357) XUSB_DEV_CFG_1_BUS_MASTER_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3358) fpci_writel(xudc, val, XUSB_DEV_CFG_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3360) /* Program BAR0 space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3361) val = fpci_readl(xudc, XUSB_DEV_CFG_4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3362) val &= ~(XUSB_DEV_CFG_4_BASE_ADDR_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3363) val |= xudc->phys_base & (XUSB_DEV_CFG_4_BASE_ADDR_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3365) fpci_writel(xudc, val, XUSB_DEV_CFG_4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3366) fpci_writel(xudc, upper_32_bits(xudc->phys_base), XUSB_DEV_CFG_5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3368) usleep_range(100, 200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3370) if (xudc->soc->has_ipfs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3371) /* Enable interrupt assertion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3372) val = ipfs_readl(xudc, XUSB_DEV_INTR_MASK_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3373) val |= XUSB_DEV_INTR_MASK_0_IP_INT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3374) ipfs_writel(xudc, val, XUSB_DEV_INTR_MASK_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3378) static void tegra_xudc_device_params_init(struct tegra_xudc *xudc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3379) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3380) u32 val, imod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3382) if (xudc->soc->has_ipfs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3383) val = xudc_readl(xudc, BLCG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3384) val |= BLCG_ALL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3385) val &= ~(BLCG_DFPCI | BLCG_UFPCI | BLCG_FE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3386) BLCG_COREPLL_PWRDN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3387) val |= BLCG_IOPLL_0_PWRDN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3388) val |= BLCG_IOPLL_1_PWRDN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3389) val |= BLCG_IOPLL_2_PWRDN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3391) xudc_writel(xudc, val, BLCG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3392) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3394) if (xudc->soc->port_speed_quirk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3395) tegra_xudc_limit_port_speed(xudc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3397) /* Set a reasonable U3 exit timer value. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3398) val = xudc_readl(xudc, SSPX_CORE_PADCTL4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3399) val &= ~(SSPX_CORE_PADCTL4_RXDAT_VLD_TIMEOUT_U3_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3400) val |= SSPX_CORE_PADCTL4_RXDAT_VLD_TIMEOUT_U3(0x5dc0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3401) xudc_writel(xudc, val, SSPX_CORE_PADCTL4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3403) /* Default ping LFPS tBurst is too large. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3404) val = xudc_readl(xudc, SSPX_CORE_CNT0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3405) val &= ~(SSPX_CORE_CNT0_PING_TBURST_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3406) val |= SSPX_CORE_CNT0_PING_TBURST(0xa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3407) xudc_writel(xudc, val, SSPX_CORE_CNT0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3409) /* Default tPortConfiguration timeout is too small. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3410) val = xudc_readl(xudc, SSPX_CORE_CNT30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3411) val &= ~(SSPX_CORE_CNT30_LMPITP_TIMER_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3412) val |= SSPX_CORE_CNT30_LMPITP_TIMER(0x978);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3413) xudc_writel(xudc, val, SSPX_CORE_CNT30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3415) if (xudc->soc->lpm_enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3416) /* Set L1 resume duration to 95 us. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3417) val = xudc_readl(xudc, HSFSPI_COUNT13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3418) val &= ~(HSFSPI_COUNT13_U2_RESUME_K_DURATION_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3419) val |= HSFSPI_COUNT13_U2_RESUME_K_DURATION(0x2c88);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3420) xudc_writel(xudc, val, HSFSPI_COUNT13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3421) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3423) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3424) * Compliacne suite appears to be violating polling LFPS tBurst max
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3425) * of 1.4us. Send 1.45us instead.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3426) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3427) val = xudc_readl(xudc, SSPX_CORE_CNT32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3428) val &= ~(SSPX_CORE_CNT32_POLL_TBURST_MAX_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3429) val |= SSPX_CORE_CNT32_POLL_TBURST_MAX(0xb0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3430) xudc_writel(xudc, val, SSPX_CORE_CNT32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3432) /* Direct HS/FS port instance to RxDetect. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3433) val = xudc_readl(xudc, CFG_DEV_FE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3434) val &= ~(CFG_DEV_FE_PORTREGSEL_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3435) val |= CFG_DEV_FE_PORTREGSEL(CFG_DEV_FE_PORTREGSEL_HSFS_PI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3436) xudc_writel(xudc, val, CFG_DEV_FE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3438) val = xudc_readl(xudc, PORTSC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3439) val &= ~(PORTSC_CHANGE_MASK | PORTSC_PLS_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3440) val |= PORTSC_LWS | PORTSC_PLS(PORTSC_PLS_RXDETECT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3441) xudc_writel(xudc, val, PORTSC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3443) /* Direct SS port instance to RxDetect. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3444) val = xudc_readl(xudc, CFG_DEV_FE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3445) val &= ~(CFG_DEV_FE_PORTREGSEL_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3446) val |= CFG_DEV_FE_PORTREGSEL_SS_PI & CFG_DEV_FE_PORTREGSEL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3447) xudc_writel(xudc, val, CFG_DEV_FE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3449) val = xudc_readl(xudc, PORTSC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3450) val &= ~(PORTSC_CHANGE_MASK | PORTSC_PLS_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3451) val |= PORTSC_LWS | PORTSC_PLS(PORTSC_PLS_RXDETECT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3452) xudc_writel(xudc, val, PORTSC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3454) /* Restore port instance. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3455) val = xudc_readl(xudc, CFG_DEV_FE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3456) val &= ~(CFG_DEV_FE_PORTREGSEL_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3457) xudc_writel(xudc, val, CFG_DEV_FE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3459) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3460) * Enable INFINITE_SS_RETRY to prevent device from entering
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3461) * Disabled.Error when attached to buggy SuperSpeed hubs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3462) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3463) val = xudc_readl(xudc, CFG_DEV_FE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3464) val |= CFG_DEV_FE_INFINITE_SS_RETRY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3465) xudc_writel(xudc, val, CFG_DEV_FE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3467) /* Set interrupt moderation. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3468) imod = XUDC_INTERRUPT_MODERATION_US * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3469) val = xudc_readl(xudc, RT_IMOD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3470) val &= ~((RT_IMOD_IMODI_MASK) | (RT_IMOD_IMODC_MASK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3471) val |= (RT_IMOD_IMODI(imod) | RT_IMOD_IMODC(imod));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3472) xudc_writel(xudc, val, RT_IMOD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3474) /* increase SSPI transaction timeout from 32us to 512us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3475) val = xudc_readl(xudc, CFG_DEV_SSPI_XFER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3476) val &= ~(CFG_DEV_SSPI_XFER_ACKTIMEOUT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3477) val |= CFG_DEV_SSPI_XFER_ACKTIMEOUT(0xf000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3478) xudc_writel(xudc, val, CFG_DEV_SSPI_XFER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3481) static int tegra_xudc_phy_get(struct tegra_xudc *xudc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3482) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3483) int err = 0, usb3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3484) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3486) xudc->utmi_phy = devm_kcalloc(xudc->dev, xudc->soc->num_phys,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3487) sizeof(*xudc->utmi_phy), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3488) if (!xudc->utmi_phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3489) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3491) xudc->usb3_phy = devm_kcalloc(xudc->dev, xudc->soc->num_phys,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3492) sizeof(*xudc->usb3_phy), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3493) if (!xudc->usb3_phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3494) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3496) xudc->usbphy = devm_kcalloc(xudc->dev, xudc->soc->num_phys,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3497) sizeof(*xudc->usbphy), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3498) if (!xudc->usbphy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3499) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3501) xudc->vbus_nb.notifier_call = tegra_xudc_vbus_notify;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3503) for (i = 0; i < xudc->soc->num_phys; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3504) char phy_name[] = "usb.-.";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3506) /* Get USB2 phy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3507) snprintf(phy_name, sizeof(phy_name), "usb2-%d", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3508) xudc->utmi_phy[i] = devm_phy_optional_get(xudc->dev, phy_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3509) if (IS_ERR(xudc->utmi_phy[i])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3510) err = PTR_ERR(xudc->utmi_phy[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3511) if (err != -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3512) dev_err(xudc->dev, "failed to get usb2-%d PHY: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3513) i, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3515) goto clean_up;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3516) } else if (xudc->utmi_phy[i]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3517) /* Get usb-phy, if utmi phy is available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3518) xudc->usbphy[i] = devm_usb_get_phy_by_node(xudc->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3519) xudc->utmi_phy[i]->dev.of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3520) &xudc->vbus_nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3521) if (IS_ERR(xudc->usbphy[i])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3522) err = PTR_ERR(xudc->usbphy[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3523) dev_err(xudc->dev, "failed to get usbphy-%d: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3524) i, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3525) goto clean_up;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3526) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3527) } else if (!xudc->utmi_phy[i]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3528) /* if utmi phy is not available, ignore USB3 phy get */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3529) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3530) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3532) /* Get USB3 phy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3533) usb3 = tegra_xusb_padctl_get_usb3_companion(xudc->padctl, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3534) if (usb3 < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3535) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3537) snprintf(phy_name, sizeof(phy_name), "usb3-%d", usb3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3538) xudc->usb3_phy[i] = devm_phy_optional_get(xudc->dev, phy_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3539) if (IS_ERR(xudc->usb3_phy[i])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3540) err = PTR_ERR(xudc->usb3_phy[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3541) if (err != -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3542) dev_err(xudc->dev, "failed to get usb3-%d PHY: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3543) usb3, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3545) goto clean_up;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3546) } else if (xudc->usb3_phy[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3547) dev_dbg(xudc->dev, "usb3-%d PHY registered", usb3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3548) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3550) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3552) clean_up:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3553) for (i = 0; i < xudc->soc->num_phys; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3554) xudc->usb3_phy[i] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3555) xudc->utmi_phy[i] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3556) xudc->usbphy[i] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3557) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3559) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3560) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3562) static void tegra_xudc_phy_exit(struct tegra_xudc *xudc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3563) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3564) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3566) for (i = 0; i < xudc->soc->num_phys; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3567) phy_exit(xudc->usb3_phy[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3568) phy_exit(xudc->utmi_phy[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3569) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3570) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3572) static int tegra_xudc_phy_init(struct tegra_xudc *xudc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3573) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3574) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3575) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3577) for (i = 0; i < xudc->soc->num_phys; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3578) err = phy_init(xudc->utmi_phy[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3579) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3580) dev_err(xudc->dev, "UTMI PHY #%u initialization failed: %d\n", i, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3581) goto exit_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3582) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3584) err = phy_init(xudc->usb3_phy[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3585) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3586) dev_err(xudc->dev, "USB3 PHY #%u initialization failed: %d\n", i, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3587) goto exit_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3588) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3589) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3590) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3592) exit_phy:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3593) tegra_xudc_phy_exit(xudc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3594) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3595) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3597) static const char * const tegra210_xudc_supply_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3598) "hvdd-usb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3599) "avddio-usb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3600) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3602) static const char * const tegra210_xudc_clock_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3603) "dev",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3604) "ss",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3605) "ss_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3606) "hs_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3607) "fs_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3608) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3610) static const char * const tegra186_xudc_clock_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3611) "dev",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3612) "ss",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3613) "ss_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3614) "fs_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3615) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3617) static struct tegra_xudc_soc tegra210_xudc_soc_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3618) .supply_names = tegra210_xudc_supply_names,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3619) .num_supplies = ARRAY_SIZE(tegra210_xudc_supply_names),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3620) .clock_names = tegra210_xudc_clock_names,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3621) .num_clks = ARRAY_SIZE(tegra210_xudc_clock_names),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3622) .num_phys = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3623) .u1_enable = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3624) .u2_enable = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3625) .lpm_enable = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3626) .invalid_seq_num = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3627) .pls_quirk = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3628) .port_reset_quirk = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3629) .port_speed_quirk = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3630) .has_ipfs = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3631) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3633) static struct tegra_xudc_soc tegra186_xudc_soc_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3634) .clock_names = tegra186_xudc_clock_names,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3635) .num_clks = ARRAY_SIZE(tegra186_xudc_clock_names),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3636) .num_phys = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3637) .u1_enable = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3638) .u2_enable = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3639) .lpm_enable = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3640) .invalid_seq_num = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3641) .pls_quirk = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3642) .port_reset_quirk = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3643) .port_speed_quirk = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3644) .has_ipfs = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3645) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3647) static struct tegra_xudc_soc tegra194_xudc_soc_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3648) .clock_names = tegra186_xudc_clock_names,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3649) .num_clks = ARRAY_SIZE(tegra186_xudc_clock_names),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3650) .num_phys = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3651) .u1_enable = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3652) .u2_enable = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3653) .lpm_enable = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3654) .invalid_seq_num = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3655) .pls_quirk = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3656) .port_reset_quirk = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3657) .port_speed_quirk = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3658) .has_ipfs = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3659) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3661) static const struct of_device_id tegra_xudc_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3662) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3663) .compatible = "nvidia,tegra210-xudc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3664) .data = &tegra210_xudc_soc_data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3665) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3666) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3667) .compatible = "nvidia,tegra186-xudc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3668) .data = &tegra186_xudc_soc_data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3669) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3670) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3671) .compatible = "nvidia,tegra194-xudc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3672) .data = &tegra194_xudc_soc_data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3673) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3674) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3675) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3676) MODULE_DEVICE_TABLE(of, tegra_xudc_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3678) static void tegra_xudc_powerdomain_remove(struct tegra_xudc *xudc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3679) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3680) if (xudc->genpd_dl_ss)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3681) device_link_del(xudc->genpd_dl_ss);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3682) if (xudc->genpd_dl_device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3683) device_link_del(xudc->genpd_dl_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3684) if (xudc->genpd_dev_ss)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3685) dev_pm_domain_detach(xudc->genpd_dev_ss, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3686) if (xudc->genpd_dev_device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3687) dev_pm_domain_detach(xudc->genpd_dev_device, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3688) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3690) static int tegra_xudc_powerdomain_init(struct tegra_xudc *xudc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3691) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3692) struct device *dev = xudc->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3693) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3695) xudc->genpd_dev_device = dev_pm_domain_attach_by_name(dev, "dev");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3696) if (IS_ERR(xudc->genpd_dev_device)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3697) err = PTR_ERR(xudc->genpd_dev_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3698) dev_err(dev, "failed to get device power domain: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3699) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3700) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3702) xudc->genpd_dev_ss = dev_pm_domain_attach_by_name(dev, "ss");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3703) if (IS_ERR(xudc->genpd_dev_ss)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3704) err = PTR_ERR(xudc->genpd_dev_ss);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3705) dev_err(dev, "failed to get SuperSpeed power domain: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3706) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3707) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3709) xudc->genpd_dl_device = device_link_add(dev, xudc->genpd_dev_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3710) DL_FLAG_PM_RUNTIME |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3711) DL_FLAG_STATELESS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3712) if (!xudc->genpd_dl_device) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3713) dev_err(dev, "failed to add USB device link\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3714) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3715) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3717) xudc->genpd_dl_ss = device_link_add(dev, xudc->genpd_dev_ss,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3718) DL_FLAG_PM_RUNTIME |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3719) DL_FLAG_STATELESS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3720) if (!xudc->genpd_dl_ss) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3721) dev_err(dev, "failed to add SuperSpeed device link\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3722) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3723) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3725) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3726) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3728) static int tegra_xudc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3729) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3730) struct tegra_xudc *xudc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3731) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3732) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3733) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3735) xudc = devm_kzalloc(&pdev->dev, sizeof(*xudc), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3736) if (!xudc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3737) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3739) xudc->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3740) platform_set_drvdata(pdev, xudc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3742) xudc->soc = of_device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3743) if (!xudc->soc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3744) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3746) res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "base");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3747) xudc->base = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3748) if (IS_ERR(xudc->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3749) return PTR_ERR(xudc->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3750) xudc->phys_base = res->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3752) xudc->fpci = devm_platform_ioremap_resource_byname(pdev, "fpci");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3753) if (IS_ERR(xudc->fpci))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3754) return PTR_ERR(xudc->fpci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3756) if (xudc->soc->has_ipfs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3757) xudc->ipfs = devm_platform_ioremap_resource_byname(pdev, "ipfs");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3758) if (IS_ERR(xudc->ipfs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3759) return PTR_ERR(xudc->ipfs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3760) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3762) xudc->irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3763) if (xudc->irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3764) return xudc->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3766) err = devm_request_irq(&pdev->dev, xudc->irq, tegra_xudc_irq, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3767) dev_name(&pdev->dev), xudc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3768) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3769) dev_err(xudc->dev, "failed to claim IRQ#%u: %d\n", xudc->irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3770) err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3771) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3772) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3774) xudc->clks = devm_kcalloc(&pdev->dev, xudc->soc->num_clks, sizeof(*xudc->clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3775) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3776) if (!xudc->clks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3777) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3779) for (i = 0; i < xudc->soc->num_clks; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3780) xudc->clks[i].id = xudc->soc->clock_names[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3782) err = devm_clk_bulk_get(&pdev->dev, xudc->soc->num_clks, xudc->clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3783) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3784) if (err != -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3785) dev_err(xudc->dev, "failed to request clocks: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3787) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3788) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3790) xudc->supplies = devm_kcalloc(&pdev->dev, xudc->soc->num_supplies,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3791) sizeof(*xudc->supplies), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3792) if (!xudc->supplies)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3793) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3795) for (i = 0; i < xudc->soc->num_supplies; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3796) xudc->supplies[i].supply = xudc->soc->supply_names[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3798) err = devm_regulator_bulk_get(&pdev->dev, xudc->soc->num_supplies,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3799) xudc->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3800) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3801) if (err != -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3802) dev_err(xudc->dev, "failed to request regulators: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3804) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3805) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3807) xudc->padctl = tegra_xusb_padctl_get(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3808) if (IS_ERR(xudc->padctl))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3809) return PTR_ERR(xudc->padctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3811) err = regulator_bulk_enable(xudc->soc->num_supplies, xudc->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3812) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3813) dev_err(xudc->dev, "failed to enable regulators: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3814) goto put_padctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3815) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3817) err = tegra_xudc_phy_get(xudc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3818) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3819) goto disable_regulator;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3821) err = tegra_xudc_powerdomain_init(xudc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3822) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3823) goto put_powerdomains;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3825) err = tegra_xudc_phy_init(xudc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3826) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3827) goto put_powerdomains;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3829) err = tegra_xudc_alloc_event_ring(xudc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3830) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3831) goto disable_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3833) err = tegra_xudc_alloc_eps(xudc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3834) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3835) goto free_event_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3837) spin_lock_init(&xudc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3839) init_completion(&xudc->disconnect_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3841) INIT_WORK(&xudc->usb_role_sw_work, tegra_xudc_usb_role_sw_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3843) INIT_DELAYED_WORK(&xudc->plc_reset_work, tegra_xudc_plc_reset_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3845) INIT_DELAYED_WORK(&xudc->port_reset_war_work,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3846) tegra_xudc_port_reset_war_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3848) pm_runtime_enable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3850) xudc->gadget.ops = &tegra_xudc_gadget_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3851) xudc->gadget.ep0 = &xudc->ep[0].usb_ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3852) xudc->gadget.name = "tegra-xudc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3853) xudc->gadget.max_speed = USB_SPEED_SUPER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3855) err = usb_add_gadget_udc(&pdev->dev, &xudc->gadget);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3856) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3857) dev_err(&pdev->dev, "failed to add USB gadget: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3858) goto free_eps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3859) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3861) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3863) free_eps:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3864) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3865) tegra_xudc_free_eps(xudc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3866) free_event_ring:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3867) tegra_xudc_free_event_ring(xudc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3868) disable_phy:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3869) tegra_xudc_phy_exit(xudc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3870) put_powerdomains:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3871) tegra_xudc_powerdomain_remove(xudc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3872) disable_regulator:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3873) regulator_bulk_disable(xudc->soc->num_supplies, xudc->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3874) put_padctl:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3875) tegra_xusb_padctl_put(xudc->padctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3877) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3878) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3880) static int tegra_xudc_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3881) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3882) struct tegra_xudc *xudc = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3883) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3885) pm_runtime_get_sync(xudc->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3887) cancel_delayed_work_sync(&xudc->plc_reset_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3888) cancel_work_sync(&xudc->usb_role_sw_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3890) usb_del_gadget_udc(&xudc->gadget);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3892) tegra_xudc_free_eps(xudc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3893) tegra_xudc_free_event_ring(xudc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3895) tegra_xudc_powerdomain_remove(xudc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3897) regulator_bulk_disable(xudc->soc->num_supplies, xudc->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3899) for (i = 0; i < xudc->soc->num_phys; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3900) phy_power_off(xudc->utmi_phy[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3901) phy_power_off(xudc->usb3_phy[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3902) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3904) tegra_xudc_phy_exit(xudc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3906) pm_runtime_disable(xudc->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3907) pm_runtime_put(xudc->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3909) tegra_xusb_padctl_put(xudc->padctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3911) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3912) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3914) static int __maybe_unused tegra_xudc_powergate(struct tegra_xudc *xudc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3915) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3916) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3918) dev_dbg(xudc->dev, "entering ELPG\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3920) spin_lock_irqsave(&xudc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3922) xudc->powergated = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3923) xudc->saved_regs.ctrl = xudc_readl(xudc, CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3924) xudc->saved_regs.portpm = xudc_readl(xudc, PORTPM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3925) xudc_writel(xudc, 0, CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3927) spin_unlock_irqrestore(&xudc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3929) clk_bulk_disable_unprepare(xudc->soc->num_clks, xudc->clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3931) regulator_bulk_disable(xudc->soc->num_supplies, xudc->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3933) dev_dbg(xudc->dev, "entering ELPG done\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3934) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3935) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3937) static int __maybe_unused tegra_xudc_unpowergate(struct tegra_xudc *xudc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3938) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3939) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3940) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3942) dev_dbg(xudc->dev, "exiting ELPG\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3944) err = regulator_bulk_enable(xudc->soc->num_supplies,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3945) xudc->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3946) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3947) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3949) err = clk_bulk_prepare_enable(xudc->soc->num_clks, xudc->clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3950) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3951) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3953) tegra_xudc_fpci_ipfs_init(xudc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3955) tegra_xudc_device_params_init(xudc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3957) tegra_xudc_init_event_ring(xudc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3959) tegra_xudc_init_eps(xudc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3961) xudc_writel(xudc, xudc->saved_regs.portpm, PORTPM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3962) xudc_writel(xudc, xudc->saved_regs.ctrl, CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3964) spin_lock_irqsave(&xudc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3965) xudc->powergated = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3966) spin_unlock_irqrestore(&xudc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3968) dev_dbg(xudc->dev, "exiting ELPG done\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3969) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3970) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3972) static int __maybe_unused tegra_xudc_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3973) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3974) struct tegra_xudc *xudc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3975) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3977) spin_lock_irqsave(&xudc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3978) xudc->suspended = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3979) spin_unlock_irqrestore(&xudc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3981) flush_work(&xudc->usb_role_sw_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3983) if (!pm_runtime_status_suspended(dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3984) /* Forcibly disconnect before powergating. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3985) tegra_xudc_device_mode_off(xudc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3986) tegra_xudc_powergate(xudc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3987) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3989) pm_runtime_disable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3991) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3992) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3994) static int __maybe_unused tegra_xudc_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3995) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3996) struct tegra_xudc *xudc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3997) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3998) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4000) err = tegra_xudc_unpowergate(xudc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4001) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4002) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4004) spin_lock_irqsave(&xudc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4005) xudc->suspended = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4006) spin_unlock_irqrestore(&xudc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4008) schedule_work(&xudc->usb_role_sw_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4010) pm_runtime_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4012) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4013) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4015) static int __maybe_unused tegra_xudc_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4016) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4017) struct tegra_xudc *xudc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4019) return tegra_xudc_powergate(xudc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4020) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4022) static int __maybe_unused tegra_xudc_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4023) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4024) struct tegra_xudc *xudc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4026) return tegra_xudc_unpowergate(xudc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4027) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4029) static const struct dev_pm_ops tegra_xudc_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4030) SET_SYSTEM_SLEEP_PM_OPS(tegra_xudc_suspend, tegra_xudc_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4031) SET_RUNTIME_PM_OPS(tegra_xudc_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4032) tegra_xudc_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4033) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4035) static struct platform_driver tegra_xudc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4036) .probe = tegra_xudc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4037) .remove = tegra_xudc_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4038) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4039) .name = "tegra-xudc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4040) .pm = &tegra_xudc_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4041) .of_match_table = tegra_xudc_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4042) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4043) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4044) module_platform_driver(tegra_xudc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4046) MODULE_DESCRIPTION("NVIDIA Tegra XUSB Device Controller");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4047) MODULE_AUTHOR("Andrew Bresticker <abrestic@chromium.org>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4048) MODULE_AUTHOR("Hui Fu <hfu@nvidia.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4049) MODULE_AUTHOR("Nagarjuna Kristam <nkristam@nvidia.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4050) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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