^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /* linux/drivers/usb/gadget/s3c-hsudc.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (c) 2010 Samsung Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * http://www.samsung.com/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * S3C24XX USB 2.0 High-speed USB controller gadget driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * The S3C24XX USB 2.0 high-speed USB controller supports upto 9 endpoints.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Each endpoint can be configured as either in or out endpoint. Endpoints
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * can be configured for Bulk or Interrupt transfer mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/usb/ch9.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/usb/gadget.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/usb/otg.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/prefetch.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/platform_data/s3c-hsudc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define S3C_HSUDC_REG(x) (x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /* Non-Indexed Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define S3C_IR S3C_HSUDC_REG(0x00) /* Index Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define S3C_EIR S3C_HSUDC_REG(0x04) /* EP Intr Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define S3C_EIR_EP0 (1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define S3C_EIER S3C_HSUDC_REG(0x08) /* EP Intr Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define S3C_FAR S3C_HSUDC_REG(0x0c) /* Gadget Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define S3C_FNR S3C_HSUDC_REG(0x10) /* Frame Number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define S3C_EDR S3C_HSUDC_REG(0x14) /* EP Direction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define S3C_TR S3C_HSUDC_REG(0x18) /* Test Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define S3C_SSR S3C_HSUDC_REG(0x1c) /* System Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define S3C_SSR_DTZIEN_EN (0xff8f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define S3C_SSR_ERR (0xff80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define S3C_SSR_VBUSON (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define S3C_SSR_HSP (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define S3C_SSR_SDE (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define S3C_SSR_RESUME (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define S3C_SSR_SUSPEND (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define S3C_SSR_RESET (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define S3C_SCR S3C_HSUDC_REG(0x20) /* System Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define S3C_SCR_DTZIEN_EN (1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define S3C_SCR_RRD_EN (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define S3C_SCR_SUS_EN (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define S3C_SCR_RST_EN (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define S3C_EP0SR S3C_HSUDC_REG(0x24) /* EP0 Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define S3C_EP0SR_EP0_LWO (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define S3C_EP0SR_STALL (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define S3C_EP0SR_TX_SUCCESS (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define S3C_EP0SR_RX_SUCCESS (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define S3C_EP0CR S3C_HSUDC_REG(0x28) /* EP0 Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define S3C_BR(_x) S3C_HSUDC_REG(0x60 + (_x * 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /* Indexed Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define S3C_ESR S3C_HSUDC_REG(0x2c) /* EPn Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define S3C_ESR_FLUSH (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define S3C_ESR_STALL (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define S3C_ESR_LWO (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define S3C_ESR_PSIF_ONE (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define S3C_ESR_PSIF_TWO (2 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define S3C_ESR_TX_SUCCESS (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define S3C_ESR_RX_SUCCESS (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define S3C_ECR S3C_HSUDC_REG(0x30) /* EPn Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define S3C_ECR_DUEN (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define S3C_ECR_FLUSH (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define S3C_ECR_STALL (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define S3C_ECR_IEMS (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define S3C_BRCR S3C_HSUDC_REG(0x34) /* Read Count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define S3C_BWCR S3C_HSUDC_REG(0x38) /* Write Count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define S3C_MPR S3C_HSUDC_REG(0x3c) /* Max Pkt Size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define WAIT_FOR_SETUP (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define DATA_STATE_XMIT (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define DATA_STATE_RECV (2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) static const char * const s3c_hsudc_supply_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) "vdda", /* analog phy supply, 3.3V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) "vddi", /* digital phy supply, 1.2V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) "vddosc", /* oscillator supply, 1.8V - 3.3V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * struct s3c_hsudc_ep - Endpoint representation used by driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * @ep: USB gadget layer representation of device endpoint.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * @name: Endpoint name (as required by ep autoconfiguration).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * @dev: Reference to the device controller to which this EP belongs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * @desc: Endpoint descriptor obtained from the gadget driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * @queue: Transfer request queue for the endpoint.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * @stopped: Maintains state of endpoint, set if EP is halted.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * @bEndpointAddress: EP address (including direction bit).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * @fifo: Base address of EP FIFO.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) struct s3c_hsudc_ep {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) struct usb_ep ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) char name[20];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) struct s3c_hsudc *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) struct list_head queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) u8 stopped;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) u8 wedge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) u8 bEndpointAddress;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) void __iomem *fifo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * struct s3c_hsudc_req - Driver encapsulation of USB gadget transfer request.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * @req: Reference to USB gadget transfer request.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) * @queue: Used for inserting this request to the endpoint request queue.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) struct s3c_hsudc_req {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) struct usb_request req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) struct list_head queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * struct s3c_hsudc - Driver's abstraction of the device controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * @gadget: Instance of usb_gadget which is referenced by gadget driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * @driver: Reference to currenty active gadget driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * @dev: The device reference used by probe function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * @lock: Lock to synchronize the usage of Endpoints (EP's are indexed).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * @regs: Remapped base address of controller's register space.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * irq: IRQ number used by the controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * uclk: Reference to the controller clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) * ep0state: Current state of EP0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * ep: List of endpoints supported by the controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) struct s3c_hsudc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) struct usb_gadget gadget;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) struct usb_gadget_driver *driver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) struct s3c24xx_hsudc_platdata *pd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) struct usb_phy *transceiver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct regulator_bulk_data supplies[ARRAY_SIZE(s3c_hsudc_supply_names)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) struct clk *uclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) int ep0state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) struct s3c_hsudc_ep ep[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define ep_maxpacket(_ep) ((_ep)->ep.maxpacket)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define ep_is_in(_ep) ((_ep)->bEndpointAddress & USB_DIR_IN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define ep_index(_ep) ((_ep)->bEndpointAddress & \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) USB_ENDPOINT_NUMBER_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static const char driver_name[] = "s3c-udc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static const char ep0name[] = "ep0-control";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static inline struct s3c_hsudc_req *our_req(struct usb_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) return container_of(req, struct s3c_hsudc_req, req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static inline struct s3c_hsudc_ep *our_ep(struct usb_ep *ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) return container_of(ep, struct s3c_hsudc_ep, ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) static inline struct s3c_hsudc *to_hsudc(struct usb_gadget *gadget)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) return container_of(gadget, struct s3c_hsudc, gadget);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static inline void set_index(struct s3c_hsudc *hsudc, int ep_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) ep_addr &= USB_ENDPOINT_NUMBER_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) writel(ep_addr, hsudc->regs + S3C_IR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) static inline void __orr32(void __iomem *ptr, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) writel(readl(ptr) | val, ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) * s3c_hsudc_complete_request - Complete a transfer request.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) * @hsep: Endpoint to which the request belongs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) * @hsreq: Transfer request to be completed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) * @status: Transfer completion status for the transfer request.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) static void s3c_hsudc_complete_request(struct s3c_hsudc_ep *hsep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) struct s3c_hsudc_req *hsreq, int status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) unsigned int stopped = hsep->stopped;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) struct s3c_hsudc *hsudc = hsep->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) list_del_init(&hsreq->queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) hsreq->req.status = status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) if (!ep_index(hsep)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) hsudc->ep0state = WAIT_FOR_SETUP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) hsep->bEndpointAddress &= ~USB_DIR_IN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) hsep->stopped = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) spin_unlock(&hsudc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) usb_gadget_giveback_request(&hsep->ep, &hsreq->req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) spin_lock(&hsudc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) hsep->stopped = stopped;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) * s3c_hsudc_nuke_ep - Terminate all requests queued for a endpoint.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) * @hsep: Endpoint for which queued requests have to be terminated.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) * @status: Transfer completion status for the transfer request.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) static void s3c_hsudc_nuke_ep(struct s3c_hsudc_ep *hsep, int status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) struct s3c_hsudc_req *hsreq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) while (!list_empty(&hsep->queue)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) hsreq = list_entry(hsep->queue.next,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) struct s3c_hsudc_req, queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) s3c_hsudc_complete_request(hsep, hsreq, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) * s3c_hsudc_stop_activity - Stop activity on all endpoints.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) * @hsudc: Device controller for which EP activity is to be stopped.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) * All the endpoints are stopped and any pending transfer requests if any on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) * the endpoint are terminated.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) static void s3c_hsudc_stop_activity(struct s3c_hsudc *hsudc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) struct s3c_hsudc_ep *hsep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) int epnum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) hsudc->gadget.speed = USB_SPEED_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) for (epnum = 0; epnum < hsudc->pd->epnum; epnum++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) hsep = &hsudc->ep[epnum];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) hsep->stopped = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) s3c_hsudc_nuke_ep(hsep, -ESHUTDOWN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) * s3c_hsudc_read_setup_pkt - Read the received setup packet from EP0 fifo.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) * @hsudc: Device controller from which setup packet is to be read.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) * @buf: The buffer into which the setup packet is read.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) * The setup packet received in the EP0 fifo is read and stored into a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) * given buffer address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) static void s3c_hsudc_read_setup_pkt(struct s3c_hsudc *hsudc, u16 *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) int count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) count = readl(hsudc->regs + S3C_BRCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) while (count--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) *buf++ = (u16)readl(hsudc->regs + S3C_BR(0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) writel(S3C_EP0SR_RX_SUCCESS, hsudc->regs + S3C_EP0SR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) * s3c_hsudc_write_fifo - Write next chunk of transfer data to EP fifo.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) * @hsep: Endpoint to which the data is to be written.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) * @hsreq: Transfer request from which the next chunk of data is written.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) * Write the next chunk of data from a transfer request to the endpoint FIFO.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) * If the transfer request completes, 1 is returned, otherwise 0 is returned.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) static int s3c_hsudc_write_fifo(struct s3c_hsudc_ep *hsep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) struct s3c_hsudc_req *hsreq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) u16 *buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) u32 max = ep_maxpacket(hsep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) u32 count, length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) bool is_last;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) void __iomem *fifo = hsep->fifo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) buf = hsreq->req.buf + hsreq->req.actual;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) prefetch(buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) length = hsreq->req.length - hsreq->req.actual;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) length = min(length, max);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) hsreq->req.actual += length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) writel(length, hsep->dev->regs + S3C_BWCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) for (count = 0; count < length; count += 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) writel(*buf++, fifo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) if (count != max) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) is_last = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) if (hsreq->req.length != hsreq->req.actual || hsreq->req.zero)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) is_last = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) is_last = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) if (is_last) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) s3c_hsudc_complete_request(hsep, hsreq, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) * s3c_hsudc_read_fifo - Read the next chunk of data from EP fifo.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) * @hsep: Endpoint from which the data is to be read.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) * @hsreq: Transfer request to which the next chunk of data read is written.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) * Read the next chunk of data from the endpoint FIFO and a write it to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) * transfer request buffer. If the transfer request completes, 1 is returned,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) * otherwise 0 is returned.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) static int s3c_hsudc_read_fifo(struct s3c_hsudc_ep *hsep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) struct s3c_hsudc_req *hsreq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) struct s3c_hsudc *hsudc = hsep->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) u32 csr, offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) u16 *buf, word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) u32 buflen, rcnt, rlen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) void __iomem *fifo = hsep->fifo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) u32 is_short = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) offset = (ep_index(hsep)) ? S3C_ESR : S3C_EP0SR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) csr = readl(hsudc->regs + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) if (!(csr & S3C_ESR_RX_SUCCESS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) buf = hsreq->req.buf + hsreq->req.actual;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) prefetchw(buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) buflen = hsreq->req.length - hsreq->req.actual;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) rcnt = readl(hsudc->regs + S3C_BRCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) rlen = (csr & S3C_ESR_LWO) ? (rcnt * 2 - 1) : (rcnt * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) hsreq->req.actual += min(rlen, buflen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) is_short = (rlen < hsep->ep.maxpacket);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) while (rcnt-- != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) word = (u16)readl(fifo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) if (buflen) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) *buf++ = word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) buflen--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) hsreq->req.status = -EOVERFLOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) writel(S3C_ESR_RX_SUCCESS, hsudc->regs + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) if (is_short || hsreq->req.actual == hsreq->req.length) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) s3c_hsudc_complete_request(hsep, hsreq, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) * s3c_hsudc_epin_intr - Handle in-endpoint interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) * @hsudc - Device controller for which the interrupt is to be handled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) * @ep_idx - Endpoint number on which an interrupt is pending.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) * Handles interrupt for a in-endpoint. The interrupts that are handled are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) * stall and data transmit complete interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) static void s3c_hsudc_epin_intr(struct s3c_hsudc *hsudc, u32 ep_idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) struct s3c_hsudc_ep *hsep = &hsudc->ep[ep_idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) struct s3c_hsudc_req *hsreq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) u32 csr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) csr = readl(hsudc->regs + S3C_ESR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) if (csr & S3C_ESR_STALL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) writel(S3C_ESR_STALL, hsudc->regs + S3C_ESR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) if (csr & S3C_ESR_TX_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) writel(S3C_ESR_TX_SUCCESS, hsudc->regs + S3C_ESR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) if (list_empty(&hsep->queue))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) hsreq = list_entry(hsep->queue.next,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) struct s3c_hsudc_req, queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) if ((s3c_hsudc_write_fifo(hsep, hsreq) == 0) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) (csr & S3C_ESR_PSIF_TWO))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) s3c_hsudc_write_fifo(hsep, hsreq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) * s3c_hsudc_epout_intr - Handle out-endpoint interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) * @hsudc - Device controller for which the interrupt is to be handled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) * @ep_idx - Endpoint number on which an interrupt is pending.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) * Handles interrupt for a out-endpoint. The interrupts that are handled are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) * stall, flush and data ready interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) static void s3c_hsudc_epout_intr(struct s3c_hsudc *hsudc, u32 ep_idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) struct s3c_hsudc_ep *hsep = &hsudc->ep[ep_idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) struct s3c_hsudc_req *hsreq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) u32 csr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) csr = readl(hsudc->regs + S3C_ESR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) if (csr & S3C_ESR_STALL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) writel(S3C_ESR_STALL, hsudc->regs + S3C_ESR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) if (csr & S3C_ESR_FLUSH) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) __orr32(hsudc->regs + S3C_ECR, S3C_ECR_FLUSH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) if (csr & S3C_ESR_RX_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) if (list_empty(&hsep->queue))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) hsreq = list_entry(hsep->queue.next,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) struct s3c_hsudc_req, queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) if (((s3c_hsudc_read_fifo(hsep, hsreq)) == 0) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) (csr & S3C_ESR_PSIF_TWO))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) s3c_hsudc_read_fifo(hsep, hsreq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) /** s3c_hsudc_set_halt - Set or clear a endpoint halt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) * @_ep: Endpoint on which halt has to be set or cleared.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) * @value: 1 for setting halt on endpoint, 0 to clear halt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) * Set or clear endpoint halt. If halt is set, the endpoint is stopped.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) * If halt is cleared, for in-endpoints, if there are any pending
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) * transfer requests, transfers are started.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) static int s3c_hsudc_set_halt(struct usb_ep *_ep, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) struct s3c_hsudc_ep *hsep = our_ep(_ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) struct s3c_hsudc *hsudc = hsep->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) struct s3c_hsudc_req *hsreq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) unsigned long irqflags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) u32 ecr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) u32 offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) if (value && ep_is_in(hsep) && !list_empty(&hsep->queue))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) spin_lock_irqsave(&hsudc->lock, irqflags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) set_index(hsudc, ep_index(hsep));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) offset = (ep_index(hsep)) ? S3C_ECR : S3C_EP0CR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) ecr = readl(hsudc->regs + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) if (value) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) ecr |= S3C_ECR_STALL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) if (ep_index(hsep))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) ecr |= S3C_ECR_FLUSH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) hsep->stopped = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) ecr &= ~S3C_ECR_STALL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) hsep->stopped = hsep->wedge = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) writel(ecr, hsudc->regs + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) if (ep_is_in(hsep) && !list_empty(&hsep->queue) && !value) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) hsreq = list_entry(hsep->queue.next,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) struct s3c_hsudc_req, queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) if (hsreq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) s3c_hsudc_write_fifo(hsep, hsreq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) spin_unlock_irqrestore(&hsudc->lock, irqflags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) /** s3c_hsudc_set_wedge - Sets the halt feature with the clear requests ignored
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) * @_ep: Endpoint on which wedge has to be set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) * Sets the halt feature with the clear requests ignored.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) static int s3c_hsudc_set_wedge(struct usb_ep *_ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) struct s3c_hsudc_ep *hsep = our_ep(_ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) if (!hsep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) hsep->wedge = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) return usb_ep_set_halt(_ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) /** s3c_hsudc_handle_reqfeat - Handle set feature or clear feature requests.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) * @_ep: Device controller on which the set/clear feature needs to be handled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) * @ctrl: Control request as received on the endpoint 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) * Handle set feature or clear feature control requests on the control endpoint.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) static int s3c_hsudc_handle_reqfeat(struct s3c_hsudc *hsudc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) struct usb_ctrlrequest *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) struct s3c_hsudc_ep *hsep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) bool set = (ctrl->bRequest == USB_REQ_SET_FEATURE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) u8 ep_num = ctrl->wIndex & USB_ENDPOINT_NUMBER_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) if (ctrl->bRequestType == USB_RECIP_ENDPOINT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) hsep = &hsudc->ep[ep_num];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) switch (le16_to_cpu(ctrl->wValue)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) case USB_ENDPOINT_HALT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) if (set || !hsep->wedge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) s3c_hsudc_set_halt(&hsep->ep, set);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) * s3c_hsudc_process_req_status - Handle get status control request.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) * @hsudc: Device controller on which get status request has be handled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) * @ctrl: Control request as received on the endpoint 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) * Handle get status control request received on control endpoint.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) static void s3c_hsudc_process_req_status(struct s3c_hsudc *hsudc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) struct usb_ctrlrequest *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) struct s3c_hsudc_ep *hsep0 = &hsudc->ep[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) struct s3c_hsudc_req hsreq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) struct s3c_hsudc_ep *hsep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) __le16 reply;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) u8 epnum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) switch (ctrl->bRequestType & USB_RECIP_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) case USB_RECIP_DEVICE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) reply = cpu_to_le16(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) case USB_RECIP_INTERFACE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) reply = cpu_to_le16(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) case USB_RECIP_ENDPOINT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) epnum = le16_to_cpu(ctrl->wIndex) & USB_ENDPOINT_NUMBER_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) hsep = &hsudc->ep[epnum];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) reply = cpu_to_le16(hsep->stopped ? 1 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) INIT_LIST_HEAD(&hsreq.queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) hsreq.req.length = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) hsreq.req.buf = &reply;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) hsreq.req.actual = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) hsreq.req.complete = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) s3c_hsudc_write_fifo(hsep0, &hsreq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) * s3c_hsudc_process_setup - Process control request received on endpoint 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) * @hsudc: Device controller on which control request has been received.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) * Read the control request received on endpoint 0, decode it and handle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) * the request.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) static void s3c_hsudc_process_setup(struct s3c_hsudc *hsudc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) struct s3c_hsudc_ep *hsep = &hsudc->ep[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) struct usb_ctrlrequest ctrl = {0};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) s3c_hsudc_nuke_ep(hsep, -EPROTO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) s3c_hsudc_read_setup_pkt(hsudc, (u16 *)&ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) if (ctrl.bRequestType & USB_DIR_IN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) hsep->bEndpointAddress |= USB_DIR_IN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) hsudc->ep0state = DATA_STATE_XMIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) hsep->bEndpointAddress &= ~USB_DIR_IN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) hsudc->ep0state = DATA_STATE_RECV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) switch (ctrl.bRequest) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) case USB_REQ_SET_ADDRESS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) if (ctrl.bRequestType != (USB_TYPE_STANDARD | USB_RECIP_DEVICE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) hsudc->ep0state = WAIT_FOR_SETUP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) case USB_REQ_GET_STATUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) if ((ctrl.bRequestType & USB_TYPE_MASK) != USB_TYPE_STANDARD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) s3c_hsudc_process_req_status(hsudc, &ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) case USB_REQ_SET_FEATURE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) case USB_REQ_CLEAR_FEATURE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) if ((ctrl.bRequestType & USB_TYPE_MASK) != USB_TYPE_STANDARD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) s3c_hsudc_handle_reqfeat(hsudc, &ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) hsudc->ep0state = WAIT_FOR_SETUP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) if (hsudc->driver) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) spin_unlock(&hsudc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) ret = hsudc->driver->setup(&hsudc->gadget, &ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) spin_lock(&hsudc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) if (ctrl.bRequest == USB_REQ_SET_CONFIGURATION) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) hsep->bEndpointAddress &= ~USB_DIR_IN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) hsudc->ep0state = WAIT_FOR_SETUP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) dev_err(hsudc->dev, "setup failed, returned %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) s3c_hsudc_set_halt(&hsep->ep, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) hsudc->ep0state = WAIT_FOR_SETUP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) hsep->bEndpointAddress &= ~USB_DIR_IN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) /** s3c_hsudc_handle_ep0_intr - Handle endpoint 0 interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) * @hsudc: Device controller on which endpoint 0 interrupt has occured.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) * Handle endpoint 0 interrupt when it occurs. EP0 interrupt could occur
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) * when a stall handshake is sent to host or data is sent/received on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) * endpoint 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) static void s3c_hsudc_handle_ep0_intr(struct s3c_hsudc *hsudc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) struct s3c_hsudc_ep *hsep = &hsudc->ep[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) struct s3c_hsudc_req *hsreq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) u32 csr = readl(hsudc->regs + S3C_EP0SR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) u32 ecr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) if (csr & S3C_EP0SR_STALL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) ecr = readl(hsudc->regs + S3C_EP0CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) ecr &= ~(S3C_ECR_STALL | S3C_ECR_FLUSH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) writel(ecr, hsudc->regs + S3C_EP0CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) writel(S3C_EP0SR_STALL, hsudc->regs + S3C_EP0SR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) hsep->stopped = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) s3c_hsudc_nuke_ep(hsep, -ECONNABORTED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) hsudc->ep0state = WAIT_FOR_SETUP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) hsep->bEndpointAddress &= ~USB_DIR_IN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) if (csr & S3C_EP0SR_TX_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) writel(S3C_EP0SR_TX_SUCCESS, hsudc->regs + S3C_EP0SR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) if (ep_is_in(hsep)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) if (list_empty(&hsep->queue))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) hsreq = list_entry(hsep->queue.next,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) struct s3c_hsudc_req, queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) s3c_hsudc_write_fifo(hsep, hsreq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) if (csr & S3C_EP0SR_RX_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) if (hsudc->ep0state == WAIT_FOR_SETUP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) s3c_hsudc_process_setup(hsudc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) if (!ep_is_in(hsep)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) if (list_empty(&hsep->queue))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) hsreq = list_entry(hsep->queue.next,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) struct s3c_hsudc_req, queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) s3c_hsudc_read_fifo(hsep, hsreq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) * s3c_hsudc_ep_enable - Enable a endpoint.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) * @_ep: The endpoint to be enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) * @desc: Endpoint descriptor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) * Enables a endpoint when called from the gadget driver. Endpoint stall if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) * any is cleared, transfer type is configured and endpoint interrupt is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) * enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) static int s3c_hsudc_ep_enable(struct usb_ep *_ep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) const struct usb_endpoint_descriptor *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) struct s3c_hsudc_ep *hsep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) struct s3c_hsudc *hsudc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) u32 ecr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) hsep = our_ep(_ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) if (!_ep || !desc || _ep->name == ep0name
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) || desc->bDescriptorType != USB_DT_ENDPOINT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) || hsep->bEndpointAddress != desc->bEndpointAddress
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) || ep_maxpacket(hsep) < usb_endpoint_maxp(desc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) if ((desc->bmAttributes == USB_ENDPOINT_XFER_BULK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) && usb_endpoint_maxp(desc) != ep_maxpacket(hsep))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) || !desc->wMaxPacketSize)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) return -ERANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) hsudc = hsep->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) if (!hsudc->driver || hsudc->gadget.speed == USB_SPEED_UNKNOWN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) return -ESHUTDOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) spin_lock_irqsave(&hsudc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) set_index(hsudc, hsep->bEndpointAddress);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) ecr |= ((usb_endpoint_xfer_int(desc)) ? S3C_ECR_IEMS : S3C_ECR_DUEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) writel(ecr, hsudc->regs + S3C_ECR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) hsep->stopped = hsep->wedge = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) hsep->ep.desc = desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) hsep->ep.maxpacket = usb_endpoint_maxp(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) s3c_hsudc_set_halt(_ep, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) __set_bit(ep_index(hsep), hsudc->regs + S3C_EIER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) spin_unlock_irqrestore(&hsudc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) * s3c_hsudc_ep_disable - Disable a endpoint.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) * @_ep: The endpoint to be disabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) * @desc: Endpoint descriptor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) * Disables a endpoint when called from the gadget driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) static int s3c_hsudc_ep_disable(struct usb_ep *_ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) struct s3c_hsudc_ep *hsep = our_ep(_ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) struct s3c_hsudc *hsudc = hsep->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) if (!_ep || !hsep->ep.desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) spin_lock_irqsave(&hsudc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) set_index(hsudc, hsep->bEndpointAddress);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) __clear_bit(ep_index(hsep), hsudc->regs + S3C_EIER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) s3c_hsudc_nuke_ep(hsep, -ESHUTDOWN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) hsep->ep.desc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) hsep->stopped = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) spin_unlock_irqrestore(&hsudc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) * s3c_hsudc_alloc_request - Allocate a new request.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) * @_ep: Endpoint for which request is allocated (not used).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) * @gfp_flags: Flags used for the allocation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) * Allocates a single transfer request structure when called from gadget driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) static struct usb_request *s3c_hsudc_alloc_request(struct usb_ep *_ep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) gfp_t gfp_flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) struct s3c_hsudc_req *hsreq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) hsreq = kzalloc(sizeof(*hsreq), gfp_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) if (!hsreq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) INIT_LIST_HEAD(&hsreq->queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) return &hsreq->req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) * s3c_hsudc_free_request - Deallocate a request.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) * @ep: Endpoint for which request is deallocated (not used).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) * @_req: Request to be deallocated.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) * Allocates a single transfer request structure when called from gadget driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) static void s3c_hsudc_free_request(struct usb_ep *ep, struct usb_request *_req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) struct s3c_hsudc_req *hsreq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) hsreq = our_req(_req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) WARN_ON(!list_empty(&hsreq->queue));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) kfree(hsreq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) * s3c_hsudc_queue - Queue a transfer request for the endpoint.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) * @_ep: Endpoint for which the request is queued.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) * @_req: Request to be queued.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) * @gfp_flags: Not used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) * Start or enqueue a request for a endpoint when called from gadget driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) static int s3c_hsudc_queue(struct usb_ep *_ep, struct usb_request *_req,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) gfp_t gfp_flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) struct s3c_hsudc_req *hsreq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) struct s3c_hsudc_ep *hsep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) struct s3c_hsudc *hsudc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) u32 offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) u32 csr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) hsreq = our_req(_req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) if ((!_req || !_req->complete || !_req->buf ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) !list_empty(&hsreq->queue)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) hsep = our_ep(_ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) hsudc = hsep->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) if (!hsudc->driver || hsudc->gadget.speed == USB_SPEED_UNKNOWN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) return -ESHUTDOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) spin_lock_irqsave(&hsudc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) set_index(hsudc, hsep->bEndpointAddress);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) _req->status = -EINPROGRESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) _req->actual = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) if (!ep_index(hsep) && _req->length == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) hsudc->ep0state = WAIT_FOR_SETUP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) s3c_hsudc_complete_request(hsep, hsreq, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) spin_unlock_irqrestore(&hsudc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) if (list_empty(&hsep->queue) && !hsep->stopped) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) offset = (ep_index(hsep)) ? S3C_ESR : S3C_EP0SR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) if (ep_is_in(hsep)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) csr = readl(hsudc->regs + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) if (!(csr & S3C_ESR_TX_SUCCESS) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) (s3c_hsudc_write_fifo(hsep, hsreq) == 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) hsreq = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) csr = readl(hsudc->regs + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) if ((csr & S3C_ESR_RX_SUCCESS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) && (s3c_hsudc_read_fifo(hsep, hsreq) == 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) hsreq = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) if (hsreq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) list_add_tail(&hsreq->queue, &hsep->queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) spin_unlock_irqrestore(&hsudc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) * s3c_hsudc_dequeue - Dequeue a transfer request from an endpoint.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) * @_ep: Endpoint from which the request is dequeued.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) * @_req: Request to be dequeued.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) * Dequeue a request from a endpoint when called from gadget driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) static int s3c_hsudc_dequeue(struct usb_ep *_ep, struct usb_request *_req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) struct s3c_hsudc_ep *hsep = our_ep(_ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) struct s3c_hsudc *hsudc = hsep->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) struct s3c_hsudc_req *hsreq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) hsep = our_ep(_ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) if (!_ep || hsep->ep.name == ep0name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) spin_lock_irqsave(&hsudc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) list_for_each_entry(hsreq, &hsep->queue, queue) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) if (&hsreq->req == _req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) if (&hsreq->req != _req) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) spin_unlock_irqrestore(&hsudc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) set_index(hsudc, hsep->bEndpointAddress);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) s3c_hsudc_complete_request(hsep, hsreq, -ECONNRESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) spin_unlock_irqrestore(&hsudc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) static const struct usb_ep_ops s3c_hsudc_ep_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) .enable = s3c_hsudc_ep_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) .disable = s3c_hsudc_ep_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) .alloc_request = s3c_hsudc_alloc_request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) .free_request = s3c_hsudc_free_request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) .queue = s3c_hsudc_queue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) .dequeue = s3c_hsudc_dequeue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) .set_halt = s3c_hsudc_set_halt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) .set_wedge = s3c_hsudc_set_wedge,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) * s3c_hsudc_initep - Initialize a endpoint to default state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) * @hsudc - Reference to the device controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) * @hsep - Endpoint to be initialized.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) * @epnum - Address to be assigned to the endpoint.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) * Initialize a endpoint with default configuration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) static void s3c_hsudc_initep(struct s3c_hsudc *hsudc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) struct s3c_hsudc_ep *hsep, int epnum)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) char *dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) if ((epnum % 2) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) dir = "out";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) dir = "in";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) hsep->bEndpointAddress = USB_DIR_IN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) hsep->bEndpointAddress |= epnum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) if (epnum)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) snprintf(hsep->name, sizeof(hsep->name), "ep%d%s", epnum, dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) snprintf(hsep->name, sizeof(hsep->name), "%s", ep0name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) INIT_LIST_HEAD(&hsep->queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) INIT_LIST_HEAD(&hsep->ep.ep_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) if (epnum)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) list_add_tail(&hsep->ep.ep_list, &hsudc->gadget.ep_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) hsep->dev = hsudc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) hsep->ep.name = hsep->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) usb_ep_set_maxpacket_limit(&hsep->ep, epnum ? 512 : 64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) hsep->ep.ops = &s3c_hsudc_ep_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) hsep->fifo = hsudc->regs + S3C_BR(epnum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) hsep->ep.desc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) hsep->stopped = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) hsep->wedge = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) if (epnum == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) hsep->ep.caps.type_control = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) hsep->ep.caps.dir_in = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) hsep->ep.caps.dir_out = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) hsep->ep.caps.type_iso = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) hsep->ep.caps.type_bulk = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) hsep->ep.caps.type_int = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) if (epnum & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) hsep->ep.caps.dir_in = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) hsep->ep.caps.dir_out = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) set_index(hsudc, epnum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) writel(hsep->ep.maxpacket, hsudc->regs + S3C_MPR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) * s3c_hsudc_setup_ep - Configure all endpoints to default state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) * @hsudc: Reference to device controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) * Configures all endpoints to default state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) static void s3c_hsudc_setup_ep(struct s3c_hsudc *hsudc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) int epnum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) hsudc->ep0state = WAIT_FOR_SETUP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) INIT_LIST_HEAD(&hsudc->gadget.ep_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) for (epnum = 0; epnum < hsudc->pd->epnum; epnum++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) s3c_hsudc_initep(hsudc, &hsudc->ep[epnum], epnum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) * s3c_hsudc_reconfig - Reconfigure the device controller to default state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) * @hsudc: Reference to device controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) * Reconfigures the device controller registers to a default state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) static void s3c_hsudc_reconfig(struct s3c_hsudc *hsudc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) writel(0xAA, hsudc->regs + S3C_EDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) writel(1, hsudc->regs + S3C_EIER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) writel(0, hsudc->regs + S3C_TR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) writel(S3C_SCR_DTZIEN_EN | S3C_SCR_RRD_EN | S3C_SCR_SUS_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) S3C_SCR_RST_EN, hsudc->regs + S3C_SCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) writel(0, hsudc->regs + S3C_EP0CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) s3c_hsudc_setup_ep(hsudc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) * s3c_hsudc_irq - Interrupt handler for device controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) * @irq: Not used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) * @_dev: Reference to the device controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) * Interrupt handler for the device controller. This handler handles controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) * interrupts and endpoint interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) static irqreturn_t s3c_hsudc_irq(int irq, void *_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) struct s3c_hsudc *hsudc = _dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) struct s3c_hsudc_ep *hsep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) u32 ep_intr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) u32 sys_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) u32 ep_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) spin_lock(&hsudc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) sys_status = readl(hsudc->regs + S3C_SSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) ep_intr = readl(hsudc->regs + S3C_EIR) & 0x3FF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) if (!ep_intr && !(sys_status & S3C_SSR_DTZIEN_EN)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) spin_unlock(&hsudc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) if (sys_status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) if (sys_status & S3C_SSR_VBUSON)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) writel(S3C_SSR_VBUSON, hsudc->regs + S3C_SSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) if (sys_status & S3C_SSR_ERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) writel(S3C_SSR_ERR, hsudc->regs + S3C_SSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) if (sys_status & S3C_SSR_SDE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) writel(S3C_SSR_SDE, hsudc->regs + S3C_SSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) hsudc->gadget.speed = (sys_status & S3C_SSR_HSP) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) USB_SPEED_HIGH : USB_SPEED_FULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) if (sys_status & S3C_SSR_SUSPEND) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) writel(S3C_SSR_SUSPEND, hsudc->regs + S3C_SSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) if (hsudc->gadget.speed != USB_SPEED_UNKNOWN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) && hsudc->driver && hsudc->driver->suspend)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) hsudc->driver->suspend(&hsudc->gadget);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) if (sys_status & S3C_SSR_RESUME) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) writel(S3C_SSR_RESUME, hsudc->regs + S3C_SSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) if (hsudc->gadget.speed != USB_SPEED_UNKNOWN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) && hsudc->driver && hsudc->driver->resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) hsudc->driver->resume(&hsudc->gadget);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) if (sys_status & S3C_SSR_RESET) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) writel(S3C_SSR_RESET, hsudc->regs + S3C_SSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) for (ep_idx = 0; ep_idx < hsudc->pd->epnum; ep_idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) hsep = &hsudc->ep[ep_idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) hsep->stopped = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) s3c_hsudc_nuke_ep(hsep, -ECONNRESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) s3c_hsudc_reconfig(hsudc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) hsudc->ep0state = WAIT_FOR_SETUP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) if (ep_intr & S3C_EIR_EP0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) writel(S3C_EIR_EP0, hsudc->regs + S3C_EIR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) set_index(hsudc, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) s3c_hsudc_handle_ep0_intr(hsudc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) ep_intr >>= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) ep_idx = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) while (ep_intr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) if (ep_intr & 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) hsep = &hsudc->ep[ep_idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) set_index(hsudc, ep_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) writel(1 << ep_idx, hsudc->regs + S3C_EIR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) if (ep_is_in(hsep))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) s3c_hsudc_epin_intr(hsudc, ep_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) s3c_hsudc_epout_intr(hsudc, ep_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) ep_intr >>= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) ep_idx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) spin_unlock(&hsudc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) static int s3c_hsudc_start(struct usb_gadget *gadget,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) struct usb_gadget_driver *driver)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) struct s3c_hsudc *hsudc = to_hsudc(gadget);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) if (!driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) || driver->max_speed < USB_SPEED_FULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) || !driver->setup)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) if (!hsudc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) if (hsudc->driver)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) hsudc->driver = driver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) ret = regulator_bulk_enable(ARRAY_SIZE(hsudc->supplies),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) hsudc->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) if (ret != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) dev_err(hsudc->dev, "failed to enable supplies: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) goto err_supplies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) /* connect to bus through transceiver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) if (!IS_ERR_OR_NULL(hsudc->transceiver)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) ret = otg_set_peripheral(hsudc->transceiver->otg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) &hsudc->gadget);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) dev_err(hsudc->dev, "%s: can't bind to transceiver\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) hsudc->gadget.name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) goto err_otg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) enable_irq(hsudc->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) s3c_hsudc_reconfig(hsudc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) pm_runtime_get_sync(hsudc->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) if (hsudc->pd->phy_init)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) hsudc->pd->phy_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) if (hsudc->pd->gpio_init)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) hsudc->pd->gpio_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) err_otg:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) regulator_bulk_disable(ARRAY_SIZE(hsudc->supplies), hsudc->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) err_supplies:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) hsudc->driver = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) static int s3c_hsudc_stop(struct usb_gadget *gadget)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) struct s3c_hsudc *hsudc = to_hsudc(gadget);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) if (!hsudc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) spin_lock_irqsave(&hsudc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) hsudc->gadget.speed = USB_SPEED_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) if (hsudc->pd->phy_uninit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) hsudc->pd->phy_uninit();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) pm_runtime_put(hsudc->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) if (hsudc->pd->gpio_uninit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) hsudc->pd->gpio_uninit();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) s3c_hsudc_stop_activity(hsudc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) spin_unlock_irqrestore(&hsudc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) if (!IS_ERR_OR_NULL(hsudc->transceiver))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) (void) otg_set_peripheral(hsudc->transceiver->otg, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) disable_irq(hsudc->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) regulator_bulk_disable(ARRAY_SIZE(hsudc->supplies), hsudc->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) hsudc->driver = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) static inline u32 s3c_hsudc_read_frameno(struct s3c_hsudc *hsudc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) return readl(hsudc->regs + S3C_FNR) & 0x3FF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) static int s3c_hsudc_gadget_getframe(struct usb_gadget *gadget)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) return s3c_hsudc_read_frameno(to_hsudc(gadget));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) static int s3c_hsudc_vbus_draw(struct usb_gadget *gadget, unsigned mA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) struct s3c_hsudc *hsudc = to_hsudc(gadget);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) if (!hsudc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) if (!IS_ERR_OR_NULL(hsudc->transceiver))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) return usb_phy_set_power(hsudc->transceiver, mA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) static const struct usb_gadget_ops s3c_hsudc_gadget_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) .get_frame = s3c_hsudc_gadget_getframe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) .udc_start = s3c_hsudc_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) .udc_stop = s3c_hsudc_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) .vbus_draw = s3c_hsudc_vbus_draw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) static int s3c_hsudc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) struct s3c_hsudc *hsudc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) struct s3c24xx_hsudc_platdata *pd = dev_get_platdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) hsudc = devm_kzalloc(&pdev->dev, sizeof(struct s3c_hsudc) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) sizeof(struct s3c_hsudc_ep) * pd->epnum,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) if (!hsudc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) platform_set_drvdata(pdev, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) hsudc->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) hsudc->pd = dev_get_platdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) hsudc->transceiver = usb_get_phy(USB_PHY_TYPE_USB2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) for (i = 0; i < ARRAY_SIZE(hsudc->supplies); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) hsudc->supplies[i].supply = s3c_hsudc_supply_names[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(hsudc->supplies),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) hsudc->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) if (ret != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) if (ret != -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) dev_err(dev, "failed to request supplies: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) goto err_supplies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) hsudc->regs = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) if (IS_ERR(hsudc->regs)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) ret = PTR_ERR(hsudc->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) goto err_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) spin_lock_init(&hsudc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) hsudc->gadget.max_speed = USB_SPEED_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) hsudc->gadget.ops = &s3c_hsudc_gadget_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) hsudc->gadget.name = dev_name(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) hsudc->gadget.ep0 = &hsudc->ep[0].ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) hsudc->gadget.is_otg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) hsudc->gadget.is_a_peripheral = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) hsudc->gadget.speed = USB_SPEED_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) s3c_hsudc_setup_ep(hsudc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) ret = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) goto err_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) hsudc->irq = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) ret = devm_request_irq(&pdev->dev, hsudc->irq, s3c_hsudc_irq, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) driver_name, hsudc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) dev_err(dev, "irq request failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) goto err_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) hsudc->uclk = devm_clk_get(&pdev->dev, "usb-device");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) if (IS_ERR(hsudc->uclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) dev_err(dev, "failed to find usb-device clock source\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) ret = PTR_ERR(hsudc->uclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) goto err_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) clk_enable(hsudc->uclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) local_irq_disable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) disable_irq(hsudc->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) local_irq_enable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) ret = usb_add_gadget_udc(&pdev->dev, &hsudc->gadget);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) goto err_add_udc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) pm_runtime_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) err_add_udc:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) clk_disable(hsudc->uclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) err_res:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) if (!IS_ERR_OR_NULL(hsudc->transceiver))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) usb_put_phy(hsudc->transceiver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) err_supplies:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) static struct platform_driver s3c_hsudc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) .name = "s3c-hsudc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) .probe = s3c_hsudc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) module_platform_driver(s3c_hsudc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) MODULE_DESCRIPTION("Samsung S3C24XX USB high-speed controller driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) MODULE_AUTHOR("Thomas Abraham <thomas.ab@samsung.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) MODULE_ALIAS("platform:s3c-hsudc");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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