^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * R8A66597 UDC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2007-2009 Renesas Solutions Corp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author : Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #ifndef __R8A66597_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define __R8A66597_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/usb/r8a66597.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define R8A66597_MAX_SAMPLING 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define R8A66597_MAX_NUM_PIPE 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define R8A66597_MAX_NUM_BULK 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define R8A66597_MAX_NUM_ISOC 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define R8A66597_MAX_NUM_INT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define R8A66597_BASE_PIPENUM_BULK 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define R8A66597_BASE_PIPENUM_ISOC 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define R8A66597_BASE_PIPENUM_INT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define R8A66597_BASE_BUFNUM 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define R8A66597_MAX_BUFNUM 0x4F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define is_bulk_pipe(pipenum) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) ((pipenum >= R8A66597_BASE_PIPENUM_BULK) && \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) (pipenum < (R8A66597_BASE_PIPENUM_BULK + R8A66597_MAX_NUM_BULK)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define is_interrupt_pipe(pipenum) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) ((pipenum >= R8A66597_BASE_PIPENUM_INT) && \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) (pipenum < (R8A66597_BASE_PIPENUM_INT + R8A66597_MAX_NUM_INT)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define is_isoc_pipe(pipenum) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) ((pipenum >= R8A66597_BASE_PIPENUM_ISOC) && \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) (pipenum < (R8A66597_BASE_PIPENUM_ISOC + R8A66597_MAX_NUM_ISOC)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define r8a66597_is_sudmac(r8a66597) (r8a66597->pdata->sudmac)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) struct r8a66597_pipe_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) u16 pipe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) u16 epnum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) u16 maxpacket;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) u16 type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) u16 interval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) u16 dir_in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) struct r8a66597_request {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) struct usb_request req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) struct list_head queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) struct r8a66597_ep {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) struct usb_ep ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) struct r8a66597 *r8a66597;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) struct r8a66597_dma *dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) struct list_head queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) unsigned busy:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) unsigned wedge:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) unsigned internal_ccpl:1; /* use only control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /* this member can able to after r8a66597_enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) unsigned use_dma:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) u16 pipenum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) u16 type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /* register address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) unsigned char fifoaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) unsigned char fifosel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) unsigned char fifoctr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) unsigned char pipectr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) unsigned char pipetre;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) unsigned char pipetrn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) struct r8a66597_dma {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) unsigned used:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) unsigned dir:1; /* 1 = IN(write), 0 = OUT(read) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) struct r8a66597 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) void __iomem *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) void __iomem *sudmac_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) struct r8a66597_platdata *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) struct usb_gadget gadget;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) struct usb_gadget_driver *driver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct r8a66597_ep ep[R8A66597_MAX_NUM_PIPE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) struct r8a66597_ep *pipenum2ep[R8A66597_MAX_NUM_PIPE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) struct r8a66597_ep *epaddr2ep[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) struct r8a66597_dma dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) struct timer_list timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) struct usb_request *ep0_req; /* for internal request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) u16 ep0_data; /* for internal request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) u16 old_vbus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) u16 scount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) u16 old_dvsq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) u16 device_status; /* for GET_STATUS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* pipe config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) unsigned char bulk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) unsigned char interrupt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) unsigned char isochronous;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) unsigned char num_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) unsigned irq_sense_low:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define gadget_to_r8a66597(_gadget) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) container_of(_gadget, struct r8a66597, gadget)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define r8a66597_to_gadget(r8a66597) (&r8a66597->gadget)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define r8a66597_to_dev(r8a66597) (r8a66597->gadget.dev.parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static inline u16 r8a66597_read(struct r8a66597 *r8a66597, unsigned long offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) return ioread16(r8a66597->reg + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static inline void r8a66597_read_fifo(struct r8a66597 *r8a66597,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) unsigned long offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) unsigned char *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) void __iomem *fifoaddr = r8a66597->reg + offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) unsigned int data = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) if (r8a66597->pdata->on_chip) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /* 32-bit accesses for on_chip controllers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) /* aligned buf case */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) if (len >= 4 && !((unsigned long)buf & 0x03)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) ioread32_rep(fifoaddr, buf, len / 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) buf += len & ~0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) len &= 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /* unaligned buf case */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) for (i = 0; i < len; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) if (!(i & 0x03))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) data = ioread32(fifoaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) buf[i] = (data >> ((i & 0x03) * 8)) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) /* 16-bit accesses for external controllers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /* aligned buf case */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) if (len >= 2 && !((unsigned long)buf & 0x01)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) ioread16_rep(fifoaddr, buf, len / 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) buf += len & ~0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) len &= 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) /* unaligned buf case */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) for (i = 0; i < len; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) if (!(i & 0x01))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) data = ioread16(fifoaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) buf[i] = (data >> ((i & 0x01) * 8)) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) static inline void r8a66597_write(struct r8a66597 *r8a66597, u16 val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) unsigned long offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) iowrite16(val, r8a66597->reg + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static inline void r8a66597_mdfy(struct r8a66597 *r8a66597,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) u16 val, u16 pat, unsigned long offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) u16 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) tmp = r8a66597_read(r8a66597, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) tmp = tmp & (~pat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) tmp = tmp | val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) r8a66597_write(r8a66597, tmp, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define r8a66597_bclr(r8a66597, val, offset) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) r8a66597_mdfy(r8a66597, 0, val, offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define r8a66597_bset(r8a66597, val, offset) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) r8a66597_mdfy(r8a66597, val, 0, offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static inline void r8a66597_write_fifo(struct r8a66597 *r8a66597,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) struct r8a66597_ep *ep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) unsigned char *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) void __iomem *fifoaddr = r8a66597->reg + ep->fifoaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) int adj = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) if (r8a66597->pdata->on_chip) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) /* 32-bit access only if buf is 32-bit aligned */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) if (len >= 4 && !((unsigned long)buf & 0x03)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) iowrite32_rep(fifoaddr, buf, len / 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) buf += len & ~0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) len &= 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) /* 16-bit access only if buf is 16-bit aligned */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) if (len >= 2 && !((unsigned long)buf & 0x01)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) iowrite16_rep(fifoaddr, buf, len / 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) buf += len & ~0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) len &= 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) /* adjust fifo address in the little endian case */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) if (!(r8a66597_read(r8a66597, CFIFOSEL) & BIGEND)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) if (r8a66597->pdata->on_chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) adj = 0x03; /* 32-bit wide */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) adj = 0x01; /* 16-bit wide */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) if (r8a66597->pdata->wr0_shorted_to_wr1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) r8a66597_bclr(r8a66597, MBW_16, ep->fifosel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) for (i = 0; i < len; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) iowrite8(buf[i], fifoaddr + adj - (i & adj));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) if (r8a66597->pdata->wr0_shorted_to_wr1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) r8a66597_bclr(r8a66597, MBW_16, ep->fifosel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) static inline u16 get_xtal_from_pdata(struct r8a66597_platdata *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) u16 clock = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) switch (pdata->xtal) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) case R8A66597_PLATDATA_XTAL_12MHZ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) clock = XTAL12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) case R8A66597_PLATDATA_XTAL_24MHZ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) clock = XTAL24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) case R8A66597_PLATDATA_XTAL_48MHZ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) clock = XTAL48;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) printk(KERN_ERR "r8a66597: platdata clock is wrong.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) return clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) static inline u32 r8a66597_sudmac_read(struct r8a66597 *r8a66597,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) unsigned long offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) return ioread32(r8a66597->sudmac_reg + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static inline void r8a66597_sudmac_write(struct r8a66597 *r8a66597, u32 val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) unsigned long offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) iowrite32(val, r8a66597->sudmac_reg + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define get_pipectr_addr(pipenum) (PIPE1CTR + (pipenum - 1) * 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define get_pipetre_addr(pipenum) (PIPE1TRE + (pipenum - 1) * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define get_pipetrn_addr(pipenum) (PIPE1TRN + (pipenum - 1) * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define enable_irq_ready(r8a66597, pipenum) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) enable_pipe_irq(r8a66597, pipenum, BRDYENB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define disable_irq_ready(r8a66597, pipenum) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) disable_pipe_irq(r8a66597, pipenum, BRDYENB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define enable_irq_empty(r8a66597, pipenum) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) enable_pipe_irq(r8a66597, pipenum, BEMPENB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define disable_irq_empty(r8a66597, pipenum) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) disable_pipe_irq(r8a66597, pipenum, BEMPENB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define enable_irq_nrdy(r8a66597, pipenum) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) enable_pipe_irq(r8a66597, pipenum, NRDYENB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define disable_irq_nrdy(r8a66597, pipenum) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) disable_pipe_irq(r8a66597, pipenum, NRDYENB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #endif /* __R8A66597_H__ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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