^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * R8A66597 UDC (USB gadget)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2006-2009 Renesas Solutions Corp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author : Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/usb/ch9.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/usb/gadget.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include "r8a66597-udc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define DRIVER_VERSION "2011-09-26"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) static const char udc_name[] = "r8a66597_udc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) static const char *r8a66597_ep_name[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) "ep0", "ep1", "ep2", "ep3", "ep4", "ep5", "ep6", "ep7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) "ep8", "ep9",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) static void init_controller(struct r8a66597 *r8a66597);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) static void disable_controller(struct r8a66597 *r8a66597);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) static void irq_ep0_write(struct r8a66597_ep *ep, struct r8a66597_request *req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) static void irq_packet_write(struct r8a66597_ep *ep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) struct r8a66597_request *req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) static int r8a66597_queue(struct usb_ep *_ep, struct usb_request *_req,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) gfp_t gfp_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) static void transfer_complete(struct r8a66597_ep *ep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) struct r8a66597_request *req, int status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /*-------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) static inline u16 get_usb_speed(struct r8a66597 *r8a66597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) return r8a66597_read(r8a66597, DVSTCTR0) & RHST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) static void enable_pipe_irq(struct r8a66597 *r8a66597, u16 pipenum,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) unsigned long reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) u16 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) tmp = r8a66597_read(r8a66597, INTENB0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) r8a66597_bclr(r8a66597, BEMPE | NRDYE | BRDYE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) INTENB0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) r8a66597_bset(r8a66597, (1 << pipenum), reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) r8a66597_write(r8a66597, tmp, INTENB0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) static void disable_pipe_irq(struct r8a66597 *r8a66597, u16 pipenum,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) unsigned long reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) u16 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) tmp = r8a66597_read(r8a66597, INTENB0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) r8a66597_bclr(r8a66597, BEMPE | NRDYE | BRDYE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) INTENB0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) r8a66597_bclr(r8a66597, (1 << pipenum), reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) r8a66597_write(r8a66597, tmp, INTENB0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) static void r8a66597_usb_connect(struct r8a66597 *r8a66597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) r8a66597_bset(r8a66597, CTRE, INTENB0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) r8a66597_bset(r8a66597, BEMPE | BRDYE, INTENB0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) r8a66597_bset(r8a66597, DPRPU, SYSCFG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) static void r8a66597_usb_disconnect(struct r8a66597 *r8a66597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) __releases(r8a66597->lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) __acquires(r8a66597->lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) r8a66597_bclr(r8a66597, CTRE, INTENB0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) r8a66597_bclr(r8a66597, BEMPE | BRDYE, INTENB0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) r8a66597_bclr(r8a66597, DPRPU, SYSCFG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) r8a66597->gadget.speed = USB_SPEED_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) spin_unlock(&r8a66597->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) r8a66597->driver->disconnect(&r8a66597->gadget);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) spin_lock(&r8a66597->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) disable_controller(r8a66597);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) init_controller(r8a66597);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) r8a66597_bset(r8a66597, VBSE, INTENB0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) INIT_LIST_HEAD(&r8a66597->ep[0].queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static inline u16 control_reg_get_pid(struct r8a66597 *r8a66597, u16 pipenum)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) u16 pid = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) unsigned long offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) if (pipenum == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) pid = r8a66597_read(r8a66597, DCPCTR) & PID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) } else if (pipenum < R8A66597_MAX_NUM_PIPE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) offset = get_pipectr_addr(pipenum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) pid = r8a66597_read(r8a66597, offset) & PID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) dev_err(r8a66597_to_dev(r8a66597), "unexpect pipe num (%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) pipenum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) return pid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static inline void control_reg_set_pid(struct r8a66597 *r8a66597, u16 pipenum,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) u16 pid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) unsigned long offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) if (pipenum == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) r8a66597_mdfy(r8a66597, pid, PID, DCPCTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) } else if (pipenum < R8A66597_MAX_NUM_PIPE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) offset = get_pipectr_addr(pipenum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) r8a66597_mdfy(r8a66597, pid, PID, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) dev_err(r8a66597_to_dev(r8a66597), "unexpect pipe num (%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) pipenum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) static inline void pipe_start(struct r8a66597 *r8a66597, u16 pipenum)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) control_reg_set_pid(r8a66597, pipenum, PID_BUF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static inline void pipe_stop(struct r8a66597 *r8a66597, u16 pipenum)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) control_reg_set_pid(r8a66597, pipenum, PID_NAK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static inline void pipe_stall(struct r8a66597 *r8a66597, u16 pipenum)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) control_reg_set_pid(r8a66597, pipenum, PID_STALL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static inline u16 control_reg_get(struct r8a66597 *r8a66597, u16 pipenum)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) u16 ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) unsigned long offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) if (pipenum == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) ret = r8a66597_read(r8a66597, DCPCTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) } else if (pipenum < R8A66597_MAX_NUM_PIPE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) offset = get_pipectr_addr(pipenum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) ret = r8a66597_read(r8a66597, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) dev_err(r8a66597_to_dev(r8a66597), "unexpect pipe num (%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) pipenum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static inline void control_reg_sqclr(struct r8a66597 *r8a66597, u16 pipenum)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) unsigned long offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) pipe_stop(r8a66597, pipenum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) if (pipenum == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) r8a66597_bset(r8a66597, SQCLR, DCPCTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) } else if (pipenum < R8A66597_MAX_NUM_PIPE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) offset = get_pipectr_addr(pipenum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) r8a66597_bset(r8a66597, SQCLR, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) dev_err(r8a66597_to_dev(r8a66597), "unexpect pipe num (%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) pipenum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) static void control_reg_sqset(struct r8a66597 *r8a66597, u16 pipenum)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) unsigned long offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) pipe_stop(r8a66597, pipenum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) if (pipenum == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) r8a66597_bset(r8a66597, SQSET, DCPCTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) } else if (pipenum < R8A66597_MAX_NUM_PIPE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) offset = get_pipectr_addr(pipenum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) r8a66597_bset(r8a66597, SQSET, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) dev_err(r8a66597_to_dev(r8a66597),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) "unexpect pipe num(%d)\n", pipenum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static u16 control_reg_sqmon(struct r8a66597 *r8a66597, u16 pipenum)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) unsigned long offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) if (pipenum == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) return r8a66597_read(r8a66597, DCPCTR) & SQMON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) } else if (pipenum < R8A66597_MAX_NUM_PIPE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) offset = get_pipectr_addr(pipenum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) return r8a66597_read(r8a66597, offset) & SQMON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) dev_err(r8a66597_to_dev(r8a66597),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) "unexpect pipe num(%d)\n", pipenum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) static u16 save_usb_toggle(struct r8a66597 *r8a66597, u16 pipenum)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) return control_reg_sqmon(r8a66597, pipenum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) static void restore_usb_toggle(struct r8a66597 *r8a66597, u16 pipenum,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) u16 toggle)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) if (toggle)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) control_reg_sqset(r8a66597, pipenum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) control_reg_sqclr(r8a66597, pipenum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) static inline int get_buffer_size(struct r8a66597 *r8a66597, u16 pipenum)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) u16 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) int size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) if (pipenum == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) tmp = r8a66597_read(r8a66597, DCPCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) if ((tmp & R8A66597_CNTMD) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) size = 256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) tmp = r8a66597_read(r8a66597, DCPMAXP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) size = tmp & MAXP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) r8a66597_write(r8a66597, pipenum, PIPESEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) tmp = r8a66597_read(r8a66597, PIPECFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) if ((tmp & R8A66597_CNTMD) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) tmp = r8a66597_read(r8a66597, PIPEBUF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) size = ((tmp >> 10) + 1) * 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) tmp = r8a66597_read(r8a66597, PIPEMAXP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) size = tmp & MXPS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) return size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) static inline unsigned short mbw_value(struct r8a66597 *r8a66597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) if (r8a66597->pdata->on_chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) return MBW_32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) return MBW_16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) static void r8a66597_change_curpipe(struct r8a66597 *r8a66597, u16 pipenum,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) u16 isel, u16 fifosel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) u16 tmp, mask, loop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) if (!pipenum) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) mask = ISEL | CURPIPE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) loop = isel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) mask = CURPIPE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) loop = pipenum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) r8a66597_mdfy(r8a66597, loop, mask, fifosel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) tmp = r8a66597_read(r8a66597, fifosel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) if (i++ > 1000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) dev_err(r8a66597_to_dev(r8a66597),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) "r8a66597: register%x, loop %x "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) "is timeout\n", fifosel, loop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) ndelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) } while ((tmp & mask) != loop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) static void pipe_change(struct r8a66597 *r8a66597, u16 pipenum)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) struct r8a66597_ep *ep = r8a66597->pipenum2ep[pipenum];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) if (ep->use_dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) r8a66597_bclr(r8a66597, DREQE, ep->fifosel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) r8a66597_mdfy(r8a66597, pipenum, CURPIPE, ep->fifosel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) ndelay(450);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) if (r8a66597_is_sudmac(r8a66597) && ep->use_dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) r8a66597_bclr(r8a66597, mbw_value(r8a66597), ep->fifosel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) r8a66597_bset(r8a66597, mbw_value(r8a66597), ep->fifosel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) if (ep->use_dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) r8a66597_bset(r8a66597, DREQE, ep->fifosel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) static int pipe_buffer_setting(struct r8a66597 *r8a66597,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) struct r8a66597_pipe_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) u16 bufnum = 0, buf_bsize = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) u16 pipecfg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) if (info->pipe == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) r8a66597_write(r8a66597, info->pipe, PIPESEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) if (info->dir_in)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) pipecfg |= R8A66597_DIR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) pipecfg |= info->type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) pipecfg |= info->epnum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) switch (info->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) case R8A66597_INT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) bufnum = 4 + (info->pipe - R8A66597_BASE_PIPENUM_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) buf_bsize = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) case R8A66597_BULK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) /* isochronous pipes may be used as bulk pipes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) if (info->pipe >= R8A66597_BASE_PIPENUM_BULK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) bufnum = info->pipe - R8A66597_BASE_PIPENUM_BULK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) bufnum = info->pipe - R8A66597_BASE_PIPENUM_ISOC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) bufnum = R8A66597_BASE_BUFNUM + (bufnum * 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) buf_bsize = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) pipecfg |= R8A66597_DBLB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) if (!info->dir_in)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) pipecfg |= R8A66597_SHTNAK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) case R8A66597_ISO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) bufnum = R8A66597_BASE_BUFNUM +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) (info->pipe - R8A66597_BASE_PIPENUM_ISOC) * 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) buf_bsize = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) if (buf_bsize && ((bufnum + 16) >= R8A66597_MAX_BUFNUM)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) pr_err("r8a66597 pipe memory is insufficient\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) r8a66597_write(r8a66597, pipecfg, PIPECFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) r8a66597_write(r8a66597, (buf_bsize << 10) | (bufnum), PIPEBUF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) r8a66597_write(r8a66597, info->maxpacket, PIPEMAXP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) if (info->interval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) info->interval--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) r8a66597_write(r8a66597, info->interval, PIPEPERI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) static void pipe_buffer_release(struct r8a66597 *r8a66597,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) struct r8a66597_pipe_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) if (info->pipe == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) if (is_bulk_pipe(info->pipe)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) r8a66597->bulk--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) } else if (is_interrupt_pipe(info->pipe)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) r8a66597->interrupt--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) } else if (is_isoc_pipe(info->pipe)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) r8a66597->isochronous--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) if (info->type == R8A66597_BULK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) r8a66597->bulk--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) dev_err(r8a66597_to_dev(r8a66597),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) "ep_release: unexpect pipenum (%d)\n", info->pipe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) static void pipe_initialize(struct r8a66597_ep *ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) struct r8a66597 *r8a66597 = ep->r8a66597;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) r8a66597_mdfy(r8a66597, 0, CURPIPE, ep->fifosel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) r8a66597_write(r8a66597, ACLRM, ep->pipectr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) r8a66597_write(r8a66597, 0, ep->pipectr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) r8a66597_write(r8a66597, SQCLR, ep->pipectr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) if (ep->use_dma) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) r8a66597_mdfy(r8a66597, ep->pipenum, CURPIPE, ep->fifosel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) ndelay(450);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) r8a66597_bset(r8a66597, mbw_value(r8a66597), ep->fifosel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) static void r8a66597_ep_setting(struct r8a66597 *r8a66597,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) struct r8a66597_ep *ep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) const struct usb_endpoint_descriptor *desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) u16 pipenum, int dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) ep->use_dma = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) ep->fifoaddr = CFIFO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) ep->fifosel = CFIFOSEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) ep->fifoctr = CFIFOCTR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) ep->pipectr = get_pipectr_addr(pipenum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) if (is_bulk_pipe(pipenum) || is_isoc_pipe(pipenum)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) ep->pipetre = get_pipetre_addr(pipenum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) ep->pipetrn = get_pipetrn_addr(pipenum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) ep->pipetre = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) ep->pipetrn = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) ep->pipenum = pipenum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) ep->ep.maxpacket = usb_endpoint_maxp(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) r8a66597->pipenum2ep[pipenum] = ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) r8a66597->epaddr2ep[usb_endpoint_num(desc)]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) = ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) INIT_LIST_HEAD(&ep->queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) static void r8a66597_ep_release(struct r8a66597_ep *ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) struct r8a66597 *r8a66597 = ep->r8a66597;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) u16 pipenum = ep->pipenum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) if (pipenum == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) if (ep->use_dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) r8a66597->num_dma--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) ep->pipenum = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) ep->busy = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) ep->use_dma = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) static int alloc_pipe_config(struct r8a66597_ep *ep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) const struct usb_endpoint_descriptor *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) struct r8a66597 *r8a66597 = ep->r8a66597;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) struct r8a66597_pipe_info info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) int dma = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) unsigned char *counter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) ep->ep.desc = desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) if (ep->pipenum) /* already allocated pipe */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) switch (usb_endpoint_type(desc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) case USB_ENDPOINT_XFER_BULK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) if (r8a66597->bulk >= R8A66597_MAX_NUM_BULK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) if (r8a66597->isochronous >= R8A66597_MAX_NUM_ISOC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) dev_err(r8a66597_to_dev(r8a66597),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) "bulk pipe is insufficient\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) info.pipe = R8A66597_BASE_PIPENUM_ISOC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) + r8a66597->isochronous;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) counter = &r8a66597->isochronous;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) info.pipe = R8A66597_BASE_PIPENUM_BULK + r8a66597->bulk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) counter = &r8a66597->bulk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) info.type = R8A66597_BULK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) dma = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) case USB_ENDPOINT_XFER_INT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) if (r8a66597->interrupt >= R8A66597_MAX_NUM_INT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) dev_err(r8a66597_to_dev(r8a66597),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) "interrupt pipe is insufficient\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) info.pipe = R8A66597_BASE_PIPENUM_INT + r8a66597->interrupt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) info.type = R8A66597_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) counter = &r8a66597->interrupt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) case USB_ENDPOINT_XFER_ISOC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) if (r8a66597->isochronous >= R8A66597_MAX_NUM_ISOC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) dev_err(r8a66597_to_dev(r8a66597),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) "isochronous pipe is insufficient\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) info.pipe = R8A66597_BASE_PIPENUM_ISOC + r8a66597->isochronous;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) info.type = R8A66597_ISO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) counter = &r8a66597->isochronous;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) dev_err(r8a66597_to_dev(r8a66597), "unexpect xfer type\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) ep->type = info.type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) info.epnum = usb_endpoint_num(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) info.maxpacket = usb_endpoint_maxp(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) info.interval = desc->bInterval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) if (desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) info.dir_in = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) info.dir_in = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) ret = pipe_buffer_setting(r8a66597, &info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) dev_err(r8a66597_to_dev(r8a66597),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) "pipe_buffer_setting fail\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) (*counter)++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) if ((counter == &r8a66597->isochronous) && info.type == R8A66597_BULK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) r8a66597->bulk++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) r8a66597_ep_setting(r8a66597, ep, desc, info.pipe, dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) pipe_initialize(ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) static int free_pipe_config(struct r8a66597_ep *ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) struct r8a66597 *r8a66597 = ep->r8a66597;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) struct r8a66597_pipe_info info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) info.pipe = ep->pipenum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) info.type = ep->type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) pipe_buffer_release(r8a66597, &info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) r8a66597_ep_release(ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) /*-------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) static void pipe_irq_enable(struct r8a66597 *r8a66597, u16 pipenum)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) enable_irq_ready(r8a66597, pipenum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) enable_irq_nrdy(r8a66597, pipenum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) static void pipe_irq_disable(struct r8a66597 *r8a66597, u16 pipenum)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) disable_irq_ready(r8a66597, pipenum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) disable_irq_nrdy(r8a66597, pipenum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) /* if complete is true, gadget driver complete function is not call */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) static void control_end(struct r8a66597 *r8a66597, unsigned ccpl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) r8a66597->ep[0].internal_ccpl = ccpl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) pipe_start(r8a66597, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) r8a66597_bset(r8a66597, CCPL, DCPCTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) static void start_ep0_write(struct r8a66597_ep *ep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) struct r8a66597_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) struct r8a66597 *r8a66597 = ep->r8a66597;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) pipe_change(r8a66597, ep->pipenum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) r8a66597_mdfy(r8a66597, ISEL, (ISEL | CURPIPE), CFIFOSEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) r8a66597_write(r8a66597, BCLR, ep->fifoctr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) if (req->req.length == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) r8a66597_bset(r8a66597, BVAL, ep->fifoctr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) pipe_start(r8a66597, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) transfer_complete(ep, req, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) r8a66597_write(r8a66597, ~BEMP0, BEMPSTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) irq_ep0_write(ep, req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) static void disable_fifosel(struct r8a66597 *r8a66597, u16 pipenum,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) u16 fifosel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) u16 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) tmp = r8a66597_read(r8a66597, fifosel) & CURPIPE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) if (tmp == pipenum)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) r8a66597_change_curpipe(r8a66597, 0, 0, fifosel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) static void change_bfre_mode(struct r8a66597 *r8a66597, u16 pipenum,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) struct r8a66597_ep *ep = r8a66597->pipenum2ep[pipenum];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) u16 tmp, toggle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) /* check current BFRE bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) r8a66597_write(r8a66597, pipenum, PIPESEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) tmp = r8a66597_read(r8a66597, PIPECFG) & R8A66597_BFRE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) if ((enable && tmp) || (!enable && !tmp))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) /* change BFRE bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) pipe_stop(r8a66597, pipenum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) disable_fifosel(r8a66597, pipenum, CFIFOSEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) disable_fifosel(r8a66597, pipenum, D0FIFOSEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) disable_fifosel(r8a66597, pipenum, D1FIFOSEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) toggle = save_usb_toggle(r8a66597, pipenum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) r8a66597_write(r8a66597, pipenum, PIPESEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) r8a66597_bset(r8a66597, R8A66597_BFRE, PIPECFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) r8a66597_bclr(r8a66597, R8A66597_BFRE, PIPECFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) /* initialize for internal BFRE flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) r8a66597_bset(r8a66597, ACLRM, ep->pipectr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) r8a66597_bclr(r8a66597, ACLRM, ep->pipectr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) restore_usb_toggle(r8a66597, pipenum, toggle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) static int sudmac_alloc_channel(struct r8a66597 *r8a66597,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) struct r8a66597_ep *ep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) struct r8a66597_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) struct r8a66597_dma *dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) if (!r8a66597_is_sudmac(r8a66597))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) /* Check transfer type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) if (!is_bulk_pipe(ep->pipenum))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) if (r8a66597->dma.used)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) /* set SUDMAC parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) dma = &r8a66597->dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) dma->used = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) if (ep->ep.desc->bEndpointAddress & USB_DIR_IN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) dma->dir = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) dma->dir = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) change_bfre_mode(r8a66597, ep->pipenum, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) /* set r8a66597_ep paramters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) ep->use_dma = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) ep->dma = dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) ep->fifoaddr = D0FIFO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) ep->fifosel = D0FIFOSEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) ep->fifoctr = D0FIFOCTR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) /* dma mapping */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) return usb_gadget_map_request(&r8a66597->gadget, &req->req, dma->dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) static void sudmac_free_channel(struct r8a66597 *r8a66597,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) struct r8a66597_ep *ep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) struct r8a66597_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) if (!r8a66597_is_sudmac(r8a66597))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) usb_gadget_unmap_request(&r8a66597->gadget, &req->req, ep->dma->dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) r8a66597_bclr(r8a66597, DREQE, ep->fifosel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) r8a66597_change_curpipe(r8a66597, 0, 0, ep->fifosel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) ep->dma->used = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) ep->use_dma = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) ep->fifoaddr = CFIFO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) ep->fifosel = CFIFOSEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) ep->fifoctr = CFIFOCTR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) static void sudmac_start(struct r8a66597 *r8a66597, struct r8a66597_ep *ep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) struct r8a66597_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) BUG_ON(req->req.length == 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) r8a66597_sudmac_write(r8a66597, LBA_WAIT, CH0CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) r8a66597_sudmac_write(r8a66597, req->req.dma, CH0BA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) r8a66597_sudmac_write(r8a66597, req->req.length, CH0BBC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) r8a66597_sudmac_write(r8a66597, CH0ENDE, DINTCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) r8a66597_sudmac_write(r8a66597, DEN, CH0DEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) static void start_packet_write(struct r8a66597_ep *ep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) struct r8a66597_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) struct r8a66597 *r8a66597 = ep->r8a66597;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) u16 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) pipe_change(r8a66597, ep->pipenum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) disable_irq_empty(r8a66597, ep->pipenum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) pipe_start(r8a66597, ep->pipenum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) if (req->req.length == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) transfer_complete(ep, req, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) r8a66597_write(r8a66597, ~(1 << ep->pipenum), BRDYSTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) if (sudmac_alloc_channel(r8a66597, ep, req) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) /* PIO mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) pipe_change(r8a66597, ep->pipenum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) disable_irq_empty(r8a66597, ep->pipenum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) pipe_start(r8a66597, ep->pipenum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) tmp = r8a66597_read(r8a66597, ep->fifoctr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) if (unlikely((tmp & FRDY) == 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) pipe_irq_enable(r8a66597, ep->pipenum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) irq_packet_write(ep, req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) /* DMA mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) pipe_change(r8a66597, ep->pipenum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) disable_irq_nrdy(r8a66597, ep->pipenum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) pipe_start(r8a66597, ep->pipenum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) enable_irq_nrdy(r8a66597, ep->pipenum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) sudmac_start(r8a66597, ep, req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) static void start_packet_read(struct r8a66597_ep *ep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) struct r8a66597_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) struct r8a66597 *r8a66597 = ep->r8a66597;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) u16 pipenum = ep->pipenum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) if (ep->pipenum == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) r8a66597_mdfy(r8a66597, 0, (ISEL | CURPIPE), CFIFOSEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) r8a66597_write(r8a66597, BCLR, ep->fifoctr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) pipe_start(r8a66597, pipenum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) pipe_irq_enable(r8a66597, pipenum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) pipe_stop(r8a66597, pipenum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) if (ep->pipetre) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) enable_irq_nrdy(r8a66597, pipenum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) r8a66597_write(r8a66597, TRCLR, ep->pipetre);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) r8a66597_write(r8a66597,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) DIV_ROUND_UP(req->req.length, ep->ep.maxpacket),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) ep->pipetrn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) r8a66597_bset(r8a66597, TRENB, ep->pipetre);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) if (sudmac_alloc_channel(r8a66597, ep, req) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) /* PIO mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) change_bfre_mode(r8a66597, ep->pipenum, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) pipe_start(r8a66597, pipenum); /* trigger once */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) pipe_irq_enable(r8a66597, pipenum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) pipe_change(r8a66597, pipenum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) sudmac_start(r8a66597, ep, req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) pipe_start(r8a66597, pipenum); /* trigger once */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) static void start_packet(struct r8a66597_ep *ep, struct r8a66597_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) if (ep->ep.desc->bEndpointAddress & USB_DIR_IN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) start_packet_write(ep, req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) start_packet_read(ep, req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) static void start_ep0(struct r8a66597_ep *ep, struct r8a66597_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) u16 ctsq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) ctsq = r8a66597_read(ep->r8a66597, INTSTS0) & CTSQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) switch (ctsq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) case CS_RDDS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) start_ep0_write(ep, req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) case CS_WRDS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) start_packet_read(ep, req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) case CS_WRND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) control_end(ep->r8a66597, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) dev_err(r8a66597_to_dev(ep->r8a66597),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) "start_ep0: unexpect ctsq(%x)\n", ctsq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) static void init_controller(struct r8a66597 *r8a66597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) u16 vif = r8a66597->pdata->vif ? LDRV : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) u16 irq_sense = r8a66597->irq_sense_low ? INTL : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) u16 endian = r8a66597->pdata->endian ? BIGEND : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) if (r8a66597->pdata->on_chip) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) if (r8a66597->pdata->buswait)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) r8a66597_write(r8a66597, r8a66597->pdata->buswait,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) SYSCFG1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) r8a66597_write(r8a66597, 0x0f, SYSCFG1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) r8a66597_bset(r8a66597, HSE, SYSCFG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) r8a66597_bclr(r8a66597, USBE, SYSCFG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) r8a66597_bclr(r8a66597, DPRPU, SYSCFG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) r8a66597_bset(r8a66597, USBE, SYSCFG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) r8a66597_bset(r8a66597, SCKE, SYSCFG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) r8a66597_bset(r8a66597, irq_sense, INTENB1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) r8a66597_write(r8a66597, BURST | CPU_ADR_RD_WR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) DMA0CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) r8a66597_bset(r8a66597, vif | endian, PINCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) r8a66597_bset(r8a66597, HSE, SYSCFG0); /* High spd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) r8a66597_mdfy(r8a66597, get_xtal_from_pdata(r8a66597->pdata),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) XTAL, SYSCFG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) r8a66597_bclr(r8a66597, USBE, SYSCFG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) r8a66597_bclr(r8a66597, DPRPU, SYSCFG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) r8a66597_bset(r8a66597, USBE, SYSCFG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) r8a66597_bset(r8a66597, XCKE, SYSCFG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) mdelay(3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) r8a66597_bset(r8a66597, PLLC, SYSCFG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) mdelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) r8a66597_bset(r8a66597, SCKE, SYSCFG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) r8a66597_bset(r8a66597, irq_sense, INTENB1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) r8a66597_write(r8a66597, BURST | CPU_ADR_RD_WR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) DMA0CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) static void disable_controller(struct r8a66597 *r8a66597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) if (r8a66597->pdata->on_chip) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) r8a66597_bset(r8a66597, SCKE, SYSCFG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) r8a66597_bclr(r8a66597, UTST, TESTMODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) /* disable interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) r8a66597_write(r8a66597, 0, INTENB0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) r8a66597_write(r8a66597, 0, INTENB1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) r8a66597_write(r8a66597, 0, BRDYENB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) r8a66597_write(r8a66597, 0, BEMPENB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) r8a66597_write(r8a66597, 0, NRDYENB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) /* clear status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) r8a66597_write(r8a66597, 0, BRDYSTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) r8a66597_write(r8a66597, 0, NRDYSTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) r8a66597_write(r8a66597, 0, BEMPSTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) r8a66597_bclr(r8a66597, USBE, SYSCFG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) r8a66597_bclr(r8a66597, SCKE, SYSCFG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) r8a66597_bclr(r8a66597, UTST, TESTMODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) r8a66597_bclr(r8a66597, SCKE, SYSCFG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) r8a66597_bclr(r8a66597, PLLC, SYSCFG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) r8a66597_bclr(r8a66597, XCKE, SYSCFG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) static void r8a66597_start_xclock(struct r8a66597 *r8a66597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) u16 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) if (!r8a66597->pdata->on_chip) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) tmp = r8a66597_read(r8a66597, SYSCFG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) if (!(tmp & XCKE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) r8a66597_bset(r8a66597, XCKE, SYSCFG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) static struct r8a66597_request *get_request_from_ep(struct r8a66597_ep *ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) return list_entry(ep->queue.next, struct r8a66597_request, queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) /*-------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) static void transfer_complete(struct r8a66597_ep *ep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) struct r8a66597_request *req, int status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) __releases(r8a66597->lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) __acquires(r8a66597->lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) int restart = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) if (unlikely(ep->pipenum == 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) if (ep->internal_ccpl) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) ep->internal_ccpl = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) list_del_init(&req->queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) if (ep->r8a66597->gadget.speed == USB_SPEED_UNKNOWN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) req->req.status = -ESHUTDOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) req->req.status = status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) if (!list_empty(&ep->queue))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) restart = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) if (ep->use_dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) sudmac_free_channel(ep->r8a66597, ep, req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) spin_unlock(&ep->r8a66597->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) usb_gadget_giveback_request(&ep->ep, &req->req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) spin_lock(&ep->r8a66597->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) if (restart) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) req = get_request_from_ep(ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) if (ep->ep.desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) start_packet(ep, req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) static void irq_ep0_write(struct r8a66597_ep *ep, struct r8a66597_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) u16 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) unsigned bufsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) size_t size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) void *buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) u16 pipenum = ep->pipenum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) struct r8a66597 *r8a66597 = ep->r8a66597;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) pipe_change(r8a66597, pipenum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) r8a66597_bset(r8a66597, ISEL, ep->fifosel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) tmp = r8a66597_read(r8a66597, ep->fifoctr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) if (i++ > 100000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) dev_err(r8a66597_to_dev(r8a66597),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) "pipe0 is busy. maybe cpu i/o bus "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) "conflict. please power off this controller.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) ndelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) } while ((tmp & FRDY) == 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) /* prepare parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) bufsize = get_buffer_size(r8a66597, pipenum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) buf = req->req.buf + req->req.actual;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) size = min(bufsize, req->req.length - req->req.actual);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) /* write fifo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) if (req->req.buf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) if (size > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) r8a66597_write_fifo(r8a66597, ep, buf, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) if ((size == 0) || ((size % ep->ep.maxpacket) != 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) r8a66597_bset(r8a66597, BVAL, ep->fifoctr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) /* update parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) req->req.actual += size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) /* check transfer finish */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) if ((!req->req.zero && (req->req.actual == req->req.length))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) || (size % ep->ep.maxpacket)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) || (size == 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) disable_irq_ready(r8a66597, pipenum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) disable_irq_empty(r8a66597, pipenum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) disable_irq_ready(r8a66597, pipenum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) enable_irq_empty(r8a66597, pipenum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) pipe_start(r8a66597, pipenum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) static void irq_packet_write(struct r8a66597_ep *ep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) struct r8a66597_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) u16 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) unsigned bufsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) size_t size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) void *buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) u16 pipenum = ep->pipenum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) struct r8a66597 *r8a66597 = ep->r8a66597;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) pipe_change(r8a66597, pipenum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) tmp = r8a66597_read(r8a66597, ep->fifoctr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) if (unlikely((tmp & FRDY) == 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) pipe_stop(r8a66597, pipenum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) pipe_irq_disable(r8a66597, pipenum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) dev_err(r8a66597_to_dev(r8a66597),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) "write fifo not ready. pipnum=%d\n", pipenum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) /* prepare parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) bufsize = get_buffer_size(r8a66597, pipenum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) buf = req->req.buf + req->req.actual;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) size = min(bufsize, req->req.length - req->req.actual);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) /* write fifo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) if (req->req.buf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) r8a66597_write_fifo(r8a66597, ep, buf, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) if ((size == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) || ((size % ep->ep.maxpacket) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) || ((bufsize != ep->ep.maxpacket)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) && (bufsize > size)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) r8a66597_bset(r8a66597, BVAL, ep->fifoctr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) /* update parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) req->req.actual += size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) /* check transfer finish */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) if ((!req->req.zero && (req->req.actual == req->req.length))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) || (size % ep->ep.maxpacket)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) || (size == 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) disable_irq_ready(r8a66597, pipenum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) enable_irq_empty(r8a66597, pipenum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) disable_irq_empty(r8a66597, pipenum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) pipe_irq_enable(r8a66597, pipenum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) static void irq_packet_read(struct r8a66597_ep *ep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) struct r8a66597_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) u16 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) int rcv_len, bufsize, req_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) int size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) void *buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) u16 pipenum = ep->pipenum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) struct r8a66597 *r8a66597 = ep->r8a66597;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) int finish = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) pipe_change(r8a66597, pipenum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) tmp = r8a66597_read(r8a66597, ep->fifoctr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) if (unlikely((tmp & FRDY) == 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) req->req.status = -EPIPE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) pipe_stop(r8a66597, pipenum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) pipe_irq_disable(r8a66597, pipenum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) dev_err(r8a66597_to_dev(r8a66597), "read fifo not ready");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) /* prepare parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) rcv_len = tmp & DTLN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) bufsize = get_buffer_size(r8a66597, pipenum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) buf = req->req.buf + req->req.actual;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) req_len = req->req.length - req->req.actual;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) if (rcv_len < bufsize)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) size = min(rcv_len, req_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) size = min(bufsize, req_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) /* update parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) req->req.actual += size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) /* check transfer finish */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) if ((!req->req.zero && (req->req.actual == req->req.length))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) || (size % ep->ep.maxpacket)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) || (size == 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) pipe_stop(r8a66597, pipenum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) pipe_irq_disable(r8a66597, pipenum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) finish = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) /* read fifo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) if (req->req.buf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) if (size == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) r8a66597_write(r8a66597, BCLR, ep->fifoctr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) r8a66597_read_fifo(r8a66597, ep->fifoaddr, buf, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) if ((ep->pipenum != 0) && finish)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) transfer_complete(ep, req, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) static void irq_pipe_ready(struct r8a66597 *r8a66597, u16 status, u16 enb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) u16 check;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) u16 pipenum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) struct r8a66597_ep *ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) struct r8a66597_request *req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) if ((status & BRDY0) && (enb & BRDY0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) r8a66597_write(r8a66597, ~BRDY0, BRDYSTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) r8a66597_mdfy(r8a66597, 0, CURPIPE, CFIFOSEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) ep = &r8a66597->ep[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) req = get_request_from_ep(ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) irq_packet_read(ep, req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) for (pipenum = 1; pipenum < R8A66597_MAX_NUM_PIPE; pipenum++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) check = 1 << pipenum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) if ((status & check) && (enb & check)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) r8a66597_write(r8a66597, ~check, BRDYSTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) ep = r8a66597->pipenum2ep[pipenum];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) req = get_request_from_ep(ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) if (ep->ep.desc->bEndpointAddress & USB_DIR_IN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) irq_packet_write(ep, req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) irq_packet_read(ep, req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) static void irq_pipe_empty(struct r8a66597 *r8a66597, u16 status, u16 enb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) u16 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) u16 check;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) u16 pipenum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) struct r8a66597_ep *ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) struct r8a66597_request *req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) if ((status & BEMP0) && (enb & BEMP0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) r8a66597_write(r8a66597, ~BEMP0, BEMPSTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) ep = &r8a66597->ep[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) req = get_request_from_ep(ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) irq_ep0_write(ep, req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) for (pipenum = 1; pipenum < R8A66597_MAX_NUM_PIPE; pipenum++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) check = 1 << pipenum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) if ((status & check) && (enb & check)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) r8a66597_write(r8a66597, ~check, BEMPSTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) tmp = control_reg_get(r8a66597, pipenum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) if ((tmp & INBUFM) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) disable_irq_empty(r8a66597, pipenum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) pipe_irq_disable(r8a66597, pipenum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) pipe_stop(r8a66597, pipenum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) ep = r8a66597->pipenum2ep[pipenum];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) req = get_request_from_ep(ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) if (!list_empty(&ep->queue))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) transfer_complete(ep, req, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) static void get_status(struct r8a66597 *r8a66597, struct usb_ctrlrequest *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) __releases(r8a66597->lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) __acquires(r8a66597->lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) struct r8a66597_ep *ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) u16 pid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) u16 status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) u16 w_index = le16_to_cpu(ctrl->wIndex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) switch (ctrl->bRequestType & USB_RECIP_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) case USB_RECIP_DEVICE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) status = r8a66597->device_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) case USB_RECIP_INTERFACE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) case USB_RECIP_ENDPOINT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) ep = r8a66597->epaddr2ep[w_index & USB_ENDPOINT_NUMBER_MASK];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) pid = control_reg_get_pid(r8a66597, ep->pipenum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) if (pid == PID_STALL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) status = 1 << USB_ENDPOINT_HALT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) pipe_stall(r8a66597, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) return; /* exit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) r8a66597->ep0_data = cpu_to_le16(status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) r8a66597->ep0_req->buf = &r8a66597->ep0_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) r8a66597->ep0_req->length = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) /* AV: what happens if we get called again before that gets through? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) spin_unlock(&r8a66597->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) r8a66597_queue(r8a66597->gadget.ep0, r8a66597->ep0_req, GFP_ATOMIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) spin_lock(&r8a66597->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) static void clear_feature(struct r8a66597 *r8a66597,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) struct usb_ctrlrequest *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) switch (ctrl->bRequestType & USB_RECIP_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) case USB_RECIP_DEVICE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) control_end(r8a66597, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) case USB_RECIP_INTERFACE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) control_end(r8a66597, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) case USB_RECIP_ENDPOINT: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) struct r8a66597_ep *ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) struct r8a66597_request *req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) u16 w_index = le16_to_cpu(ctrl->wIndex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) ep = r8a66597->epaddr2ep[w_index & USB_ENDPOINT_NUMBER_MASK];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) if (!ep->wedge) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) pipe_stop(r8a66597, ep->pipenum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) control_reg_sqclr(r8a66597, ep->pipenum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) spin_unlock(&r8a66597->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) usb_ep_clear_halt(&ep->ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) spin_lock(&r8a66597->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) control_end(r8a66597, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) req = get_request_from_ep(ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) if (ep->busy) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) ep->busy = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) if (list_empty(&ep->queue))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) start_packet(ep, req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) } else if (!list_empty(&ep->queue))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) pipe_start(r8a66597, ep->pipenum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) pipe_stall(r8a66597, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) static void set_feature(struct r8a66597 *r8a66597, struct usb_ctrlrequest *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) u16 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) int timeout = 3000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) switch (ctrl->bRequestType & USB_RECIP_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) case USB_RECIP_DEVICE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) switch (le16_to_cpu(ctrl->wValue)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) case USB_DEVICE_TEST_MODE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) control_end(r8a66597, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) /* Wait for the completion of status stage */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) tmp = r8a66597_read(r8a66597, INTSTS0) & CTSQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) } while (tmp != CS_IDST && timeout-- > 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) if (tmp == CS_IDST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) r8a66597_bset(r8a66597,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) le16_to_cpu(ctrl->wIndex >> 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) TESTMODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) pipe_stall(r8a66597, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) case USB_RECIP_INTERFACE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) control_end(r8a66597, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) case USB_RECIP_ENDPOINT: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) struct r8a66597_ep *ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) u16 w_index = le16_to_cpu(ctrl->wIndex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) ep = r8a66597->epaddr2ep[w_index & USB_ENDPOINT_NUMBER_MASK];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) pipe_stall(r8a66597, ep->pipenum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) control_end(r8a66597, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) pipe_stall(r8a66597, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) /* if return value is true, call class driver's setup() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) static int setup_packet(struct r8a66597 *r8a66597, struct usb_ctrlrequest *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) u16 *p = (u16 *)ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) unsigned long offset = USBREQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) int i, ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) /* read fifo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) r8a66597_write(r8a66597, ~VALID, INTSTS0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) for (i = 0; i < 4; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) p[i] = r8a66597_read(r8a66597, offset + i*2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) /* check request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) switch (ctrl->bRequest) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) case USB_REQ_GET_STATUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) get_status(r8a66597, ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) case USB_REQ_CLEAR_FEATURE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) clear_feature(r8a66597, ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) case USB_REQ_SET_FEATURE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) set_feature(r8a66597, ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) ret = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) ret = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) static void r8a66597_update_usb_speed(struct r8a66597 *r8a66597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) u16 speed = get_usb_speed(r8a66597);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) switch (speed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) case HSMODE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) r8a66597->gadget.speed = USB_SPEED_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) case FSMODE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) r8a66597->gadget.speed = USB_SPEED_FULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) r8a66597->gadget.speed = USB_SPEED_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) dev_err(r8a66597_to_dev(r8a66597), "USB speed unknown\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) static void irq_device_state(struct r8a66597 *r8a66597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) u16 dvsq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) dvsq = r8a66597_read(r8a66597, INTSTS0) & DVSQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) r8a66597_write(r8a66597, ~DVST, INTSTS0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) if (dvsq == DS_DFLT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) /* bus reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) spin_unlock(&r8a66597->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) usb_gadget_udc_reset(&r8a66597->gadget, r8a66597->driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) spin_lock(&r8a66597->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) r8a66597_update_usb_speed(r8a66597);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) if (r8a66597->old_dvsq == DS_CNFG && dvsq != DS_CNFG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) r8a66597_update_usb_speed(r8a66597);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) if ((dvsq == DS_CNFG || dvsq == DS_ADDS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) && r8a66597->gadget.speed == USB_SPEED_UNKNOWN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) r8a66597_update_usb_speed(r8a66597);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) r8a66597->old_dvsq = dvsq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) static void irq_control_stage(struct r8a66597 *r8a66597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) __releases(r8a66597->lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) __acquires(r8a66597->lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) struct usb_ctrlrequest ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) u16 ctsq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) ctsq = r8a66597_read(r8a66597, INTSTS0) & CTSQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) r8a66597_write(r8a66597, ~CTRT, INTSTS0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) switch (ctsq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) case CS_IDST: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) struct r8a66597_ep *ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) struct r8a66597_request *req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) ep = &r8a66597->ep[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) req = get_request_from_ep(ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) transfer_complete(ep, req, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) case CS_RDDS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) case CS_WRDS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) case CS_WRND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) if (setup_packet(r8a66597, &ctrl)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) spin_unlock(&r8a66597->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) if (r8a66597->driver->setup(&r8a66597->gadget, &ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) pipe_stall(r8a66597, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) spin_lock(&r8a66597->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) case CS_RDSS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) case CS_WRSS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) control_end(r8a66597, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) dev_err(r8a66597_to_dev(r8a66597),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) "ctrl_stage: unexpect ctsq(%x)\n", ctsq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) static void sudmac_finish(struct r8a66597 *r8a66597, struct r8a66597_ep *ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) u16 pipenum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) struct r8a66597_request *req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) u32 len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) pipenum = ep->pipenum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) pipe_change(r8a66597, pipenum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) while (!(r8a66597_read(r8a66597, ep->fifoctr) & FRDY)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) if (unlikely(i++ >= 10000)) { /* timeout = 10 msec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) dev_err(r8a66597_to_dev(r8a66597),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) "%s: FRDY was not set (%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) __func__, pipenum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) r8a66597_bset(r8a66597, BCLR, ep->fifoctr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) req = get_request_from_ep(ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) /* prepare parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) len = r8a66597_sudmac_read(r8a66597, CH0CBC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) req->req.actual += len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) /* clear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) r8a66597_sudmac_write(r8a66597, CH0STCLR, DSTSCLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) /* check transfer finish */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) if ((!req->req.zero && (req->req.actual == req->req.length))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) || (len % ep->ep.maxpacket)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) if (ep->dma->dir) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) disable_irq_ready(r8a66597, pipenum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) enable_irq_empty(r8a66597, pipenum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) /* Clear the interrupt flag for next transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) r8a66597_write(r8a66597, ~(1 << pipenum), BRDYSTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) transfer_complete(ep, req, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) static void r8a66597_sudmac_irq(struct r8a66597 *r8a66597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) u32 irqsts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) struct r8a66597_ep *ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) u16 pipenum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) irqsts = r8a66597_sudmac_read(r8a66597, DINTSTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) if (irqsts & CH0ENDS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) r8a66597_sudmac_write(r8a66597, CH0ENDC, DINTSTSCLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) pipenum = (r8a66597_read(r8a66597, D0FIFOSEL) & CURPIPE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) ep = r8a66597->pipenum2ep[pipenum];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) sudmac_finish(r8a66597, ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) static irqreturn_t r8a66597_irq(int irq, void *_r8a66597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) struct r8a66597 *r8a66597 = _r8a66597;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) u16 intsts0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) u16 intenb0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) u16 savepipe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) u16 mask0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) spin_lock(&r8a66597->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) if (r8a66597_is_sudmac(r8a66597))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) r8a66597_sudmac_irq(r8a66597);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) intsts0 = r8a66597_read(r8a66597, INTSTS0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) intenb0 = r8a66597_read(r8a66597, INTENB0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) savepipe = r8a66597_read(r8a66597, CFIFOSEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) mask0 = intsts0 & intenb0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) if (mask0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) u16 brdysts = r8a66597_read(r8a66597, BRDYSTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) u16 bempsts = r8a66597_read(r8a66597, BEMPSTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) u16 brdyenb = r8a66597_read(r8a66597, BRDYENB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) u16 bempenb = r8a66597_read(r8a66597, BEMPENB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) if (mask0 & VBINT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) r8a66597_write(r8a66597, 0xffff & ~VBINT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) INTSTS0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) r8a66597_start_xclock(r8a66597);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) /* start vbus sampling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) r8a66597->old_vbus = r8a66597_read(r8a66597, INTSTS0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) & VBSTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) r8a66597->scount = R8A66597_MAX_SAMPLING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) mod_timer(&r8a66597->timer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) jiffies + msecs_to_jiffies(50));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) if (intsts0 & DVSQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) irq_device_state(r8a66597);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) if ((intsts0 & BRDY) && (intenb0 & BRDYE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) && (brdysts & brdyenb))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) irq_pipe_ready(r8a66597, brdysts, brdyenb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) if ((intsts0 & BEMP) && (intenb0 & BEMPE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) && (bempsts & bempenb))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) irq_pipe_empty(r8a66597, bempsts, bempenb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) if (intsts0 & CTRT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) irq_control_stage(r8a66597);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) r8a66597_write(r8a66597, savepipe, CFIFOSEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) spin_unlock(&r8a66597->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) static void r8a66597_timer(struct timer_list *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) struct r8a66597 *r8a66597 = from_timer(r8a66597, t, timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) u16 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) spin_lock_irqsave(&r8a66597->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) tmp = r8a66597_read(r8a66597, SYSCFG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) if (r8a66597->scount > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) tmp = r8a66597_read(r8a66597, INTSTS0) & VBSTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) if (tmp == r8a66597->old_vbus) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) r8a66597->scount--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) if (r8a66597->scount == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) if (tmp == VBSTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) r8a66597_usb_connect(r8a66597);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) r8a66597_usb_disconnect(r8a66597);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) mod_timer(&r8a66597->timer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) jiffies + msecs_to_jiffies(50));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) r8a66597->scount = R8A66597_MAX_SAMPLING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) r8a66597->old_vbus = tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) mod_timer(&r8a66597->timer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) jiffies + msecs_to_jiffies(50));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) spin_unlock_irqrestore(&r8a66597->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) /*-------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) static int r8a66597_enable(struct usb_ep *_ep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) const struct usb_endpoint_descriptor *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) struct r8a66597_ep *ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) ep = container_of(_ep, struct r8a66597_ep, ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) return alloc_pipe_config(ep, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) static int r8a66597_disable(struct usb_ep *_ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) struct r8a66597_ep *ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) struct r8a66597_request *req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) ep = container_of(_ep, struct r8a66597_ep, ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) BUG_ON(!ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) while (!list_empty(&ep->queue)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) req = get_request_from_ep(ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) spin_lock_irqsave(&ep->r8a66597->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) transfer_complete(ep, req, -ECONNRESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) spin_unlock_irqrestore(&ep->r8a66597->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) pipe_irq_disable(ep->r8a66597, ep->pipenum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) return free_pipe_config(ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) static struct usb_request *r8a66597_alloc_request(struct usb_ep *_ep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) gfp_t gfp_flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) struct r8a66597_request *req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) req = kzalloc(sizeof(struct r8a66597_request), gfp_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) if (!req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) INIT_LIST_HEAD(&req->queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) return &req->req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) static void r8a66597_free_request(struct usb_ep *_ep, struct usb_request *_req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) struct r8a66597_request *req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) req = container_of(_req, struct r8a66597_request, req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) kfree(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) static int r8a66597_queue(struct usb_ep *_ep, struct usb_request *_req,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) gfp_t gfp_flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) struct r8a66597_ep *ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) struct r8a66597_request *req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) int request = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) ep = container_of(_ep, struct r8a66597_ep, ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) req = container_of(_req, struct r8a66597_request, req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) if (ep->r8a66597->gadget.speed == USB_SPEED_UNKNOWN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) return -ESHUTDOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) spin_lock_irqsave(&ep->r8a66597->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) if (list_empty(&ep->queue))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) request = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) list_add_tail(&req->queue, &ep->queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) req->req.actual = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) req->req.status = -EINPROGRESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) if (ep->ep.desc == NULL) /* control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) start_ep0(ep, req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) if (request && !ep->busy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) start_packet(ep, req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) spin_unlock_irqrestore(&ep->r8a66597->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) static int r8a66597_dequeue(struct usb_ep *_ep, struct usb_request *_req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) struct r8a66597_ep *ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) struct r8a66597_request *req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) ep = container_of(_ep, struct r8a66597_ep, ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) req = container_of(_req, struct r8a66597_request, req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) spin_lock_irqsave(&ep->r8a66597->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) if (!list_empty(&ep->queue))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) transfer_complete(ep, req, -ECONNRESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) spin_unlock_irqrestore(&ep->r8a66597->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) static int r8a66597_set_halt(struct usb_ep *_ep, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) struct r8a66597_ep *ep = container_of(_ep, struct r8a66597_ep, ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) spin_lock_irqsave(&ep->r8a66597->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) if (!list_empty(&ep->queue)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) ret = -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) } else if (value) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) ep->busy = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) pipe_stall(ep->r8a66597, ep->pipenum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) ep->busy = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) ep->wedge = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) pipe_stop(ep->r8a66597, ep->pipenum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) spin_unlock_irqrestore(&ep->r8a66597->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) static int r8a66597_set_wedge(struct usb_ep *_ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) struct r8a66597_ep *ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) ep = container_of(_ep, struct r8a66597_ep, ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) if (!ep || !ep->ep.desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) spin_lock_irqsave(&ep->r8a66597->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) ep->wedge = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) spin_unlock_irqrestore(&ep->r8a66597->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) return usb_ep_set_halt(_ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) static void r8a66597_fifo_flush(struct usb_ep *_ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) struct r8a66597_ep *ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) ep = container_of(_ep, struct r8a66597_ep, ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) spin_lock_irqsave(&ep->r8a66597->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) if (list_empty(&ep->queue) && !ep->busy) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) pipe_stop(ep->r8a66597, ep->pipenum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) r8a66597_bclr(ep->r8a66597, BCLR, ep->fifoctr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) r8a66597_write(ep->r8a66597, ACLRM, ep->pipectr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) r8a66597_write(ep->r8a66597, 0, ep->pipectr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) spin_unlock_irqrestore(&ep->r8a66597->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) static const struct usb_ep_ops r8a66597_ep_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) .enable = r8a66597_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) .disable = r8a66597_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) .alloc_request = r8a66597_alloc_request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) .free_request = r8a66597_free_request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) .queue = r8a66597_queue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) .dequeue = r8a66597_dequeue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) .set_halt = r8a66597_set_halt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) .set_wedge = r8a66597_set_wedge,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) .fifo_flush = r8a66597_fifo_flush,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) /*-------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) static int r8a66597_start(struct usb_gadget *gadget,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) struct usb_gadget_driver *driver)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) struct r8a66597 *r8a66597 = gadget_to_r8a66597(gadget);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) if (!driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) || driver->max_speed < USB_SPEED_HIGH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) || !driver->setup)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) if (!r8a66597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) /* hook up the driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) r8a66597->driver = driver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) init_controller(r8a66597);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) r8a66597_bset(r8a66597, VBSE, INTENB0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) if (r8a66597_read(r8a66597, INTSTS0) & VBSTS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) r8a66597_start_xclock(r8a66597);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) /* start vbus sampling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) r8a66597->old_vbus = r8a66597_read(r8a66597,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) INTSTS0) & VBSTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) r8a66597->scount = R8A66597_MAX_SAMPLING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) mod_timer(&r8a66597->timer, jiffies + msecs_to_jiffies(50));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) static int r8a66597_stop(struct usb_gadget *gadget)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) struct r8a66597 *r8a66597 = gadget_to_r8a66597(gadget);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) spin_lock_irqsave(&r8a66597->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) r8a66597_bclr(r8a66597, VBSE, INTENB0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) disable_controller(r8a66597);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) spin_unlock_irqrestore(&r8a66597->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) r8a66597->driver = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) /*-------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) static int r8a66597_get_frame(struct usb_gadget *_gadget)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) struct r8a66597 *r8a66597 = gadget_to_r8a66597(_gadget);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) return r8a66597_read(r8a66597, FRMNUM) & 0x03FF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) static int r8a66597_pullup(struct usb_gadget *gadget, int is_on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) struct r8a66597 *r8a66597 = gadget_to_r8a66597(gadget);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) spin_lock_irqsave(&r8a66597->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) if (is_on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) r8a66597_bset(r8a66597, DPRPU, SYSCFG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) r8a66597_bclr(r8a66597, DPRPU, SYSCFG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) spin_unlock_irqrestore(&r8a66597->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) static int r8a66597_set_selfpowered(struct usb_gadget *gadget, int is_self)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) struct r8a66597 *r8a66597 = gadget_to_r8a66597(gadget);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) gadget->is_selfpowered = (is_self != 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) if (is_self)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) r8a66597->device_status |= 1 << USB_DEVICE_SELF_POWERED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) r8a66597->device_status &= ~(1 << USB_DEVICE_SELF_POWERED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) static const struct usb_gadget_ops r8a66597_gadget_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) .get_frame = r8a66597_get_frame,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) .udc_start = r8a66597_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) .udc_stop = r8a66597_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) .pullup = r8a66597_pullup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) .set_selfpowered = r8a66597_set_selfpowered,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) static int r8a66597_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) struct r8a66597 *r8a66597 = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) usb_del_gadget_udc(&r8a66597->gadget);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) del_timer_sync(&r8a66597->timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) r8a66597_free_request(&r8a66597->ep[0].ep, r8a66597->ep0_req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) if (r8a66597->pdata->on_chip) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) clk_disable_unprepare(r8a66597->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) static void nop_completion(struct usb_ep *ep, struct usb_request *r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) static int r8a66597_sudmac_ioremap(struct r8a66597 *r8a66597,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) r8a66597->sudmac_reg =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) devm_platform_ioremap_resource_byname(pdev, "sudmac");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) return PTR_ERR_OR_ZERO(r8a66597->sudmac_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) static int r8a66597_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) char clk_name[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) struct resource *ires;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) void __iomem *reg = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) struct r8a66597 *r8a66597 = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) unsigned long irq_trigger;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) reg = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) if (IS_ERR(reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) return PTR_ERR(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) ires = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) if (!ires)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) irq = ires->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) irq_trigger = ires->flags & IRQF_TRIGGER_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) if (irq < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) dev_err(dev, "platform_get_irq error.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) /* initialize ucd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) r8a66597 = devm_kzalloc(dev, sizeof(struct r8a66597), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) if (r8a66597 == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) spin_lock_init(&r8a66597->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) platform_set_drvdata(pdev, r8a66597);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) r8a66597->pdata = dev_get_platdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) r8a66597->irq_sense_low = irq_trigger == IRQF_TRIGGER_LOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) r8a66597->gadget.ops = &r8a66597_gadget_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) r8a66597->gadget.max_speed = USB_SPEED_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) r8a66597->gadget.name = udc_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) timer_setup(&r8a66597->timer, r8a66597_timer, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) r8a66597->reg = reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) if (r8a66597->pdata->on_chip) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) snprintf(clk_name, sizeof(clk_name), "usb%d", pdev->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) r8a66597->clk = devm_clk_get(dev, clk_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) if (IS_ERR(r8a66597->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) dev_err(dev, "cannot get clock \"%s\"\n", clk_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) return PTR_ERR(r8a66597->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) clk_prepare_enable(r8a66597->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) if (r8a66597->pdata->sudmac) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) ret = r8a66597_sudmac_ioremap(r8a66597, pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) goto clean_up2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) disable_controller(r8a66597); /* make sure controller is disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) ret = devm_request_irq(dev, irq, r8a66597_irq, IRQF_SHARED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) udc_name, r8a66597);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) dev_err(dev, "request_irq error (%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) goto clean_up2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) INIT_LIST_HEAD(&r8a66597->gadget.ep_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) r8a66597->gadget.ep0 = &r8a66597->ep[0].ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) INIT_LIST_HEAD(&r8a66597->gadget.ep0->ep_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) for (i = 0; i < R8A66597_MAX_NUM_PIPE; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) struct r8a66597_ep *ep = &r8a66597->ep[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) if (i != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) INIT_LIST_HEAD(&r8a66597->ep[i].ep.ep_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) list_add_tail(&r8a66597->ep[i].ep.ep_list,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) &r8a66597->gadget.ep_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) ep->r8a66597 = r8a66597;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) INIT_LIST_HEAD(&ep->queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) ep->ep.name = r8a66597_ep_name[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) ep->ep.ops = &r8a66597_ep_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) usb_ep_set_maxpacket_limit(&ep->ep, 512);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) if (i == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) ep->ep.caps.type_control = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) ep->ep.caps.type_iso = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) ep->ep.caps.type_bulk = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) ep->ep.caps.type_int = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) ep->ep.caps.dir_in = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) ep->ep.caps.dir_out = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) usb_ep_set_maxpacket_limit(&r8a66597->ep[0].ep, 64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) r8a66597->ep[0].pipenum = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) r8a66597->ep[0].fifoaddr = CFIFO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) r8a66597->ep[0].fifosel = CFIFOSEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) r8a66597->ep[0].fifoctr = CFIFOCTR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) r8a66597->ep[0].pipectr = get_pipectr_addr(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) r8a66597->pipenum2ep[0] = &r8a66597->ep[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) r8a66597->epaddr2ep[0] = &r8a66597->ep[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) r8a66597->ep0_req = r8a66597_alloc_request(&r8a66597->ep[0].ep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) if (r8a66597->ep0_req == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) goto clean_up2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) r8a66597->ep0_req->complete = nop_completion;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) ret = usb_add_gadget_udc(dev, &r8a66597->gadget);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) goto err_add_udc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) dev_info(dev, "version %s\n", DRIVER_VERSION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) err_add_udc:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) r8a66597_free_request(&r8a66597->ep[0].ep, r8a66597->ep0_req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) clean_up2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) if (r8a66597->pdata->on_chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) clk_disable_unprepare(r8a66597->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) if (r8a66597->ep0_req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) r8a66597_free_request(&r8a66597->ep[0].ep, r8a66597->ep0_req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) /*-------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) static struct platform_driver r8a66597_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) .remove = r8a66597_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) .name = udc_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) module_platform_driver_probe(r8a66597_driver, r8a66597_probe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) MODULE_DESCRIPTION("R8A66597 USB gadget driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) MODULE_AUTHOR("Yoshihiro Shimoda");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) MODULE_ALIAS("platform:r8a66597_udc");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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