Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * NetChip 2280 high/full speed USB device controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Unlike many such controllers, this one talks PCI.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * Copyright (C) 2002 NetChip Technology, Inc. (http://www.netchip.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * Copyright (C) 2003 David Brownell
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  * Copyright (C) 2014 Ricardo Ribalda - Qtechnology/AS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/usb/net2280.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/usb/usb338x.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) /*-------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #ifdef	__KERNEL__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) /* indexed registers [11.10] are accessed indirectly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21)  * caller must own the device lock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) static inline u32 get_idx_reg(struct net2280_regs __iomem *regs, u32 index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	writel(index, &regs->idxaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	/* NOTE:  synchs device/cpu memory views */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	return readl(&regs->idxdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) set_idx_reg(struct net2280_regs __iomem *regs, u32 index, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	writel(index, &regs->idxaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	writel(value, &regs->idxdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	/* posted, may not be visible yet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #endif	/* __KERNEL__ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define PCI_VENDOR_ID_PLX_LEGACY 0x17cc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define PLX_LEGACY		BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define PLX_2280		BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define PLX_SUPERSPEED		BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define PLX_PCIE		BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define REG_DIAG		0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define     RETRY_COUNTER                                       16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define     FORCE_PCI_SERR                                      11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define     FORCE_PCI_INTERRUPT                                 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define     FORCE_USB_INTERRUPT                                 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define     FORCE_CPU_INTERRUPT                                 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define     ILLEGAL_BYTE_ENABLES                                5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define     FAST_TIMES                                          4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define     FORCE_RECEIVE_ERROR                                 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define     FORCE_TRANSMIT_CRC_ERROR                            0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define REG_FRAME		0x02	/* from last sof */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define REG_CHIPREV		0x03	/* in bcd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define	REG_HS_NAK_RATE		0x0a	/* NAK per N uframes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define	CHIPREV_1	0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define	CHIPREV_1A	0x0110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) /* DEFECT 7374 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define DEFECT_7374_NUMBEROF_MAX_WAIT_LOOPS         200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define DEFECT_7374_PROCESSOR_WAIT_TIME             10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) /* ep0 max packet size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define EP0_SS_MAX_PACKET_SIZE  0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define EP0_HS_MAX_PACKET_SIZE  0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #ifdef	__KERNEL__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) /*-------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) /* [8.3] for scatter/gather i/o
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77)  * use struct net2280_dma_regs bitfields
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) struct net2280_dma {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	__le32		dmacount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	__le32		dmaaddr;		/* the buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	__le32		dmadesc;		/* next dma descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	__le32		_reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) } __aligned(16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) /*-------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) /* DRIVER DATA STRUCTURES and UTILITIES */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) struct net2280_ep {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	struct usb_ep				ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	struct net2280_ep_regs __iomem *cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	struct net2280_ep_regs			__iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	struct net2280_dma_regs			__iomem *dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	struct net2280_dma			*dummy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	dma_addr_t				td_dma;	/* of dummy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	struct net2280				*dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	unsigned long				irqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	/* analogous to a host-side qh */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	struct list_head			queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	const struct usb_endpoint_descriptor	*desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	unsigned				num : 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 						fifo_size : 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 						in_fifo_validate : 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 						out_overflow : 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 						stopped : 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 						wedged : 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 						is_in : 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 						is_iso : 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 						responded : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static inline void allow_status(struct net2280_ep *ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	/* ep0 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	writel(BIT(CLEAR_CONTROL_STATUS_PHASE_HANDSHAKE) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 		BIT(CLEAR_NAK_OUT_PACKETS) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 		BIT(CLEAR_NAK_OUT_PACKETS_MODE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 		&ep->regs->ep_rsp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	ep->stopped = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static inline void allow_status_338x(struct net2280_ep *ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	 * Control Status Phase Handshake was set by the chip when the setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	 * packet arrived. While set, the chip automatically NAKs the host's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	 * Status Phase tokens.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	writel(BIT(CLEAR_CONTROL_STATUS_PHASE_HANDSHAKE), &ep->regs->ep_rsp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	ep->stopped = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	/* TD 9.9 Halt Endpoint test.  TD 9.22 set feature test. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	ep->responded = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) struct net2280_request {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	struct usb_request		req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	struct net2280_dma		*td;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	dma_addr_t			td_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	struct list_head		queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	unsigned			mapped : 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 					valid : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) struct net2280 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	/* each pci device provides one gadget, several endpoints */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	struct usb_gadget		gadget;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	spinlock_t			lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	struct net2280_ep		ep[9];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	struct usb_gadget_driver	*driver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	unsigned			enabled : 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 					protocol_stall : 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 					softconnect : 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 					got_irq : 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 					region:1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 					added:1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 					u1_enable:1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 					u2_enable:1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 					ltm_enable:1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 					wakeup_enable:1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 					addressed_state:1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 					bug7734_patched:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	u16				chiprev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	int enhanced_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	int n_ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	kernel_ulong_t			quirks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	/* pci state used to access those endpoints */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	struct pci_dev			*pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	struct net2280_regs		__iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	struct net2280_usb_regs		__iomem *usb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	struct usb338x_usb_ext_regs	__iomem *usb_ext;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	struct net2280_pci_regs		__iomem *pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	struct net2280_dma_regs		__iomem *dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	struct net2280_dep_regs		__iomem *dep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	struct net2280_ep_regs		__iomem *epregs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	struct usb338x_ll_regs		__iomem *llregs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	struct usb338x_pl_regs		__iomem *plregs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	struct dma_pool			*requests;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	/* statistics...*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static inline void set_halt(struct net2280_ep *ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	/* ep0 and bulk/intr endpoints */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	writel(BIT(CLEAR_CONTROL_STATUS_PHASE_HANDSHAKE) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 		/* set NAK_OUT for erratum 0114 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 		((ep->dev->chiprev == CHIPREV_1) << SET_NAK_OUT_PACKETS) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 		BIT(SET_ENDPOINT_HALT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 		&ep->regs->ep_rsp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) static inline void clear_halt(struct net2280_ep *ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	/* ep0 and bulk/intr endpoints */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	writel(BIT(CLEAR_ENDPOINT_HALT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 		BIT(CLEAR_ENDPOINT_TOGGLE) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 		    /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 		     * unless the gadget driver left a short packet in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 		     * fifo, this reverses the erratum 0114 workaround.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 		     */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 		((ep->dev->chiprev == CHIPREV_1) << CLEAR_NAK_OUT_PACKETS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 		&ep->regs->ep_rsp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)  * FSM value for Defect 7374 (U1U2 Test) is managed in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)  * chip's SCRATCH register:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define DEFECT7374_FSM_FIELD    28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /* Waiting for Control Read:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)  *  - A transition to this state indicates a fresh USB connection,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)  *    before the first Setup Packet. The connection speed is not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)  *    known. Firmware is waiting for the first Control Read.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)  *  - Starting state: This state can be thought of as the FSM's typical
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)  *    starting state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)  *  - Tip: Upon the first SS Control Read the FSM never
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)  *    returns to this state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define DEFECT7374_FSM_WAITING_FOR_CONTROL_READ BIT(DEFECT7374_FSM_FIELD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) /* Non-SS Control Read:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)  *  - A transition to this state indicates detection of the first HS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)  *    or FS Control Read.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)  *  - Tip: Upon the first SS Control Read the FSM never
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)  *    returns to this state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define	DEFECT7374_FSM_NON_SS_CONTROL_READ (2 << DEFECT7374_FSM_FIELD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) /* SS Control Read:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)  *  - A transition to this state indicates detection of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)  *    first SS Control Read.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)  *  - This state indicates workaround completion. Workarounds no longer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)  *    need to be applied (as long as the chip remains powered up).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)  *  - Tip: Once in this state the FSM state does not change (until
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)  *    the chip's power is lost and restored).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)  *  - This can be thought of as the final state of the FSM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)  *    the FSM 'locks-up' in this state until the chip loses power.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define DEFECT7374_FSM_SS_CONTROL_READ (3 << DEFECT7374_FSM_FIELD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #ifdef USE_RDK_LEDS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) static inline void net2280_led_init(struct net2280 *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	/* LED3 (green) is on during USB activity. note erratum 0113. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	writel(BIT(GPIO3_LED_SELECT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 		BIT(GPIO3_OUTPUT_ENABLE) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 		BIT(GPIO2_OUTPUT_ENABLE) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 		BIT(GPIO1_OUTPUT_ENABLE) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 		BIT(GPIO0_OUTPUT_ENABLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 		&dev->regs->gpioctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) /* indicate speed with bi-color LED 0/1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) static inline
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) void net2280_led_speed(struct net2280 *dev, enum usb_device_speed speed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	u32	val = readl(&dev->regs->gpioctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	switch (speed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	case USB_SPEED_SUPER:		/* green + red */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 		val |= BIT(GPIO0_DATA) | BIT(GPIO1_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	case USB_SPEED_HIGH:		/* green */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 		val &= ~BIT(GPIO0_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 		val |= BIT(GPIO1_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	case USB_SPEED_FULL:		/* red */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 		val &= ~BIT(GPIO1_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 		val |= BIT(GPIO0_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	default:			/* (off/black) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 		val &= ~(BIT(GPIO1_DATA) | BIT(GPIO0_DATA));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	writel(val, &dev->regs->gpioctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) /* indicate power with LED 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) static inline void net2280_led_active(struct net2280 *dev, int is_active)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	u32	val = readl(&dev->regs->gpioctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	/* FIXME this LED never seems to turn on.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	if (is_active)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 		val |= GPIO2_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 		val &= ~GPIO2_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	writel(val, &dev->regs->gpioctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) static inline void net2280_led_shutdown(struct net2280 *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	/* turn off all four GPIO*_DATA bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	writel(readl(&dev->regs->gpioctl) & ~0x0f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 			&dev->regs->gpioctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define net2280_led_init(dev)		do { } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define net2280_led_speed(dev, speed)	do { } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define net2280_led_shutdown(dev)	do { } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) /*-------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define ep_dbg(ndev, fmt, args...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	dev_dbg((&((ndev)->pdev->dev)), fmt, ##args)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define ep_vdbg(ndev, fmt, args...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	dev_vdbg((&((ndev)->pdev->dev)), fmt, ##args)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define ep_info(ndev, fmt, args...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	dev_info((&((ndev)->pdev->dev)), fmt, ##args)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define ep_warn(ndev, fmt, args...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	dev_warn((&((ndev)->pdev->dev)), fmt, ##args)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define ep_err(ndev, fmt, args...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	dev_err((&((ndev)->pdev->dev)), fmt, ##args)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) /*-------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) static inline void set_fifo_bytecount(struct net2280_ep *ep, unsigned count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	if (ep->dev->pdev->vendor == 0x17cc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 		writeb(count, 2 + (u8 __iomem *) &ep->regs->ep_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	else{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 		u32 tmp = readl(&ep->cfg->ep_cfg) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 					(~(0x07 << EP_FIFO_BYTE_COUNT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 		writel(tmp | (count << EP_FIFO_BYTE_COUNT), &ep->cfg->ep_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) static inline void start_out_naking(struct net2280_ep *ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	/* NOTE:  hardware races lurk here, and PING protocol issues */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	writel(BIT(SET_NAK_OUT_PACKETS), &ep->regs->ep_rsp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	/* synch with device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	readl(&ep->regs->ep_rsp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) static inline void stop_out_naking(struct net2280_ep *ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	u32	tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	tmp = readl(&ep->regs->ep_stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	if ((tmp & BIT(NAK_OUT_PACKETS)) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 		writel(BIT(CLEAR_NAK_OUT_PACKETS), &ep->regs->ep_rsp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) static inline void set_max_speed(struct net2280_ep *ep, u32 max)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 	static const u32 ep_enhanced[9] = { 0x10, 0x60, 0x30, 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 					  0x50, 0x20, 0x70, 0x40, 0x90 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 	if (ep->dev->enhanced_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 		reg = ep_enhanced[ep->num];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 		switch (ep->dev->gadget.speed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 		case USB_SPEED_SUPER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 			reg += 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 		case USB_SPEED_FULL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 			reg += 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 		case USB_SPEED_HIGH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 		default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 		reg = (ep->num + 1) * 0x10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 		if (ep->dev->gadget.speed != USB_SPEED_HIGH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 			reg += 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 	set_idx_reg(ep->dev->regs, reg, max);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #endif	/* __KERNEL__ */