^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * M66592 UDC (USB gadget)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2006-2007 Renesas Solutions Corp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author : Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #ifndef __M66592_UDC_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define __M66592_UDC_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/usb/m66592.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define M66592_SYSCFG 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define M66592_XTAL 0xC000 /* b15-14: Crystal selection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define M66592_XTAL48 0x8000 /* 48MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define M66592_XTAL24 0x4000 /* 24MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define M66592_XTAL12 0x0000 /* 12MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define M66592_XCKE 0x2000 /* b13: External clock enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define M66592_RCKE 0x1000 /* b12: Register clock enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define M66592_PLLC 0x0800 /* b11: PLL control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define M66592_SCKE 0x0400 /* b10: USB clock enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define M66592_ATCKM 0x0100 /* b8: Automatic clock supply */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define M66592_HSE 0x0080 /* b7: Hi-speed enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define M66592_DCFM 0x0040 /* b6: Controller function select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define M66592_DMRPD 0x0020 /* b5: D- pull down control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define M66592_DPRPU 0x0010 /* b4: D+ pull up control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define M66592_FSRPC 0x0004 /* b2: Full-speed receiver enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define M66592_PCUT 0x0002 /* b1: Low power sleep enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define M66592_USBE 0x0001 /* b0: USB module operation enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define M66592_SYSSTS 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define M66592_LNST 0x0003 /* b1-0: D+, D- line status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define M66592_SE1 0x0003 /* SE1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define M66592_KSTS 0x0002 /* K State */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define M66592_JSTS 0x0001 /* J State */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define M66592_SE0 0x0000 /* SE0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define M66592_DVSTCTR 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define M66592_WKUP 0x0100 /* b8: Remote wakeup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define M66592_RWUPE 0x0080 /* b7: Remote wakeup sense */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define M66592_USBRST 0x0040 /* b6: USB reset enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define M66592_RESUME 0x0020 /* b5: Resume enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define M66592_UACT 0x0010 /* b4: USB bus enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define M66592_RHST 0x0003 /* b1-0: Reset handshake status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define M66592_HSMODE 0x0003 /* Hi-Speed mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define M66592_FSMODE 0x0002 /* Full-Speed mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define M66592_HSPROC 0x0001 /* HS handshake is processing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define M66592_TESTMODE 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define M66592_UTST 0x000F /* b4-0: Test select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define M66592_H_TST_PACKET 0x000C /* HOST TEST Packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define M66592_H_TST_SE0_NAK 0x000B /* HOST TEST SE0 NAK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define M66592_H_TST_K 0x000A /* HOST TEST K */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define M66592_H_TST_J 0x0009 /* HOST TEST J */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define M66592_H_TST_NORMAL 0x0000 /* HOST Normal Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define M66592_P_TST_PACKET 0x0004 /* PERI TEST Packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define M66592_P_TST_SE0_NAK 0x0003 /* PERI TEST SE0 NAK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define M66592_P_TST_K 0x0002 /* PERI TEST K */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define M66592_P_TST_J 0x0001 /* PERI TEST J */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define M66592_P_TST_NORMAL 0x0000 /* PERI Normal Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /* built-in registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define M66592_CFBCFG 0x0A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define M66592_D0FBCFG 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define M66592_LITTLE 0x0100 /* b8: Little endian mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /* external chip case */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define M66592_PINCFG 0x0A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define M66592_LDRV 0x8000 /* b15: Drive Current Adjust */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define M66592_BIGEND 0x0100 /* b8: Big endian mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define M66592_DMA0CFG 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define M66592_DMA1CFG 0x0E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define M66592_DREQA 0x4000 /* b14: Dreq active select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define M66592_BURST 0x2000 /* b13: Burst mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define M66592_DACKA 0x0400 /* b10: Dack active select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define M66592_DFORM 0x0380 /* b9-7: DMA mode select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define M66592_CPU_ADR_RD_WR 0x0000 /* Address + RD/WR mode (CPU bus) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define M66592_CPU_DACK_RD_WR 0x0100 /* DACK + RD/WR mode (CPU bus) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define M66592_CPU_DACK_ONLY 0x0180 /* DACK only mode (CPU bus) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define M66592_SPLIT_DACK_ONLY 0x0200 /* DACK only mode (SPLIT bus) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define M66592_SPLIT_DACK_DSTB 0x0300 /* DACK + DSTB0 mode (SPLIT bus) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define M66592_DENDA 0x0040 /* b6: Dend active select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define M66592_PKTM 0x0020 /* b5: Packet mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define M66592_DENDE 0x0010 /* b4: Dend enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define M66592_OBUS 0x0004 /* b2: OUTbus mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /* common case */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define M66592_CFIFO 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define M66592_D0FIFO 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define M66592_D1FIFO 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define M66592_CFIFOSEL 0x1E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define M66592_D0FIFOSEL 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define M66592_D1FIFOSEL 0x2A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define M66592_RCNT 0x8000 /* b15: Read count mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define M66592_REW 0x4000 /* b14: Buffer rewind */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define M66592_DCLRM 0x2000 /* b13: DMA buffer clear mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define M66592_DREQE 0x1000 /* b12: DREQ output enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define M66592_MBW_8 0x0000 /* 8bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define M66592_MBW_16 0x0400 /* 16bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define M66592_MBW_32 0x0800 /* 32bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define M66592_TRENB 0x0200 /* b9: Transaction counter enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define M66592_TRCLR 0x0100 /* b8: Transaction counter clear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define M66592_DEZPM 0x0080 /* b7: Zero-length packet mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define M66592_ISEL 0x0020 /* b5: DCP FIFO port direction select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define M66592_CURPIPE 0x0007 /* b2-0: PIPE select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define M66592_CFIFOCTR 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define M66592_D0FIFOCTR 0x26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define M66592_D1FIFOCTR 0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define M66592_BVAL 0x8000 /* b15: Buffer valid flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define M66592_BCLR 0x4000 /* b14: Buffer clear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define M66592_FRDY 0x2000 /* b13: FIFO ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define M66592_DTLN 0x0FFF /* b11-0: FIFO received data length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define M66592_CFIFOSIE 0x22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define M66592_TGL 0x8000 /* b15: Buffer toggle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define M66592_SCLR 0x4000 /* b14: Buffer clear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define M66592_SBUSY 0x2000 /* b13: SIE_FIFO busy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define M66592_D0FIFOTRN 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define M66592_D1FIFOTRN 0x2E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define M66592_TRNCNT 0xFFFF /* b15-0: Transaction counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define M66592_INTENB0 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define M66592_VBSE 0x8000 /* b15: VBUS interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define M66592_RSME 0x4000 /* b14: Resume interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define M66592_SOFE 0x2000 /* b13: Frame update interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define M66592_DVSE 0x1000 /* b12: Device state transition interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define M66592_CTRE 0x0800 /* b11: Control transfer stage transition irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define M66592_BEMPE 0x0400 /* b10: Buffer empty interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define M66592_NRDYE 0x0200 /* b9: Buffer not ready interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define M66592_BRDYE 0x0100 /* b8: Buffer ready interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define M66592_URST 0x0080 /* b7: USB reset detected interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define M66592_SADR 0x0040 /* b6: Set address executed interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define M66592_SCFG 0x0020 /* b5: Set configuration executed interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define M66592_SUSP 0x0010 /* b4: Suspend detected interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define M66592_WDST 0x0008 /* b3: Control write data stage completed irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define M66592_RDST 0x0004 /* b2: Control read data stage completed irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define M66592_CMPL 0x0002 /* b1: Control transfer complete interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define M66592_SERR 0x0001 /* b0: Sequence error interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define M66592_INTENB1 0x32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define M66592_BCHGE 0x4000 /* b14: USB us chenge interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define M66592_DTCHE 0x1000 /* b12: Detach sense interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define M66592_SIGNE 0x0020 /* b5: SETUP IGNORE interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define M66592_SACKE 0x0010 /* b4: SETUP ACK interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define M66592_BRDYM 0x0004 /* b2: BRDY clear timing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define M66592_INTL 0x0002 /* b1: Interrupt sense select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define M66592_PCSE 0x0001 /* b0: PCUT enable by CS assert */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define M66592_BRDYENB 0x36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define M66592_BRDYSTS 0x46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define M66592_BRDY7 0x0080 /* b7: PIPE7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define M66592_BRDY6 0x0040 /* b6: PIPE6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define M66592_BRDY5 0x0020 /* b5: PIPE5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define M66592_BRDY4 0x0010 /* b4: PIPE4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define M66592_BRDY3 0x0008 /* b3: PIPE3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define M66592_BRDY2 0x0004 /* b2: PIPE2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define M66592_BRDY1 0x0002 /* b1: PIPE1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define M66592_BRDY0 0x0001 /* b1: PIPE0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define M66592_NRDYENB 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define M66592_NRDYSTS 0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define M66592_NRDY7 0x0080 /* b7: PIPE7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define M66592_NRDY6 0x0040 /* b6: PIPE6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define M66592_NRDY5 0x0020 /* b5: PIPE5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define M66592_NRDY4 0x0010 /* b4: PIPE4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define M66592_NRDY3 0x0008 /* b3: PIPE3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define M66592_NRDY2 0x0004 /* b2: PIPE2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define M66592_NRDY1 0x0002 /* b1: PIPE1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define M66592_NRDY0 0x0001 /* b1: PIPE0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define M66592_BEMPENB 0x3A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define M66592_BEMPSTS 0x4A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define M66592_BEMP7 0x0080 /* b7: PIPE7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define M66592_BEMP6 0x0040 /* b6: PIPE6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define M66592_BEMP5 0x0020 /* b5: PIPE5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define M66592_BEMP4 0x0010 /* b4: PIPE4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define M66592_BEMP3 0x0008 /* b3: PIPE3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define M66592_BEMP2 0x0004 /* b2: PIPE2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define M66592_BEMP1 0x0002 /* b1: PIPE1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define M66592_BEMP0 0x0001 /* b0: PIPE0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define M66592_SOFCFG 0x3C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define M66592_SOFM 0x000C /* b3-2: SOF palse mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define M66592_SOF_125US 0x0008 /* SOF OUT 125us uFrame Signal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define M66592_SOF_1MS 0x0004 /* SOF OUT 1ms Frame Signal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define M66592_SOF_DISABLE 0x0000 /* SOF OUT Disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define M66592_INTSTS0 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define M66592_VBINT 0x8000 /* b15: VBUS interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define M66592_RESM 0x4000 /* b14: Resume interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define M66592_SOFR 0x2000 /* b13: SOF frame update interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define M66592_DVST 0x1000 /* b12: Device state transition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define M66592_CTRT 0x0800 /* b11: Control stage transition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define M66592_BEMP 0x0400 /* b10: Buffer empty interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define M66592_NRDY 0x0200 /* b9: Buffer not ready interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define M66592_BRDY 0x0100 /* b8: Buffer ready interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define M66592_VBSTS 0x0080 /* b7: VBUS input port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define M66592_DVSQ 0x0070 /* b6-4: Device state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define M66592_DS_SPD_CNFG 0x0070 /* Suspend Configured */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define M66592_DS_SPD_ADDR 0x0060 /* Suspend Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define M66592_DS_SPD_DFLT 0x0050 /* Suspend Default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define M66592_DS_SPD_POWR 0x0040 /* Suspend Powered */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define M66592_DS_SUSP 0x0040 /* Suspend */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define M66592_DS_CNFG 0x0030 /* Configured */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define M66592_DS_ADDS 0x0020 /* Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define M66592_DS_DFLT 0x0010 /* Default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define M66592_DS_POWR 0x0000 /* Powered */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define M66592_DVSQS 0x0030 /* b5-4: Device state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define M66592_VALID 0x0008 /* b3: Setup packet detected flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define M66592_CTSQ 0x0007 /* b2-0: Control transfer stage */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define M66592_CS_SQER 0x0006 /* Sequence error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define M66592_CS_WRND 0x0005 /* Control write nodata status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define M66592_CS_WRSS 0x0004 /* Control write status stage */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define M66592_CS_WRDS 0x0003 /* Control write data stage */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define M66592_CS_RDSS 0x0002 /* Control read status stage */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define M66592_CS_RDDS 0x0001 /* Control read data stage */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define M66592_CS_IDST 0x0000 /* Idle or setup stage */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define M66592_INTSTS1 0x42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define M66592_BCHG 0x4000 /* b14: USB bus chenge interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define M66592_DTCH 0x1000 /* b12: Detach sense interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define M66592_SIGN 0x0020 /* b5: SETUP IGNORE interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define M66592_SACK 0x0010 /* b4: SETUP ACK interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define M66592_FRMNUM 0x4C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define M66592_OVRN 0x8000 /* b15: Overrun error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define M66592_CRCE 0x4000 /* b14: Received data error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define M66592_SOFRM 0x0800 /* b11: SOF output mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define M66592_FRNM 0x07FF /* b10-0: Frame number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define M66592_UFRMNUM 0x4E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define M66592_UFRNM 0x0007 /* b2-0: Micro frame number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define M66592_RECOVER 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define M66592_STSRECOV 0x0700 /* Status recovery */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define M66592_STSR_HI 0x0400 /* FULL(0) or HI(1) Speed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define M66592_STSR_DEFAULT 0x0100 /* Default state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define M66592_STSR_ADDRESS 0x0200 /* Address state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define M66592_STSR_CONFIG 0x0300 /* Configured state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define M66592_USBADDR 0x007F /* b6-0: USB address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define M66592_USBREQ 0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define M66592_bRequest 0xFF00 /* b15-8: bRequest */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define M66592_GET_STATUS 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define M66592_CLEAR_FEATURE 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define M66592_ReqRESERVED 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define M66592_SET_FEATURE 0x0300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define M66592_ReqRESERVED1 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define M66592_SET_ADDRESS 0x0500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define M66592_GET_DESCRIPTOR 0x0600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define M66592_SET_DESCRIPTOR 0x0700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define M66592_GET_CONFIGURATION 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define M66592_SET_CONFIGURATION 0x0900
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define M66592_GET_INTERFACE 0x0A00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define M66592_SET_INTERFACE 0x0B00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define M66592_SYNCH_FRAME 0x0C00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define M66592_bmRequestType 0x00FF /* b7-0: bmRequestType */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define M66592_bmRequestTypeDir 0x0080 /* b7 : Data direction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define M66592_HOST_TO_DEVICE 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define M66592_DEVICE_TO_HOST 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define M66592_bmRequestTypeType 0x0060 /* b6-5: Type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define M66592_STANDARD 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define M66592_CLASS 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define M66592_VENDOR 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define M66592_bmRequestTypeRecip 0x001F /* b4-0: Recipient */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define M66592_DEVICE 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define M66592_INTERFACE 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define M66592_ENDPOINT 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define M66592_USBVAL 0x56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define M66592_wValue 0xFFFF /* b15-0: wValue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) /* Standard Feature Selector */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define M66592_ENDPOINT_HALT 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define M66592_DEVICE_REMOTE_WAKEUP 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define M66592_TEST_MODE 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) /* Descriptor Types */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define M66592_DT_TYPE 0xFF00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define M66592_GET_DT_TYPE(v) (((v) & DT_TYPE) >> 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define M66592_DT_DEVICE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define M66592_DT_CONFIGURATION 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define M66592_DT_STRING 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define M66592_DT_INTERFACE 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define M66592_DT_ENDPOINT 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define M66592_DT_DEVICE_QUALIFIER 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define M66592_DT_OTHER_SPEED_CONFIGURATION 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define M66592_DT_INTERFACE_POWER 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define M66592_DT_INDEX 0x00FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define M66592_CONF_NUM 0x00FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define M66592_ALT_SET 0x00FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define M66592_USBINDEX 0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define M66592_wIndex 0xFFFF /* b15-0: wIndex */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define M66592_TEST_SELECT 0xFF00 /* b15-b8: Test Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define M66592_TEST_J 0x0100 /* Test_J */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define M66592_TEST_K 0x0200 /* Test_K */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define M66592_TEST_SE0_NAK 0x0300 /* Test_SE0_NAK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define M66592_TEST_PACKET 0x0400 /* Test_Packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define M66592_TEST_FORCE_ENABLE 0x0500 /* Test_Force_Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define M66592_TEST_STSelectors 0x0600 /* Standard test selectors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define M66592_TEST_Reserved 0x4000 /* Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define M66592_TEST_VSTModes 0xC000 /* Vendor-specific tests */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define M66592_EP_DIR 0x0080 /* b7: Endpoint Direction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define M66592_EP_DIR_IN 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define M66592_EP_DIR_OUT 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define M66592_USBLENG 0x5A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define M66592_wLength 0xFFFF /* b15-0: wLength */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define M66592_DCPCFG 0x5C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define M66592_CNTMD 0x0100 /* b8: Continuous transfer mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define M66592_DIR 0x0010 /* b4: Control transfer DIR select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define M66592_DCPMAXP 0x5E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define M66592_DEVSEL 0xC000 /* b15-14: Device address select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define M66592_DEVICE_0 0x0000 /* Device address 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define M66592_DEVICE_1 0x4000 /* Device address 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define M66592_DEVICE_2 0x8000 /* Device address 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define M66592_DEVICE_3 0xC000 /* Device address 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define M66592_MAXP 0x007F /* b6-0: Maxpacket size of ep0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define M66592_DCPCTR 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define M66592_BSTS 0x8000 /* b15: Buffer status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define M66592_SUREQ 0x4000 /* b14: Send USB request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define M66592_SQCLR 0x0100 /* b8: Sequence toggle bit clear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define M66592_SQSET 0x0080 /* b7: Sequence toggle bit set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define M66592_SQMON 0x0040 /* b6: Sequence toggle bit monitor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define M66592_CCPL 0x0004 /* b2: control transfer complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define M66592_PID 0x0003 /* b1-0: Response PID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define M66592_PID_STALL 0x0002 /* STALL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define M66592_PID_BUF 0x0001 /* BUF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define M66592_PID_NAK 0x0000 /* NAK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define M66592_PIPESEL 0x64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define M66592_PIPENM 0x0007 /* b2-0: Pipe select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define M66592_PIPE0 0x0000 /* PIPE 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define M66592_PIPE1 0x0001 /* PIPE 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define M66592_PIPE2 0x0002 /* PIPE 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define M66592_PIPE3 0x0003 /* PIPE 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define M66592_PIPE4 0x0004 /* PIPE 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define M66592_PIPE5 0x0005 /* PIPE 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define M66592_PIPE6 0x0006 /* PIPE 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define M66592_PIPE7 0x0007 /* PIPE 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define M66592_PIPECFG 0x66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define M66592_TYP 0xC000 /* b15-14: Transfer type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define M66592_ISO 0xC000 /* Isochronous */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define M66592_INT 0x8000 /* Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define M66592_BULK 0x4000 /* Bulk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define M66592_BFRE 0x0400 /* b10: Buffer ready interrupt mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define M66592_DBLB 0x0200 /* b9: Double buffer mode select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define M66592_CNTMD 0x0100 /* b8: Continuous transfer mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define M66592_SHTNAK 0x0080 /* b7: Transfer end NAK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define M66592_DIR 0x0010 /* b4: Transfer direction select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define M66592_DIR_H_OUT 0x0010 /* HOST OUT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define M66592_DIR_P_IN 0x0010 /* PERI IN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define M66592_DIR_H_IN 0x0000 /* HOST IN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define M66592_DIR_P_OUT 0x0000 /* PERI OUT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define M66592_EPNUM 0x000F /* b3-0: Eendpoint number select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define M66592_EP1 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define M66592_EP2 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define M66592_EP3 0x0003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define M66592_EP4 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define M66592_EP5 0x0005
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define M66592_EP6 0x0006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define M66592_EP7 0x0007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define M66592_EP8 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define M66592_EP9 0x0009
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define M66592_EP10 0x000A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define M66592_EP11 0x000B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define M66592_EP12 0x000C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define M66592_EP13 0x000D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define M66592_EP14 0x000E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define M66592_EP15 0x000F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define M66592_PIPEBUF 0x68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define M66592_BUFSIZE 0x7C00 /* b14-10: Pipe buffer size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define M66592_BUF_SIZE(x) ((((x) / 64) - 1) << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define M66592_BUFNMB 0x00FF /* b7-0: Pipe buffer number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define M66592_PIPEMAXP 0x6A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #define M66592_MXPS 0x07FF /* b10-0: Maxpacket size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define M66592_PIPEPERI 0x6C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define M66592_IFIS 0x1000 /* b12: ISO in-buffer flush mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define M66592_IITV 0x0007 /* b2-0: ISO interval */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define M66592_PIPE1CTR 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define M66592_PIPE2CTR 0x72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #define M66592_PIPE3CTR 0x74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #define M66592_PIPE4CTR 0x76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #define M66592_PIPE5CTR 0x78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define M66592_PIPE6CTR 0x7A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define M66592_PIPE7CTR 0x7C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define M66592_BSTS 0x8000 /* b15: Buffer status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #define M66592_INBUFM 0x4000 /* b14: IN buffer monitor (PIPE 1-5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #define M66592_ACLRM 0x0200 /* b9: Out buffer auto clear mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define M66592_SQCLR 0x0100 /* b8: Sequence toggle bit clear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #define M66592_SQSET 0x0080 /* b7: Sequence toggle bit set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #define M66592_SQMON 0x0040 /* b6: Sequence toggle bit monitor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define M66592_PID 0x0003 /* b1-0: Response PID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #define M66592_INVALID_REG 0x7E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #define get_pipectr_addr(pipenum) (M66592_PIPE1CTR + (pipenum - 1) * 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #define M66592_MAX_SAMPLING 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #define M66592_MAX_NUM_PIPE 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) #define M66592_MAX_NUM_BULK 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) #define M66592_MAX_NUM_ISOC 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) #define M66592_MAX_NUM_INT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) #define M66592_BASE_PIPENUM_BULK 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) #define M66592_BASE_PIPENUM_ISOC 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #define M66592_BASE_PIPENUM_INT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) #define M66592_BASE_BUFNUM 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) #define M66592_MAX_BUFNUM 0x4F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) struct m66592_pipe_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) u16 pipe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) u16 epnum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) u16 maxpacket;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) u16 type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) u16 interval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) u16 dir_in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) struct m66592_request {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) struct usb_request req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) struct list_head queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) struct m66592_ep {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) struct usb_ep ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) struct m66592 *m66592;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) struct list_head queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) unsigned busy:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) unsigned internal_ccpl:1; /* use only control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) /* this member can able to after m66592_enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) unsigned use_dma:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) u16 pipenum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) u16 type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) /* register address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) unsigned long fifoaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) unsigned long fifosel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) unsigned long fifoctr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) unsigned long fifotrn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) unsigned long pipectr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) struct m66592 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) void __iomem *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) struct m66592_platdata *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) unsigned long irq_trigger;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) struct usb_gadget gadget;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) struct usb_gadget_driver *driver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) struct m66592_ep ep[M66592_MAX_NUM_PIPE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) struct m66592_ep *pipenum2ep[M66592_MAX_NUM_PIPE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) struct m66592_ep *epaddr2ep[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) struct usb_request *ep0_req; /* for internal request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) __le16 ep0_data; /* for internal request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) u16 old_vbus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) struct timer_list timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) int scount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) int old_dvsq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) /* pipe config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) int bulk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) int interrupt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) int isochronous;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) int num_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) #define to_m66592(g) (container_of((g), struct m66592, gadget))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) #define gadget_to_m66592(_gadget) container_of(_gadget, struct m66592, gadget)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) #define m66592_to_gadget(m66592) (&m66592->gadget)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) #define is_bulk_pipe(pipenum) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) ((pipenum >= M66592_BASE_PIPENUM_BULK) && \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) (pipenum < (M66592_BASE_PIPENUM_BULK + M66592_MAX_NUM_BULK)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) #define is_interrupt_pipe(pipenum) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) ((pipenum >= M66592_BASE_PIPENUM_INT) && \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) (pipenum < (M66592_BASE_PIPENUM_INT + M66592_MAX_NUM_INT)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) #define is_isoc_pipe(pipenum) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) ((pipenum >= M66592_BASE_PIPENUM_ISOC) && \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) (pipenum < (M66592_BASE_PIPENUM_ISOC + M66592_MAX_NUM_ISOC)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) #define enable_irq_ready(m66592, pipenum) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) enable_pipe_irq(m66592, pipenum, M66592_BRDYENB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) #define disable_irq_ready(m66592, pipenum) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) disable_pipe_irq(m66592, pipenum, M66592_BRDYENB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) #define enable_irq_empty(m66592, pipenum) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) enable_pipe_irq(m66592, pipenum, M66592_BEMPENB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) #define disable_irq_empty(m66592, pipenum) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) disable_pipe_irq(m66592, pipenum, M66592_BEMPENB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) #define enable_irq_nrdy(m66592, pipenum) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) enable_pipe_irq(m66592, pipenum, M66592_NRDYENB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) #define disable_irq_nrdy(m66592, pipenum) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) disable_pipe_irq(m66592, pipenum, M66592_NRDYENB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) /*-------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) static inline u16 m66592_read(struct m66592 *m66592, unsigned long offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) return ioread16(m66592->reg + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) static inline void m66592_read_fifo(struct m66592 *m66592,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) unsigned long offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) void *buf, unsigned long len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) void __iomem *fifoaddr = m66592->reg + offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) if (m66592->pdata->on_chip) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) len = (len + 3) / 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) ioread32_rep(fifoaddr, buf, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) len = (len + 1) / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) ioread16_rep(fifoaddr, buf, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) static inline void m66592_write(struct m66592 *m66592, u16 val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) unsigned long offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) iowrite16(val, m66592->reg + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) static inline void m66592_mdfy(struct m66592 *m66592, u16 val, u16 pat,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) unsigned long offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) u16 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) tmp = m66592_read(m66592, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) tmp = tmp & (~pat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) tmp = tmp | val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) m66592_write(m66592, tmp, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) #define m66592_bclr(m66592, val, offset) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) m66592_mdfy(m66592, 0, val, offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) #define m66592_bset(m66592, val, offset) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) m66592_mdfy(m66592, val, 0, offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) static inline void m66592_write_fifo(struct m66592 *m66592,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) struct m66592_ep *ep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) void *buf, unsigned long len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) void __iomem *fifoaddr = m66592->reg + ep->fifoaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) if (m66592->pdata->on_chip) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) unsigned long count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) unsigned char *pb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) count = len / 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) iowrite32_rep(fifoaddr, buf, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) if (len & 0x00000003) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) pb = buf + count * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) for (i = 0; i < (len & 0x00000003); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) if (m66592_read(m66592, M66592_CFBCFG)) /* le */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) iowrite8(pb[i], fifoaddr + (3 - i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) iowrite8(pb[i], fifoaddr + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) unsigned long odd = len & 0x0001;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) len = len / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) iowrite16_rep(fifoaddr, buf, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) if (odd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) unsigned char *p = buf + len*2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) if (m66592->pdata->wr0_shorted_to_wr1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) m66592_bclr(m66592, M66592_MBW_16, ep->fifosel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) iowrite8(*p, fifoaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) if (m66592->pdata->wr0_shorted_to_wr1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) m66592_bset(m66592, M66592_MBW_16, ep->fifosel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) #endif /* ifndef __M66592_UDC_H__ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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